Use MATLAB to Debug your SoC IP Core/technologies/fpga-group/b/blog/posts/use-matlab-to-debug-your-soc-ip-coreRecently I discovered a clever way in MATLAB to interact with my HDL IP cores in situ, running in the programmable logic. Yes, of course, there are many ways to probe logic in an FPGA, but this one is particularly helpful when I need to analyze bits en-USTelligent Community 12RE: Use MATLAB to Debug your SoC IP Corehttps://community.element14.com/technologies/fpga-group/b/blog/posts/use-matlab-to-debug-your-soc-ip-coreThu, 03 May 2018 11:13:52 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:cb432d05-041d-458b-b0f4-eeaaf6a6e6dcrachaelp0<p>Oh this looks very cool! I&#39;m planning to get back into some more serious FPGA design this year as it&#39;s been too long since I did a really big FPGA design and I was also looking at MatLab and this seems like a good <span style="text-decoration:line-through;">excuse</span> justification for spending the money on a MatLab license!</p><img src="https://community.element14.com/aggbug?PostID=4728&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">