/technologies/fpga-group/b/blog/posts/lpddr4-timing-parameters-for-zynq-ultrascale-mpsoc-in-vivado-based-on-ultra96Note: The v1.0 Ultra96 board definition files (BDF) embedded in Vivado 2018.1 and 2018.2 have a bug. The latest BDF is on the Avnet GitHub here: https://github.com/Avnet/bdf . The article below describes the parameters included in the v1.2 board defien-USTelligent Community 12