The Art of FPGA Design - Post 3

RE: The Art of FPGA Design - Post 3

gustavovelascoh — Tue, 10 Nov 2020 10:18:45 GMT

Hi Catalin, thanks for your series of posts on FPGA. I will give FPGA a try (again). On this post you mentioned that HLS design flow is good in terms of abstraction, simulation time and time to market, but poor in performance. Is this still the case today (2 years after)? Thanks

RE: The Art of FPGA Design - Post 3

johnbeetem — Thu, 26 Jul 2018 16:16:53 GMT

Oh goody, Language Wars!

We've had some interesting discussions of the years here in the FPGA Group about Verilog and VHDL. Here are a couple of 2014 discussions I found this morning:

Alternatives to VHDL/Verilog for hardware design

Connecting Verilog to Synthesis

I'm going to repeat part of a comment I made in the first discussion:

I don't like Verilog or VHDL. Given the choice, I mostly use Verilog since I don't want to type more than necessary and I have limited storage space for listings.

My main problem with Verilog and VHDL is that they were designed for simulation. Synthesis was added as an afterthought. It's quite difficult for an inexperienced user to know how to write Verilog to get the synthesizer (I mostly use Xilinx's XST) to create the logic the user wants. XST matches "language templates" to find things like flip-flops, registers, and RAMs. "Language templates" are hidden in ISE's Edit menu. Many new users don't know about the templates, and merrily write Verilog or VHDL from textbooks and it simulates fine. Then they try to synthesize and get frustrated.

Here's how I write Verilog: I imagine what hardware I want, and then I write my Verilog to match the template for each piece of hardware. This is basically compiling in reverse: you imagine the object code, and then write your source code so that the compiler does the right thing. I'm probably better at this than most designers since I've written compilers and digital design tools, so it's easy for me to guess at what Xilinx tools do.

The second discussion is a typical example of what happens when a new user takes Verilog that simulates correctly and tries to synthesize.

Of the commercial HDLs I've used over the years, my favorite is AHDL (Altera's HDL). It let me describe the hardware I wanted more easily and I didn't have to jump through hoops to cajole the synthesizer into doing what I wanted.

RE: The Art of FPGA Design - Post 3

DAB — Tue, 24 Jul 2018 18:17:37 GMT

Yes, I remember the wars well.

The die hard hardware folks were very biased about any "software" like description language for implementing the sacred hardware circuits.

To be fair, their were equal battles among the various software languages and passions ran very high.

As a systems engineer, I readily saw the value of circuit description languages, and as the lines of software and hardware blurred, I found it very useful that everyone was using similar constructs to describe what the entire system was intended to do. The similarities allowed both sides to easily agree to where the logic transitioned between subsystems.

DAB