/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-7We&#39;re Not in Kansas Anymore In this post we will try to do things you probably never tried to do using VHDL, assuming they were not even possible in such a low level language. VHDL and Verilog/SystemVerilog are considered low level hardware...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-7Tue, 13 Dec 2022 22:03:20 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:e9feba35-bc89-45d0-a6f3-be688e5dc0f0miki0<p>Thank you for the great article, coming in to FPGAs from a software engineering role I was under the (incorrect) assumption that these kinds of things are not possible in VHDL,<br />I&#39;m glad that I&#39;ve been wrong.</p><img src="https://community.element14.com/aggbug?PostID=5383&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-7Tue, 21 Aug 2018 18:01:32 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:e9feba35-bc89-45d0-a6f3-be688e5dc0f0DAB1<p>I think it would help the reader is you included some pictures of the overall circuit that you are implementing here.</p><p>I understand the various data types, but being able to see the circuit would help me understand why there is an issue here with respect to VHDL.</p><p>&nbsp;</p><p>DAB</p><img src="https://community.element14.com/aggbug?PostID=5383&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">