<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design - Post 8</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-8</link><description>The Universal DELAY Building Block This is the first post in this blog in which I will try to actually design something useful based on the ideas introduced so far. Also, instead of just short code snippets, the code examples in this post are co...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: The Art of FPGA Design - Post 8</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-8</link><pubDate>Thu, 05 Nov 2020 13:25:48 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3d438328-e3c4-45da-a18b-49ff4c426740</guid><dc:creator>amkichu</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;When I try to synthesize or simulate SDELY module, I receive the following error from Vivado.&lt;/p&gt;&lt;p&gt;[Synth 8-2190] illegal syntax for subtype indication ["K:/Projects/0_Personal/FPGA/Design/13_art/hdl/SDELAY.vhd":12]&lt;/p&gt;&lt;p&gt;=&amp;gt; &lt;span style="font-weight:inherit;font-style:inherit;"&gt;signal&lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt; D:SFIXED_VECTOR(&lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt;0 &lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt;to&lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt; SIZE)(I&amp;#39;range):=(&lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt;others&lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt;=&amp;gt;TO_SFIXED(&lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt;0.0,I&lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt;)); &lt;/span&gt;&lt;span style="font-weight:inherit;font-style:inherit;"&gt;–- delay line signal is SIZE+1 in length &lt;/span&gt;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;What is this error and how can I fix it?&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5413&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: The Art of FPGA Design - Post 8</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-8</link><pubDate>Tue, 28 Aug 2018 19:09:07 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3d438328-e3c4-45da-a18b-49ff4c426740</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Very nice example.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;DAB&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5413&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>