<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design - Post 10</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-10</link><description>Instantiating LUT6 Primitives In the previous post we have already seen how to instantiate FPGA primitives, SRL16s in that case. The role of the synthesis tool is to take HDL behavioral code and translate it into a netlist of FPGA fundamental bu...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: The Art of FPGA Design - Post 10</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-10</link><pubDate>Tue, 11 Sep 2018 19:45:10 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:0b08ec0f-90d7-4458-82d3-931361ddc073</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice post.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;DAB&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5482&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>