<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design - Post 11</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-11</link><description>Instantiating LUT6 Primitives Part 2 Today I will show a couple of examples where LUT6 primitive instantiations make sense. To keep things short and simple these are somewhat artificial examples but situations like these tend to show up all the ...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: The Art of FPGA Design - Post 11</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-11</link><pubDate>Tue, 18 Sep 2018 18:33:56 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:e1a51d9d-7c0f-483f-b9a4-11714dfdf365</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Good example.&lt;/p&gt;&lt;p&gt;Sometimes adding complexity works well, but you always have to keep the detail in mind while you map out the FPGA circuit.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;DAB&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5545&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>