Integrating a Microchip Gigabit Ethernet PHY into the Xilinx FPGA Ecosystem - Hardware/technologies/fpga-group/b/blog/posts/integrating-a-microchip-gigabit-ethernet-phy-into-the-xilinx-fpga-ecosystem---hardwareHave you ever wanted to integrate a Microchip PHY into the Xilinx Ecosystem, but previously had no proven reference designs available to mitigate risk factors? Recently Avnet released the Network FMC ( http://avnet.me/fmc-network1 ), which is a dual Men-USTelligent Community 12RE: Integrating a Microchip Gigabit Ethernet PHY into the Xilinx FPGA Ecosystem - Hardwarehttps://community.element14.com/technologies/fpga-group/b/blog/posts/integrating-a-microchip-gigabit-ethernet-phy-into-the-xilinx-fpga-ecosystem---hardwareThu, 20 Sep 2018 17:09:20 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:aafe405c-b4da-4529-84fc-074b305e4fe9michaelkellett1<p>Interesting article - I think you must work for Avnet - can you confirm that ?</p><p>&nbsp;</p><p>I&#39;ve done a similar job (KSZ9567R 7 port switch direct to Xilinx Artix FPGA). I wish I&#39;d known about the Microchip LAN check - they might have spotted the data scrambling on the RGMII interface (easy enough to fix in the FPGA but it took a lot of effort to locate and prove !).</p><p>&nbsp;</p><p>MK</p><img src="https://community.element14.com/aggbug?PostID=5554&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">