<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design - Post 20</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-20</link><description>The DSP48 Primitive This post will start a longer series dedicated to the DSP48 primitive, a MAC (multiply/accumulate) block which is the workhorse for any kind of signal processing design that requires lots of mathematical operations beyond sim...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: The Art of FPGA Design - Post 20</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-20</link><pubDate>Mon, 10 Apr 2023 07:22:48 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:63c04d9d-8007-4096-89e5-43e4e5186c15</guid><dc:creator>RAJAT99</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;&lt;span&gt;Avnet boards come with speed grade -1, -2 etc. What does it mean?&lt;/span&gt;&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5957&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>