<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design - Post 23</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-23</link><description>The DSP48 Primitive - Instantiating the DSP48 Behavioral inference has many advantages - relatively simple and compact code, works with signed and unsigned operands of any size, hides the intricacies of the DSP48 primitive from the user. It shou...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: The Art of FPGA Design - Post 23</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-23</link><pubDate>Tue, 11 Dec 2018 20:31:26 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:97568ce9-5b12-4d2e-ba19-4a76eddd0a6b</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice update,&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;You are doing a great job of showing people how you have to carefully plan your FPGA build and implement it in a careful way.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;DAB&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=6092&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>