<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design - Post 24</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-24</link><description>The DSP48 Primitive - FIR with DSP48 Primitive Instantiations After a break I will be resuming my weekly posts on The Art of FPGA Design. In the last posts we started looking at the DSP48 primitive, essentially a signed 27x18 multiplier which al...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>