<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design - Post 33</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-33</link><description>Sorting Networks - The Batcher or odd-even mergesort sorting algorithm Now that we have defined the FPGA design engineering problem - parallel sorting of a set of N items in one clock, that is one new sorting operation starting every clock - we ...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: The Art of FPGA Design - Post 33</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-33</link><pubDate>Tue, 02 Jul 2019 18:19:07 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:4ce48c49-319a-4acf-ba8a-a85030ce0bed</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Good overview of the algorithm.&lt;/p&gt;&lt;p&gt;I look forward to seeing your implementation.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;DAB&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=7379&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>