The Art of FPGA Design - Post 34

The Art of FPGA Design - Post 34/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-34Sorting Networks - The VHDL implementation of Batcher's sorting algorithm OK, enough with the preliminaries, it's time now for the real deal, how do we implement in an FPGA this parallel sorting network thing. The main design goals are creating ...en-USTelligent Community 12RE: The Art of FPGA Design - Post 34https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-34Mon, 08 Jul 2019 19:42:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:17c9e048-9c4c-4d8c-8a00-936c7786530fDAB1<p>Nice post.</p><p> </p><p>Are you going to work through a timing diagram for this algorithm?</p><p> </p><p>DAB</p><img src="https://community.element14.com/aggbug?PostID=7411&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">