RE: FPGA: Waves 2: Simple Sinewave

neuromodulator — Sun, 22 Sep 2019 00:25:39 GMT

Taking advantage of the symmetry of sin/cos, and through interpolation you could significantly reduce the LUT size. Alternatively you could also use CORDIC.

RE: FPGA: Waves 2: Simple Sinewave

michaelkellett — Sat, 21 Sep 2019 10:07:19 GMT

Now you've done it the hard way - try the other way:

https://forums.xilinx.com/t5/DSP-IP-and-Tools/Generating-SIne-Wave/td-p/53120

(scroll all the way down to Eilert's reply where you'll find this gem:

BEGIN -- PROCESS sinegen

IF reset = '0' THEN -- asynchronous reset (active low)

mult := (OTHERS => '0');

sine := (OTHERS => '0');

n1 := (OTHERS => '0');

n2 := (OTHERS => '0');

alfa := (OTHERS => '0');

ELSIF clock'event AND clock = '1' THEN -- rising clock edge

IF load='1' THEN

n2 := beta; --use in port later

alfa := alpha; --use in port later

ELSE

mult := alfa * n1;

sine := mult(45 DOWNTO 45-24) - n2;

n2 := n1;

n1 := sine;

END IF;

END PROCESS sinegen;

It will give you chance to use the multipliers rather than the look up tables.

This might help explain a bit better.

https://electronicmission.wordpress.com/2017/06/02/a-digital-sine-wave-oscillator-theory/