FPGA: Waves 3: Computed Sinewave Oscillators

RE: FPGA: Waves 3: Computed Sinewave Oscillators

jc2048 — Tue, 08 Oct 2019 09:49:41 GMT

As an experiment, I thought I'd have a go at a crude frequency sweep of the 'magic roundabout' oscillator.

Here's the result of sweeping by simply incrementing the frequency-setting value (alpha) at each sample time.

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3d27585b-91a8-4217-9619-8524778f0614/contentimage_5F00_204733.png:480:234]

The 'scope trace is a bit of a mess because of the display aliasing.

Here's near the start in closer detail

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3d27585b-91a8-4217-9619-8524778f0614/contentimage_5F00_204734.png:480:234]

Here's somewhere around the middle

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3d27585b-91a8-4217-9619-8524778f0614/contentimage_5F00_204735.png:480:234]

And this is just before the end

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3d27585b-91a8-4217-9619-8524778f0614/contentimage_5F00_204736.png:480:234]

By the end, the amplitude has increased by about 2%. That's not as much as I was expecting, but it's enough that

you'd need some kind of adjustment of it if you wanted a continuous oscillator that could vary in

frequency.

RE: FPGA: Waves 3: Computed Sinewave Oscillators

shabaz — Thu, 03 Oct 2019 16:08:34 GMT

Hi Jon,

This is really great to see this sine-wave generation capability!! The results look great, and I think it would be fun to try your HDL, I hope to do so on an FPGA board sometime.

RE: FPGA: Waves 3: Computed Sinewave Oscillators

neuromodulator — Wed, 02 Oct 2019 06:53:27 GMT

I've been playing a bit with sine wave generator today. Managed to get a sweep but there are still many issues that need to be fixed.

[View:https://www.youtube.com/watch?v=wcHd3u-fQdw:740:466]

The sine wave is generated with a mixture of LUT and linear interpolation. To generate an exponential sweep I just increase the phase exponentially per unit of time.

RE: FPGA: Waves 3: Computed Sinewave Oscillators

jc2048 — Tue, 01 Oct 2019 08:54:26 GMT

After writing the blog, I realised what I was doing wrong with the simple Biquad oscillator. The frequency parameter is two times a cosine, so can range up to a value of almost 2. That means there is a binary digit ahead of the implied binary point and so when two numbers like that are multiplied it will result in two binary digits ahead of the implied point for the product. So the result from the multiplier needs to be adapted slightly (to keep the sign bit in place but move the rest along to lose the excess digit).

Once I did that it worked fine.

Here's the data flow diagram. You can see how simple it is, with just one multiplier and one subtractor.

[View:/resized-image/__size/600x450/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3d27585b-91a8-4217-9619-8524778f0614/contentimage_5F00_204729.jpg:600:450]

Here it is generating a 1kHz sinewave at half amplitude.

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3d27585b-91a8-4217-9619-8524778f0614/contentimage_5F00_204730.png:480:234]

I left it running for over an hour and it was still running ok with the same amplitude as at the start.

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3d27585b-91a8-4217-9619-8524778f0614/contentimage_5F00_204731.png:480:234]

Here's the VHDL in case it's of any interest to anyone.

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=text&text=------------------------------------------------------------------%0A--+++++*****+waves_shm+*****+++++++--%0A--++Test+of+MCP4821+DAC+with+sine+wave+from+biquad+generator++++--%0A------------------------------------------------------------------%0A--+JC+30th+September+2019++++++++++--%0A------------------------------------------------------------------%0A--+Rev++++Date+++++++++Comments+++++++++--%0A--+01+++++30-Sept-2019++++++++++++--%0A------------------------------------------------------------------%0Alibrary+ieee%3B%0Ause+ieee.std_logic_1164.all%3B%0Ause+ieee.std_logic_arith.all%3B%0Ause+ieee.std_logic_unsigned.all%3B%0Aentity+wave_test_con+is+port%28%0A++clk_in%3A+++in+std_logic%3B++++++++---+system+clock+in+%2850+MHz+oscillator%29%0A++---+DAC+connections%0A++mcp4821_ncs%3A+out+std_logic%3B++++++++---+DAC+cs%0A++mcp4821_sck%3A+out+std_logic%3B++++++++---+DAC+sck%0A++mcp4821_sdi%3A+out+std_logic%3B++++++++---+DAC+sdi%0A++mcp4821_nldac%3A+out+std_logic%3B++++++++---+DAC+load%0A++---+misc+control+signals+on+evaluation+board+that+it+might+be+good+to+hold+at+fixed+levels%0A++spi_cs%3A+++out+std_logic%3B++++++++---+%0A++hold_n%3A+++out+std_logic%3B++++++++---+%0A++sram_cen%3A++out+std_logic%3B++++++++---+%0A++sram_oen%3A++out+std_logic%3B++++++++---+%0A++sram_wen%3A++out+std_logic%3B++++++++---+%0A++uart_tx%3A++out+std_logic%29%3B++++++++---+%0A+%0Aend+wave_test_con%3B%0Aarchitecture+arch_wave_test+of+wave_test_con+is%0Asignal+spi_send%2C+spi_ncs%2C+spi_ncs_del%3A+std_logic%3B%0A---signal+waveform_count%3A+std_logic_vector+%2811+downto+0%29%3B%0Asignal+spi_output_sr_bit_count%3A+std_logic_vector+%285+downto+0%29%3B%0Asignal+spi_output_sr%3A+std_logic_vector+%2815+downto+0%29%3B%0Asignal+interval_count%3A+std_logic_vector+%288+downto+0%29%3B%0Asignal+osc_reset%3A+std_logic_vector+%281+downto+0%29%3B%0Asignal+sine_value%3A+std_logic_vector+%2817+downto+0%29%3B%0Asignal+del_sine_value%3A+std_logic_vector+%2817+downto+0%29%3B%0Asignal+product_value%3A+std_logic_vector+%2835+downto+0%29%3B%0Asignal+sub_result%3A+std_logic_vector+%2817+downto+0%29%3B%0Asignal+product_value_reduced%3A+std_logic_vector+%2817+downto+0%29%3B%0Asignal+alpha%3A+std_logic_vector+%2817+downto+0%29%3B%0Asignal+beta%3A+std_logic_vector+%2817+downto+0%29%3B%0A---+declare+the+multiplier+and+the+subtractor+modules+as+components%0Acomponent+mult_module+is%0A++++port+%28%0A++++++++A%3A+in++std_logic_vector%2817+downto+0%29%3B+%0A++++++++B%3A+in++std_logic_vector%2817+downto+0%29%3B+%0A++++++++P%3A+out++std_logic_vector%2835+downto+0%29%29%3B%0Aend+component%3B%0Acomponent+sub_module+is%0A++++port+%28%0A++++++++DataA%3A+in++std_logic_vector%2817+downto+0%29%3B+%0A++++++++DataB%3A+in++std_logic_vector%2817+downto+0%29%3B+%0A++++++++Result%3A+out++std_logic_vector%2817+downto+0%29%29%3B%0Aend+component%3B%0Abegin%0A+wave_test_stuff%3A+process+%28clk_in%29%0A++begin%0A+++if+%28clk_in%27event+and+clk_in%3D%271%27%29+then%0A++%0A++++---+interval_count+counts+at+the+clock+rate+%2850MHz%29%0A++++---+count+divides+by+500%2C+so+spi_send+occurs+every+10us+%28100ksps%29%0A++++if+%28interval_count%288+downto+0%29+%3D+b%22000000000%22%29+then+++++---+if+zero%0A+++++interval_count%288+downto+0%29+%3C%3D+b%22111110011%22%3B++++++---+preset+to+499%0A+++++spi_send+%3C%3D+%271%27%3B%0A++++else%0A+++++interval_count%288+downto+0%29+%3C%3D+interval_count%288+downto+0%29+-+1%3B+---+count+down%0A+++++spi_send+%3C%3D+%270%27%3B%0A++++end+if%3B%0A++++---+spi+ncs+goes+low+when+triggered+by+spi_send%2C+goes+hi+again+when+bitcount+reaches+31%0A++++%0A++++if+%28spi_send+%3D+%271%27%29+then%0A+++++spi_ncs+%3C%3D+%270%27%3B%0A++++elsif+%28spi_output_sr_bit_count%285+downto+0%29+%3D+b%22111111%22%29+then%0A+++++spi_ncs+%3C%3D+%271%27%3B%0A++++end+if%3B%0A++++%0A++++spi_ncs_del+%3C%3D+spi_ncs%3B%0A++++---+spi+output+bit+count+only+counts+when+enable+spi+cs+is+low%0A++++%0A++++if+%28spi_ncs+%3D+%270%27%29+then%0A+++++spi_output_sr_bit_count%285+downto+0%29+%3C%3D+spi_output_sr_bit_count%285+downto+0%29+%2B+1%3B%0A++++else%0A+++++spi_output_sr_bit_count%285+downto+0%29+%3C%3D+b%22000000%22%3B%0A++++end+if%3B%0A++++---+oscillator+reset+-+once-off+reset+at+start%0A++++if+%28spi_send+%3D+%271%27+and+osc_reset%2F%3Db%2210%22%29+then%0A+++++osc_reset%281+downto+0%29+%3C%3D+osc_reset%281+downto+0%29+%2B+1%3B+%0A++++end+if%3B%0A++++---+oscillator%0A++++---+this+is+storage+part%0A++++---+see+the+instantiated+components+below+for+the+rest%0A++++if+%28spi_send+%3D+%271%27%29+then%0A+++++if+%28osc_reset%280%29%3D%271%27%29+then%0A++++++sine_value%2817+downto+0%29+%3C%3D+%28others+%3D%3E+%270%27%29%3B%0A++++++del_sine_value%2817+downto+0%29+%3C%3D+beta%3B%0A+++++else%0A++++++sine_value%2817+downto+0%29+%3C%3D+sub_result%2817+downto+0%29%3B%0A++++++del_sine_value%2817+downto+0%29+%3C%3D+sine_value%2817+downto+0%29%3B%0A+++++end+if%3B%0A++++end+if%3B%0A++++---+spi+output+shift+register%0A++++%0A++++if+%28spi_send+%3D+%271%27%29+then+++++++++++++---+load+register...%0A+++++spi_output_sr%2811+downto+0%29+%3C%3D+sine_value%2816+downto+5%29%3B+++++---++sine+wave+data+%0A+++++spi_output_sr%2811%29+%3C%3D+not+sine_value%2817%29%3B++++++++---++invert+sign+bit+%0A+++++spi_output_sr%2815+downto+12%29+%3C%3D+b%220011%22%3B+++++++++---+++dac+control+bits%0A++++elsif+%28spi_ncs+%3D+%270%27+and+spi_output_sr_bit_count%281+downto+0%29+%3D+b%2211%22%29+then+---+shift+register...%0A+++++spi_output_sr%2815+downto+1%29+%3C%3D+spi_output_sr%2814+downto+0%29%3B++++---++the+register+contents%0A+++++spi_output_sr%280%29+%3C%3D+%270%27%3B%0A++++end+if%3B%0A+++end+if%3B%0A+++%0A+++---+oscillator+control+parameters%0A+++---+these+give+frequency+of+fs%2F100+%3D+1kHz%0A+++---+amplitude+of+0.5+x+full+range+%3D+1.024V+pk%2Fpk%0A+++%0A+++alpha+%3C%3D+b%22011111111011111101%22%3B%0A+++beta+%3C%3D++b%22111111011111110101%22%3B%0A+++---+this+is+to+fiddle+the+product+from+the+multiplier%0A+++---+to+get+the+implied+binary+point+in+right+place%0A+++---+%28multiplication+gives+two+bits+ahead+of+point+output%0A+++---+with+operands+having+one+digit+ahead+of+point%29%0A+++product_value_reduced%2817%29+%3C%3D+product_value%2835%29%3B%0A+++product_value_reduced%2816+downto+0%29+%3C%3D+product_value%2832+downto+16%29%3B%0A+++---+connecting+various+signals+to+output+pins%0A+++%0A+++mcp4821_ncs+%3C%3D+spi_ncs%3B%0A+++mcp4821_sck+%3C%3D+spi_output_sr_bit_count%281%29%3B%0A+++mcp4821_sdi+%3C%3D+spi_output_sr%2815%29%3B%0A+++mcp4821_nldac+%3C%3D+%270%27%3B%0A++%0A+++---+hold+these+device+control+pins+at+a+fixed+level+to+stop+them+flapping+around%0A+++spi_cs+%3C%3D+%271%27%3B%0A+++hold_n+%3C%3D+%271%27%3B%0A+++sram_cen+%3C%3D+%271%27%3B%0A+++sram_oen+%3C%3D+%271%27%3B%0A+++sram_wen+%3C%3D+%271%27%3B%0A+++uart_tx+%3C%3D+%271%27%3B%0A++end+process+wave_test_stuff%3B%0A+%0A++---+instantiate+the+multiplier+and+the+subtractor+for+the+oscillator%0A++---+and+make+the+signal+connections%0A++%0A++mult_module1%3A+mult_module%0A+++port+map%28%0A++++A+%3D%3E+alpha%2C%0A++++B+%3D%3E+sine_value%2817+downto+0%29%2C%0A++++P+%3D%3E+product_value%2835+downto+0%29%29%3B%0A++++%0A++sub_module1%3A+sub_module%0A+++port+map%28%0A++++DataA+%3D%3E+product_value_reduced%2817+downto+0%29%2C+%0A++++DataB+%3D%3E+del_sine_value%2817+downto+0%29%2C+%0A++++Result+%3D%3E+sub_result%2817+downto+0%29%29%3B%0Aend+arch_wave_test%3B]

RE: FPGA: Waves 3: Computed Sinewave Oscillators

neuromodulator — Mon, 30 Sep 2019 18:59:10 GMT

BTW, you may want to check 2d rotation matrices, thats pretty much what you are doing. If you are familiar with 3d computer graphics you may know that linear transformations are represented as matrices. 2 lienar transformations can be represented as a single matrix if you multiply the 2. Thus if you build a small delta theta rotatoin matrix and multiply it by itselff you will rotate 2 delta thetas, and so on.

What kind of DAC are you using? I'll probably post something similar, an FPGA based frequency sweeper...

RE: FPGA: Waves 3: Computed Sinewave Oscillators

genebren — Mon, 30 Sep 2019 18:28:56 GMT

Great update on FPGA computed sinewave oscillator series. This looks like a very cool way to make sinewaves!

Thanks for sharing!

Gene