FPGA: Waves 8: Fast CORDIC Sine and Cosine

RE: FPGA: Waves 8: Fast CORDIC Sine and Cosine

neuromodulator — Wed, 27 Nov 2019 13:09:04 GMT

Give delta sigma a try! Its fun! Its pretty linear, requires a single pin besides the ground and can be adapted according to your needs!

RE: FPGA: Waves 8: Fast CORDIC Sine and Cosine

jc2048 — Sun, 24 Nov 2019 20:34:14 GMT

I realised, after I'd posted the above comment, that it sort of implies the noise

is flat and therefore the trace does accurately show the filter response. That

isn't quite true because, as the frequency moves up toward the sampling

frequency, the response of the output of the DAC drops off.

I thought it would be an interesting experiment to disconnect the DAC from the

filter and measure the spectrum at the DAC output.

Here is the filter output again, and below that the output of the DAC (without

the filter attached - I disconnected the filter entirely because, otherwise, it

would affect the results)

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-d3c46c16-cbc4-4254-bd85-36d322cadced/contentimage_5F00_205286.png:480:234]

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-d3c46c16-cbc4-4254-bd85-36d322cadced/contentimage_5F00_205287.png:480:234]

We can see the way the DAC output falls as it moves towards the sampling

frequency (fs=50Msps) [with the linear frequency scale (5MHz per div), fs is at

the righthand edge of the screen].

First observation is that with a cut-off frequency for the filter of about a

quarter of the sample rate, the filter output response does give a moderately

good indication of the cut-off frequency and the first part of the roll-off above

that. Further up it is going to start to be be increasingly compromised by the

DAC response (though with my 'scope FFT so limited by its comparatively poor

resolution, compared to an actual spectrum analyser, it's hardly an issue - I

can't look at that area sensibly anyway).

The reason for that drop is that this kind of DAC moves to a set level and then

sits there for the sample period. If it did that perfectly, that results in a

(sin x)/x spectrum envelope. That curve has nulls at multiples of the sampling

frequency.

If I change the settings, so that we can see up beyond the sample rate, we get

this with the nulls quite clear [this is now 25MHz per div].

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-d3c46c16-cbc4-4254-bd85-36d322cadced/contentimage_5F00_205288.png:480:234]

A couple of observations. There's quite a lot of energy at the actual sample rate

frequency (and its multiples) and the null around it isn't all that deep. We can

surmise the reason if I show you the actual DAC output waveform

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-d3c46c16-cbc4-4254-bd85-36d322cadced/contentimage_5F00_205289.png:480:234]

Instead of a nice stepped waveform, I have the output slewing from sample to

sample and often only just making it before the next change. That then gives me

something quite messy between the delta functions of perfect sampling theory and

an accurate, precise step that you'd get with a monolithic DAC that can manage a

decent zero-order (stepped) output.

Perhaps I was a touch optimistic about the kind of results I could get with a

resistor DAC, built on stripboard, at rf frequencies [though it has been fun to

experiment with and the results are better than I feared they might be].

RE: FPGA: Waves 8: Fast CORDIC Sine and Cosine

jc2048 — Sat, 23 Nov 2019 23:30:02 GMT

Here's the stats

Device utilization summary:

   GSR                1/1           100% used
   PIO (prelim)      19/174          10% used
                     19/100          19% bonded
   SLICE            244/2376         10% used

and the floorplan

[View:/resized-image/__size/620x513/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-d3c46c16-cbc4-4254-bd85-36d322cadced/2450.contentimage_5F00_205284.png:620:513]

That looks quite reasonable, but remember it's for a short wordlength (only 6

bits).

Finally, I hacked my random number generator and attached it to the DACs. The

oscilloscope's FFT then shows, somewhat crudely, the frequency response of the

filter [note that the frequency scale is linear]. That suggests that my cut-off

frequency is around 12.5MHz, where it was meant to be. So I got that right, at

least.

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-d3c46c16-cbc4-4254-bd85-36d322cadced/5582.contentimage_5F00_205285.png:480:234]

RE: FPGA: Waves 8: Fast CORDIC Sine and Cosine

shabaz — Sat, 23 Nov 2019 22:30:09 GMT

Hi Jon,

This is a great blog post. Thanks for sharing the VHDL code too, it's awesome being able to see all this as you experiment.

RE: FPGA: Waves 8: Fast CORDIC Sine and Cosine

genebren — Sat, 23 Nov 2019 18:06:05 GMT

Another great entry in your series of blogs. Interesting artifact at/around the zero crossing, hopefully you will find a good solution.