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Project IceStorm: fully open-source FPGA tools for Lattice iCE40

johnbeetem

As some of you may have noticed, I've been obsessed for many decades with having open FPGA bitstream documentation so that people can write their own FPGA designs tools, especially FLOSS (Free-as-in-Liberty Open Source Software).

 

I recently found out about IceStorm, a project that has somehow reverse-engineered and documented the Lattice iCE40 FPGA.  They've actually put together a fully-open-source tool chain with Yosys for Verilog synthesis and Arachne_pnr for placement and routing.  I don't know how usable or robust the tools are.  I'm planning on taking a close look starting next month.

 

If you're interested, here's the IceStorm link, which has links to the other tools: Project IceStorm

Discussion of Yosys and the tools is at reddit: Yosys Open SYnthesis Suite

 

Update: Here are a couple of nice Hackaday items about IceStorm:

 

From 29 March 2015: Reverse Engineering Lattice’s iCE40 FPGA Bitstream | Hackaday

From 29 May 2015: An Open Source Toolchain For iCE40 FPGAs | Hackaday

 

Update 2: Here are some good IceStorm installation instructions: Projet IceStorm : le FPGA libéré ! | Front de Libération des FPGA.  They're in a combination of French and GNU/Linux.

 

Here's the Lattice IceStick directly supported by IceStorm: Lattice Semiconductor: ICE40HX1K-STICK-EVN iCEstick Evaluation Kit.  It's US$20.89 in the USA.

  • I'm amazed and impressed at the amount of effort going into this but for so little gain !

     

    Targeting the 1k part and no support for block ram or plls isn't really getting to the point where you could do any real design with the tools so the project has a very long way to go.

     

    From a personal point of view it's such a shame they are using Verilog 2005  - which is a pretty low base for an HDL.

     

    If it ever gets to the point of supporting the bigger iCE40 parts the packages will be a problem - some of the newer ones come in 0.5mm pitch BGA (or smaller if you like ).

     

    MK

  • in reply to michaelkellett

    Michael Kellett wrote:

     

    I'm amazed and impressed at the amount of effort going into this but for so little gain!

    I see IceStorm as a huge step in the right direction.  IMO the best way to get vendors to document their bitstreams is to have projects like IceStorm and my Flavia show that it's possible to use FLOSS tools and that there are advantages to doing so, both for users and vendors.  For example, Flavia is much faster than Xilinx tools for small designs, making it a better platform for teaching programmable logic concepts.  I'm hoping these projects will embarrass Xilinx and Altera into opening their bitstreams.

     

    I'm looking forward to playing with IceStorm.  While the iCE40 HX1K is indeed a small part, it's big enough for teaching about FPGAs and has a lot more capacity than any of my Flavia implementations.  So it looks like a good answer to 's FPGA/CPLD education question: http://www.element14.com/community/thread/17692?start=56

  • element14/Newark has a great price (US$20.89) on the Lattice IceStick, which is the development board used in the IceStorm demos: Lattice Semiconductor: ICE40HX1K-STICK-EVN iCEstick Evaluation Kit

  • I've got IceStorm running and my own examples working on an IceStick!

     

    I installed IceStorm and its companion tools using instructions from: Projet IceStorm : le FPGA libéré ! | Front de Libération des FPGA.  Its in a combination of French and GNU/Linux.

     

    Installing arachne-pnr was a pain since it's written in C++11, and the Ubuntu 12.04 I normally use has an older GCC.  Finding out how to update to 4.8.1 was an adventure, as usual.  Installing Yosys took over an hour on an ODROID-C1.  I guess I should be glad I could do it at all

     

    The "rot" example -- which uses Yosys -- didn't work for me.  It compiled and loaded OK, but only set the LEDs to the initial pattern and didn't update it.  That's OK, because I really just need arachne-pnr and IceStorm for my work.  On the other hand, my own examples written in BLIF (Berkeley Logic Interchange Format) worked great once I figured out how to match LUT inputs I0-I3 to 16-bit truth tables.

     

    [Update 9 August 2015:  The "rot" example works with a newer version of arachne-pnr I downloaded 4 August 2015.]

     

    Arachne-pnr is very fast for my simple examples once it's loaded the IceStorm's iCE40-HX1K ASCII chip database, which is 7 MB.  The IceStorm tools are very fast.  An unmodified IceStick requires that IceStorm first programs the serial flash, so "iceprog" should be even faster if I have it download to FPGA configuration memory directly.  The HX1K binaries are only 32KB.

     

    [Update 9 August 2015:  Newer versions of arachne-pnr convert IceStorm database files from text to binary as part of the "make" process.  Loading the binary database is very fast.]

     

    My plan is to call Arachne-pnr and IceStorm from my XXICC project, using GCHD for synthesis.  This will make a nice companion to my Xilinx-based Flavia: the Free Logic Array.

  • iCEstick is now US$30.02 and out of stock at Newark (USA).  I don't know why it went up so much.  It's still US$21.86 at Lattice Semiconductor site.

     

    IceStorm now supports the iCE40-HX8K with 7680 logic cells, which is 6 times the capacity of the HX1K with 1280 logic cells.  You can get an HX8K breakout board for US$42.88 at Lattice Semiconductor site.  It's not listed at Newark.

  • in reply to johnbeetem

    The HX8K is big enough to do useful work although its lack of multipliers is a pain. It comes in BGA only -  the 132 ball 0.5mm pitch part is quite cheap but requires the use of exotic design rules to use all the pins. I think the OSHPark multi layer design rules will allow you to get one running and use most of the IO.

    The part is also available in 0.8mm pitch 256 ball BGA which might allow easier design rules but I haven't tried.

     

    I do wish Lattice would make ALL the ICE40xxxx parts available in TQFP - I'm sure it would increase the number of design ins quite a lot.

     

    MK

  • in reply to johnbeetem

    johnbeetem wrote:

     

    The "rot" example -- which uses Yosys -- didn't work for me.  It compiled and loaded OK, but only set the LEDs to the initial pattern and didn't update it...

     

    Arachne-pnr is very fast for my simple examples once it's loaded the IceStorm's iCE40-HX1K ASCII chip database, which is 7 MB.

    Both of these problems have been fixed in a newer version of arachne-pnr I downloaded 4 August 2015.  The "rot" example now works.  Arachne-pnr now converts IceStorm database files from ASCII to binary as part of the "make" process.  Loading the binary database is very fast.

  • John,

     

    Are there any independently produced iCE40 breakout boards?

     

    I did not find one, which is a concern,

    as there are many guides, tutorials as well as cheap boards, for say Xilinx Spartan.

    what is the reason?

     

    Farnell UK are also out of stock.

     

    I am keen to give IceStorm a whirl....

  • in reply to peepo

    I don't know of any.

    I've designed ICE40 devices into a few commercial designs and get the impression that Lattice are only interested in supporting developers who will use huge numbers in any given design.

    As I mentioned above it's a shame that the parts are mainly available only in difficult packages.

    Having said that it's not hard to design a board to use the 1k part (which comes in TQFP) and I think it is possible to design a board using an 8k part in the 132 ball 0.5mm BGA package using OSHPark's 4 layer design rules. I've designed boards with that package but with 0.075mm track and gap rules which is a bit pricey (think in terms of £450 for 12 off 25mm x 100mm boards).

    If I could drum up any interest I would be keen to help design a board for either part.

     

    If you are in the UK why not come to the UK OSHG jamboree at the end of this month and see if you can find any like minded collaborators. (wutheringbytes.com)

     

    MK

  • in reply to peepo

    Jonathan Chetwynd wrote:

     

    Are there any independently produced iCE40 breakout boards?

     

    I did not find one, which is a concern, as there are many guides, tutorials as well as cheap boards, for say Xilinx Spartan.  what is the reason?

    I don't know of any independent iCE40 breakout boards either.  I would say that the reason is that the boards from Lattice as so cheap (especially the iCEstick at approx US$22) that it would be hard for an independent board maker to compete.  IMO independent FPGA development boards are generally expensive because they're produced in small quantities, which drives up manufacturing costs a lot.  A smart IC vendor sells eval boards at or below cost and considers this to be part of marketing cost.

     

    Xilinx has been around a long time, so it's not surprising that there are lots of moderately-priced boards available.  I won't say cheap, because I don't consider US$70 and up "cheap" for a Spartan-6 development board when you can get a RasPi 2 or equivalent for US$35.  OTOH, the independent boards are a lot cheaper than official Xilinx development boards, so there is definitely a market for them.  Avnet used to have a dandy Spartan-3A board they priced at $49 (and sometimes $39), which was very attractive at the time.

     

    I often recommend Gadget Factory's Papilio One 250K as a great little board for US$38.  While the Spartan-3E 250K is now a "mature" product, it's a very nice FPGA to work with and the Papilio One brings out 48 GPIOs to headers (plus UART RX/TX) so it's great for projects with lots of I/O.  You do have to face the steep Xilinx ISE software learning curve.

     

    For people getting started with FPGAs, particularly those who just want to play a little to see if FPGAs are something they want to pursue more seriously, IMO iCEstick with IceStorm and its companion tools are the best way to go.  Xilinx ISE is a very powerful tool suite, but it's intended for serious FPGA developers who are more willing to climb the learning curve.

     

    JMO/YMMV