Forum - Recent Threads

Learning FPGA

danielpgleason — Mon, 04 May 2026 18:33:04 GMT

Does anyone know of any good learning resources about how to start learning FPGA? I've been a software engineer for several years and the FPGA world is quite new to me. I'm trying to implement RMII but have been struggling a lot. I purchased a logic analyzer but I don't know what I'm looking at. I need something that will tell me how to properly understand and read datasheets, know how to debug signals, how to understand what VHDL is good and what is bad. How to read RTL generations..Etc

I'm starting from the beginning. Any resources or materials are greatly appreciated.

What is the latest Lattice eval board?

Jayfox — Fri, 06 Mar 2026 10:41:09 GMT

Looking for a low-cost FPG eval board to start learning Verilog/VHDL and work with soft-core .

Lattice seems to be low cost / low power: what is the latest eval board?

Ultra96-V2 – VART not found / Unable to run .xmodel

wael_gu — Fri, 13 Feb 2026 20:34:44 GMT

Hello everyone,

I am working with an Ultra96-V2 (Zynq UltraScale+ MPSoC) board and trying to deploy an AI model using Vitis AI.

Here is my current situation:

I successfully quantized and compiled my model on my PC using Vitis AI Docker (CPU version 2.5.0).
I transferred the generated .xmodel file (resnet50.xmodel) to the Ultra96-V2 board.
The board is running a Linux image (ultra96v2-2020-1).
When I try to run:

I get:

I also checked for VART libraries using:

No results were found.

It seems that Vitis AI Runtime (VART) is not installed in the current image.

My questions are:

What is the recommended Vitis AI image for Ultra96-V2?
Is there a prebuilt SD card image that includes VART and DPU support?
If manual installation is required, what is the correct procedure for installing VART on Ultra96-V2 (aarch64)?

Any help or guidance would be greatly appreciated.

Thank you.

In hackathalon FPGA projects, I dont know why but i only see health or disease based projects saying that it will save 2 to 5 minutes of processing,and they even win many times

Aniket_kumar_raj — Tue, 06 Jan 2026 11:26:04 GMT

Judges should not select health based projects as Saviour to the world, something more can be done with FPGA if a person is creative,i recently hosted a offline FPGA hackathon ane everyone made a project on Boilogy realated thing, and this is what made me hate every project which is health based project

I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

micheal.embedded — Sun, 04 Jan 2026 17:48:45 GMT

I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

On paper, using the PL for acceleration always looks like the right move. In practice, I keep finding that the integration cost—AXI plumbing, cache coherency, DMA setup, and tool friction—ends up dominating the project far more than the accelerator itself.

I’ve had projects where the hardware worked, but performance was still disappointing because the PS–PL interface became the bottleneck, or where workflow choices (Vivado vs Vitis) boxed me into painful rework later.

So my question is: at what point do you personally decide that moving functionality into the PL is worth it on Zynq, and when do you step back and keep things in software instead?

I’d really like to hear what decision signals or failure experiences others use to make that call.

Suggestion needed regarding Zynq ultrascale+ FPGAs

Praj — Fri, 24 Oct 2025 21:11:46 GMT

Hello, I am looking for a Zynq Ultrascale+ based FPGA with the following features

1) (PS + PL)

2) RDIMM slots

3) PL can access the RDIMM

I am implementing a custom memory controller, so I need an FPGA with an ARM core and programmable logic wth DIMM slots.

Please let me know if anyone is aware of FPGAs that meet the above specifications.

Thanks,

Issues with outputs on new ZCU104 eval kit

Akropolidis — Mon, 13 Oct 2025 15:57:00 GMT

I just obtained a new ZCU104 Eval kit (AMD Zynq Ultrascale+ MPSoC ZCU104 Evaluation Kit) and I'm running into some issues with my bitstreams.

I have a bitstream implementation of a ARM Cortex-M0 mcu and tested this on the board and observed the expected results. Now I want to move development to another ZCU104 eval board that I've just obtained, I flashed the exact bitstream but the I/Os don't seem to be working. In debugging, I tested with a simpler design below:

`timescale 1ns/1ps
module test(
input logic clk_p,
input logic clk_n,
output logic clk_50,
// output logic sys_clk,
// output logic locked,
output logic [2:0] led
);
logic sys_clk;
logic locked;
IBUFGDS osc_clk (
.O(sys_clk),
.I(clk_p),
.IB(clk_n)
);
clk_wiz_1 clock_test
(
// Clock out ports
.clk_out1(clk_50), // output clk_out1
// Status and control signals
.locked(locked), // output locked
// Clock in ports
.clk_in1(sys_clk) // input clk_in1
);
assign led[0] = locked;
assign led[1] = 1'b1;
assign led[2] = 1'b1;
endmodule

# Clock - ZCU104 125MHz System Clock (Differential)
set_property PACKAGE_PIN F23 [get_ports clk_p]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property PACKAGE_PIN E23 [get_ports clk_n]
set_property IOSTANDARD LVDS [get_ports clk_n]
##############################################################
# Status LEDs - ZCU104 User LEDs
##############################################################
set_property PACKAGE_PIN D6 [get_ports clk_50]
set_property IOSTANDARD LVCMOS33 [get_ports clk_50]
set_property PACKAGE_PIN D5 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN A5 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN B5 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]

What's interesting is I did observe an expected output from driving the pins of the led directly with assign statements as shown above. But the led connected to locked which is an output driven by the clock wiz module is not set. Running post synthesis and implementation simulations indicate the locked signal and clock wizard work fine so I'm confused.

I think the issue is in the hardware configuration, are there additional bringup steps that I'm missing? I've referenced the documentation and SW6 is set to JTAG mode (0000/0x0) but I can't seem to find the issue.

Avnet UltraZed-EG PCIe Carrier Card - Golden Constraints

slavikolev-ilt — Tue, 16 Sep 2025 12:14:58 GMT

Hello all,

Thank you so much for the help on my previous post! Unfortunately, I am still missing some very important reference design files. Namely, I am looking for a golden constraints file, meaning constraints for every peripheral of the PCIe card. However, if you're able to point me to a resource on official reference designs for UltraZed and the PCIe card more broadly (or even an unofficial reference design), I would very much appreciate that. Most of the links on the official product page are dead, sadly.

Thank you very much!

Slavi

Avnet UltraZed-EG SOM - Trace Delays

slavikolev-ilt — Tue, 02 Sep 2025 11:14:11 GMT

Hello all,

I need to find out the trace delays of the UltraZed-EG SOM (from SoC to JX1, JX2, JX3 connectors) with as high precision as possible for use in a high speed interface design. I see that in the Designer's Guide (attached) in Section 9, Page 47, there are three values provided for each pin, with no explanation given. At first I assumed they mean minimum, average, and maximum delay, respectively. However, the value ranges seem quite high for that to be the case.

Does anyone have an idea what the three values are? If they are indeed "min, avg, max", then why is the value range so high?

Any advice is greatly appreciated!

Slavi

community.element14.com/.../5290_2D00_DG_2D00_AES_2D00_EG_2D00_SOM_2D00_V1.pdf

How to make a silent boot on Petalinux 2022.2

bugtech — Thu, 28 Aug 2025 08:15:58 GMT

I have been trying to make a silent boot on Petalinux 2022.2 on Kria KV260 board. I have added different bootargs like, "quiet". But still i see a lot of dump during the boot. How to make a clean silent boot without displaying nothing? Any leads!

ZCU208 RFSoC Explorer Toolbox Dual AXI DMA Integration & FIL Workflow Limitations with HDL Coder

100asut01 — Wed, 20 Aug 2025 17:33:17 GMT

Hello everyone,

We recently purchased four ZCU208 boards and are in the process of extending an HDL Coder–based design to support eight-channel IQ data capture. While the single-DMA reference design works fine, we’ve run into several roadblocks trying to scale this to a dual-DMA setup. I’d like to outline the issues here and see if anyone in the community has experience or workarounds.

Background

Board: ZCU208
Flow: MATLAB/Simulink HDL Coder (R2023b / R2024a)
Starting point: Avnet RFSoC Explorer Toolbox reference design (single DMA, validated on hardware)
Goal: Add a second AXI DMA to stream 8-channel complex data at higher throughput

Challenges Encountered

1. Reference Design Integration

The Avnet Explorer Toolbox single-DMA plugin integrates fine.
Attempting to extend to dual DMA requires modifying:
- plugin_rd_dualdma.m
- system.tcl (to instantiate/connect the second DMA)
We confirmed that the older ReferenceDesignPlugin class approach is unsupported in R2023a/b.
Factory-based plugin (hdlcoder.ReferenceDesign) works in R2024a, but integration remains unstable.
MathWorks support confirmed that dual-DMA examples are not provided in their documentation (e.g., Chapter 35), and that ZCU208 is not officially supported.

2. FIL Workflow Limitations

Using FIL snapshot mode:
- Theoretical capture: ~31k IQ samples for 8 channels (given 1 MB buffer, 32 bytes/sample).
- Practical result: Only ~2k samples for 4 channels before buffer limits hit.
This makes FIL unsuitable for high-throughput testing, meaning dual-DMA streaming is mandatory for our use case.

3. Toolchain & Device Tree

Even with a functional dual-DMA block design in Vivado, HDL Coder integration requires manual PetaLinux device tree updates.
Without this step, Linux drivers won’t recognize the second DMA.
At present, HDL Coder alone does not provide a clean, supported way to integrate this.

Questions for the Community

Has anyone successfully integrated dual AXI DMA with ZCU208 using Avnet’s reference design as a base?
If so, was the workflow MATLAB-centric, or did it require deeper Vivado/Device Tree customization?
Are there any known workarounds or examples (Element14 or otherwise) for extending the Avnet Explorer Toolbox to multi-DMA?
Given the FIL capture bottleneck, is there a better recommended flow for validating 8-channel high-rate IQ streaming on ZCU208?

Closing

We’d greatly value insights from others who may have solved similar integration challenges. Since we’ve already invested in multiple ZCU208 boards, we want to avoid reinventing the wheel if community knowledge exists.

Thanks in advance for any guidance, links, or even partial solutions that can help move this forward.

Feedback Requested - Brand New SDR

pope — Wed, 09 Jul 2025 15:32:06 GMT

Hey everyone,

We’re building the next generation of RF technology at krtkl and are reaching out to the community for input.

If you’re an engineer, researcher, or developer working with SDRs or wireless systems, we’d love to hear from you. We're especially interested in understanding your current challenges, workflows, and where existing tools fall short.

If you're up for a quick chat (or even just want to share your thoughts in the thread), drop a reply or shoot an email to pope (at) krtkl (dot) com.

Thanks in advance!

- Micah @ krtkl

Microzed Carrier Board Component Question

jamesyin1289 — Thu, 26 Jun 2025 19:11:53 GMT

I was wondering if it was possible to answer a question regarding a component on a previous Avnet product that is now obsolete. In particular, I am looking at the MicroZed I/O Carrier Card (MBCC). I noticed that from the DataSheet, there are specifications for the behavior of the VCCIO_EN and PWR_EN signals, which are controlled by the MAX16025 chip. However, I noticed that the corresponding BOM labels this as DNP, and the physical board is also missing this particular component. I was curious about the exact purpose and placement of this component. It had seemed as if they were necessary to enable the VCCIO_34 and VCCIO_35 power supplies to the rest of the carrier board, so I am confused why they are not present physically.

Hardware Manager unconnected. Autoconnect crashes

sam_jones — Wed, 09 Apr 2025 15:32:00 GMT

Hi all,

i am able to run linux images on the K24 SoM board via SD card image.

However i cant access the board via JTAG. Open Hardware doesnt detect it.

I have run "install" scripts in /xicom. Other Xilinx FPGAs (e.g. Zybo) are immediately detectable.

Do i have to install any special drivers ?

Thanks

WiFi SD Card application

shroomcurry — Tue, 25 Mar 2025 15:55:16 GMT

Hi,

MicroSD Card : This represents a memory card, typically used for storage.
SoC (System on a Chip) : This is the central processing unit, the "brain" of the system. It handles data processing and communication between different components.
WiFi: This represents the WiFi module, responsible for wireless internet connectivity.
SD Host (PC): This represents the host device, likely a personal computer, which interacts with the system.
WiFi/BT ANT : This represents the antenna for both WiFi and Bluetooth communication.

SoC acts as a central hub, facilitating communication between the MicroSD Card, the WiFi module, and the SD Host (PC).

Data can be transferred between the MicroSD Card and the SoC using the storage protocol.
The SoC can communicate with the WiFi module using the communication protocol, enabling wireless internet access.
The SoC can also communicate with the SD Host (PC) using some protocol, allowing data transfer between the computer and the device.

What is the best suited Lattice FPGA and IP cores for this application?

Thanks.

Turing my M5stack core2 to a flipper

Kobe — Tue, 21 Jan 2025 09:19:28 GMT

Hey guys, Im new to coding, but have general knowledge of hardware. Im about to take on task which is out my scrope but wit chatgpt i will try it. this what i will be doing, i bought all the parts , the hard part is the coding. if anyone is willing to jump on board this project let me know. here is what im doing :

Flipper-Like Project with M5Stack Core2

Welcome to the **Flipper-Like Project using M5Stack Core2**! This project aims to transform the M5Stack Core2 into a versatile, Flipper Zero-like device. By leveraging the Core2's hardware capabilities and expanding its functionality with additional modules and custom software, we hope to build a powerful tool for RF communication, signal analysis, and more.

---

## **Project Overview**

The goal of this project is to create a device inspired by the **Flipper Zero**, but based on the open-source-friendly **M5Stack Core2** hardware. This project will focus on:

- **RF communication**: Support for common protocols like Sub-1GHz, Bluetooth, Wi-Fi, and LoRa.
- **Modularity**: Integration with M5Stack modules (e.g., LoRa, RS485, Proto Boards).
- **User Interface**: A touchscreen interface powered by the Core2's built-in display.
- **Expandability**: Allow for additional custom hardware, such as CC1101, NRF24L01, and FPGA modules.
- **Open Development**: Create a community-driven project where developers can contribute new features and improve existing ones.

---

## **Current Features**

- **Hardware Integration**:
- M5Stack Core2 touchscreen and processing power.
- RF modules: CC1101, LoRa (433MHz and 900MHz), and NRF24L01.
- Support for additional modules: FPGA (iCESugar-nano), ESP32, and external antennas.

- **Planned Functionalities**:
- Sub-1GHz scanning and transmission.
- Signal replay and analysis.
- Wi-Fi and Bluetooth communication.
- Infrared (IR) support.
- GPIO-based hacking tools.

---

## **Hardware Requirements**

### **Required Components**
1. **M5Stack Core2**: The central controller with a touchscreen interface.
2. **RF Modules**:
- CC1101 RF Module.
- NRF24L01 Wireless Module.
- LoRa Modules (e.g., Ra-08 and Ra-08H).
3. **Expansion Modules**:
- M5Stack Proto Boards.
- iCESugar-nano FPGA Development Board.
4. **Antennas**:
- Sub-1GHz antennas.
- External directional antennas for extended range.
5. **Power Supply**:
- M5Stack Battery Modules (13.2).
6. **Miscellaneous**:
- SMA connectors, jumper wires, headers, etc.

---

## **Software Requirements**

1. **Firmware Development**:
- PlatformIO with Visual Studio Code for development.
- ESP-IDF for Core2 programming.

2. **Features Under Development**:
- A user-friendly interface for scanning and replaying RF signals.
- Drivers for CC1101, NRF24L01, and LoRa modules.
- Wi-Fi and Bluetooth utilities for hacking and testing.

3. **Libraries and Dependencies**:
- **M5Stack Core2 Libraries**: Touchscreen, display, and GPIO handling.
- **RF Driver Libraries**: For Sub-1GHz communication (e.g., ELECHOUSE CC1101 library).
- **Signal Processing Libraries**: FFT and RF signal encoding/decoding.

---

## **How to Contribute**

1. **Fork and Clone**
- Fork this repository and clone it to your local machine.

2. **Set Up Development Environment**
- Install PlatformIO and required libraries.
- Flash the initial firmware onto the Core2 to verify setup.

3. **Choose a Task**
- Check the [Issues](#issues) tab for open tasks.
- Suggest new features or improvements in Discussions.

4. **Submit Pull Requests**
- Develop your feature or fix and submit a pull request.
- Include detailed descriptions of changes made.

---

## **Getting Started**

1. **Prepare the Core2**:
- Flash the provided base firmware.
- Connect required modules (e.g., CC1101, NRF24L01).

2. **Install Software**:
- Clone this repository.
- Set up the development environment with PlatformIO.

3. **Test Basic Functionality**:
- Verify touchscreen and RF module communication.
- Test signal scanning and basic transmissions.

---

## **Future Plans**

1. **Expand RF Protocol Support**:
- Add support for Zigbee, Z-Wave, and other protocols.
2. **Develop Community Plugins**:
- Enable developers to create custom tools and utilities.
3. **Improve Usability**:
- Add graphical tools for signal analysis and automation.

---

## **Contact and Support**

If you have any questions or need support:
- Open a discussion or issue on this GitHub repository.
- Contact the project maintainer via email or the community chat.

---

Together, we can create an open-source alternative to Flipper Zero that empowers users and supports innovation. Let's build something amazing!

Setting up CAN interface for Xilinx ZCU102

bugtech — Fri, 17 Jan 2025 11:58:55 GMT

I am working on zcu102 ultrascale board. I want to use CAN interface to send and receive data, Is there any guide or tutorial to setup this connection?

Are there any drivers needed to be installed separately? (CAN4Linux or SocketCAN)

On loopback mode i am able to see the data that i send, cansend can0 123#1234 (from here i imagine that CAN drivers are working)

But in normal mode, i dont receive anything.

Also i dont receive anything on oscilloscope.

Any leads?

Using waveshare CANopen interface with zcu102

bugtech — Wed, 08 Jan 2025 08:28:53 GMT

Is there any guide or example to use the CANopen interface with zcu102 board. I just want to make the connection and send some data for testing.

Thank you

Zynq PS Spi and Quad Spi referance design tutorial Help

brhn — Mon, 16 Dec 2024 17:52:07 GMT

I'm trying to make communicate between ps7_spi_0 and axi_quad_spi. This is block diagram. FCLK_CLK0 is 100 Mhz. SPI_0 is 166.666666 Mhz

C code :

/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xspips.h"
#include "xspi.h"
#include "sleep.h"

#define SPI_DEVICE_ID		XPAR_XSPIPS_0_DEVICE_ID
#define QSPI_DEVICE_ID		XPAR_SPI_0_DEVICE_ID

static XSpiPs SpiInstance;
static XSpi 	Spi;

u16 TxBuffer[4];
u16 RxBuffer[4];

int main()
{
	XSpiPs_Config *SpiConfig;
	int Status,i;
	init_platform();
	int NumBytesRcvd;

    printf("SPI Example\n");

	SpiConfig = XSpiPs_LookupConfig(SPI_DEVICE_ID);
	if (NULL == SpiConfig) {
		return XST_FAILURE;
	}

	Status = XSpiPs_CfgInitialize(&SpiInstance, SpiConfig,SpiConfig->BaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	Status = XSpiPs_SelfTest(&SpiInstance);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	XSpiPs_SetOptions(&SpiInstance, XSPIPS_MASTER_OPTION | XSPIPS_FORCE_SSELECT_OPTION);

	XSpiPs_SetClkPrescaler(&SpiInstance, XSPIPS_CLK_PRESCALE_64);


	XSpi_Initialize( &Spi, QSPI_DEVICE_ID );
    Status = XSpi_SelfTest( &Spi );
    if (Status != XST_SUCCESS) {
    	return XST_FAILURE;
    }
    XSpi_Reset(&Spi);


    XSpi_Start(&Spi);
    XSpi_IntrGlobalDisable(&Spi);



	TxBuffer[0] = 0xa0a0;
	TxBuffer[1] = 0x0505;
	TxBuffer[2] = 0xa0a0;
	TxBuffer[3] = 0x0505;

	while (1) {
			XSpiPs_SetSlaveSelect(&SpiInstance, 0x00);
			Status = XSpiPs_Transfer(&SpiInstance, (u8*)&TxBuffer, (u8*)&RxBuffer, 8);
			if(Status != XST_SUCCESS) {
				printf("XSpiPs_Transfer failed\n")
			}


			NumBytesRcvd = 0;
			
			//XSpi_SetControlReg(&Spi,0x60);
			XSpi_WriteReg((SpiInstance.SpiConfig.BaseAddr), XSPIPS_TXD_OFFSET, TxBuffer[0]);
			XSpi_WriteReg((SpiInstance.SpiConfig.BaseAddr), XSPIPS_TXD_OFFSET, TxBuffer[1]);
			//XSpi_SetControlReg(&Spi,0x02);
			XSpi_WriteReg((SpiInstance.SpiConfig.BaseAddr), XSPIPS_TXD_OFFSET, TxBuffer[2]);
			XSpi_WriteReg((SpiInstance.SpiConfig.BaseAddr), XSPIPS_TXD_OFFSET, TxBuffer[3]);

			while (!(XSpi_ReadReg(Spi.BaseAddr, XSP_SR_OFFSET) & XSP_SR_TX_EMPTY_MASK));

			while ((XSpi_ReadReg(Spi.BaseAddr, XSP_SR_OFFSET) & 	XSP_SR_RX_EMPTY_MASK) == 0) {
				printf("In While\n");
				RxBuffer[NumBytesRcvd++] = XSpi_ReadReg((Spi.BaseAddr), XSP_DRR_OFFSET);
			}

			for(i=0;i<4;i++){
				printf("rx %04x \n", RxBuffer[i]);
			}
			usleep(1000000);
	}


    cleanup_platform();
    return 0;
}

Console (uart) out:

SPI Example
In While
In While
In While
In While
In While
In While
rx a0a0
rx 0505
rx a0a0
rx 0505
XSpiPs_Transfer failed
rx a0a0
rx 0505
rx a0a0
rx 0505
XSpiPs_Transfer failed
In While
In While
In While
In While
rx a005
rx a005
rx a005
rx a005
XSpiPs_Transfer failed
rx a005
rx a005
rx a005
rx a005
XSpiPs_Transfer failed
In While
In While
In While
In While
rx a005
rx a005
rx a005
rx a005

Help Object detection and tracking with color space conversion and morph operators

brhn — Wed, 13 Nov 2024 14:59:55 GMT

Help Object detection and tracking with color space conversion and morph operators

I want to implement with boundingbox the opencv example code on the link:

https://www.opencv-srf.com/2010/09/object-detection-using-color-seperation.html

I need to conversion XF_8UC1 to XF_8UC3 to hsv2rgb

and I also get hanging error in the for loop and xf::cv::boundingbox:

pixel = imgOutput.read_float(i);

#include "xf_colordetect_config.h"

static constexpr int __XF_DEPTH = (HEIGHT * WIDTH * (XF_PIXELWIDTH(IN_TYPE, NPC1)) / 8) / (INPUT_PTR_WIDTH / 8);
static constexpr int __XF_DEPTH_OUT = (HEIGHT * WIDTH * (XF_PIXELWIDTH(OUT_TYPE, NPC1)) / 8) / (OUTPUT_PTR_WIDTH / 8);
static constexpr int __XF_DEPTH_FILTER = (FILTER_SIZE * FILTER_SIZE);

void colordetect_accel(ap_uint<INPUT_PTR_WIDTH>* img_in,
                       ap_uint<OUTPUT_PTR_WIDTH>* img_out,
                       int rows,
                       int cols) {
    #pragma HLS INTERFACE m_axi port=img_in offset=slave bundle=gmem0 depth=__XF_DEPTH
    #pragma HLS INTERFACE m_axi port=img_out offset=slave bundle=gmem4 depth=__XF_DEPTH_OUT
    #pragma HLS INTERFACE s_axilite port=rows
    #pragma HLS INTERFACE s_axilite port=cols
    #pragma HLS INTERFACE s_axilite port=return

    // Initialize input and intermediary matrices
    xf::cv::Mat<IN_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_IN_1> imgInput(rows, cols);
    xf::cv::Mat<IN_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_RGB2HSV> rgb2hsv(rows, cols);
    xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_HELP_1> imgHelper1(rows, cols);
    xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_HELP_2> imgHelper2(rows, cols);
    xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_HELP_3> imgHelper3(rows, cols);
    xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_HELP_3> imgHelper4(rows, cols);
    xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_HELP_3> imgHelper5(rows, cols);
    xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_OUT_1> imgOutput(rows, cols);
    xf::cv::Mat<OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_OUT_1> imgOutputwithBox(rows, cols);

    unsigned char low_thresh[MAXCOLORS] = {170, 150, 60};
    unsigned char high_thresh[MAXCOLORS] = {179, 255, 255};
    unsigned char _kernel[FILTER_SIZE * FILTER_SIZE] = {1, 1, 1, 1, 1, 1, 1, 1, 1}; // 3x3 kernel for erosion/dilation

    // Load input image to xf::cv::Mat format
    xf::cv::Array2xfMat<INPUT_PTR_WIDTH, IN_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_IN_1>(img_in, imgInput);

    // RGB to HSV conversion
    xf::cv::bgr2hsv<IN_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_IN_1, XF_CV_DEPTH_RGB2HSV>(imgInput, rgb2hsv);

    // Color thresholding to detect specific colors
    xf::cv::colorthresholding<IN_TYPE, OUT_TYPE, MAXCOLORS, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_RGB2HSV,
                              XF_CV_DEPTH_HELP_1>(rgb2hsv, imgHelper1, low_thresh, high_thresh);

    // Apply morphological operations (erode + dilate)
    xf::cv::erode<XF_BORDER_CONSTANT, OUT_TYPE, HEIGHT, WIDTH, XF_KERNEL_SHAPE, FILTER_SIZE, FILTER_SIZE, ITERATIONS,
                  NPC1, XF_CV_DEPTH_HELP_1, XF_CV_DEPTH_HELP_2>(imgHelper1, imgHelper2, _kernel);
    xf::cv::dilate<XF_BORDER_CONSTANT, OUT_TYPE, HEIGHT, WIDTH, XF_KERNEL_SHAPE, FILTER_SIZE, FILTER_SIZE, ITERATIONS,
                   NPC1, XF_CV_DEPTH_HELP_2, XF_CV_DEPTH_HELP_3>(imgHelper2, imgHelper3, _kernel);

    xf::cv::dilate<XF_BORDER_CONSTANT, OUT_TYPE, HEIGHT, WIDTH, XF_KERNEL_SHAPE, FILTER_SIZE, FILTER_SIZE, ITERATIONS,
                          NPC1, XF_CV_DEPTH_HELP_2, XF_CV_DEPTH_HELP_3>(imgHelper3, imgHelper4, _kernel);
    xf::cv::erode<XF_BORDER_CONSTANT, OUT_TYPE, HEIGHT, WIDTH, XF_KERNEL_SHAPE, FILTER_SIZE, FILTER_SIZE, ITERATIONS,
                     NPC1, XF_CV_DEPTH_HELP_1, XF_CV_DEPTH_HELP_2>(imgHelper4, imgOutput, _kernel);

    xf::cv::hsv2rgb<XF_8UC1, XF_8UC1, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_IN_1, XF_CV_DEPTH_IN_1>(imgOutput, imgOutputwithBox);

    // Calculate bounding box by iterating through imgThresholded
    //int min_x = cols, min_y = rows, max_x = 0, max_y = 0;

	/*for (int i = 0; i < rows; i++) {
		for (int j = 0; j < cols; j++) {
				unsigned char pixel;
				pixel = imgOutput.read_float(i);
				if (pixel > 0) { // If pixel is part of the detected region
				// Update bounding box coordinates
				if (j < min_x) min_x = j;
				if (j > max_x) max_x = j;
				if (i < min_y) min_y = i;
				if (i > max_y) max_y = i;
			}
		}
	}*/


	// Define the bounding box region as an xf::cv::Rect object
	/*xf::cv::Rect_<int> roi;
	roi.x = min_x;
	roi.y = min_y;
	roi.width = max_x - min_x + 1;
	roi.height = max_y - min_y + 1;*/

	// Define the bounding box color (e.g., green)
	//xf::cv::Scalar<4, unsigned char> color(0, 255, 0, 255); // RGBA format, green color

    // Draw bounding box on the thresholded image
    //xf::cv::boundingbox<OUT_TYPE, HEIGHT, WIDTH, 1, NPC1, XF_CV_DEPTH_HELP_1>(imgOutput, &roi, &color, 1);

    // Step 5: Convert processed data to output array
    xf::cv::xfMat2Array<OUTPUT_PTR_WIDTH, OUT_TYPE, HEIGHT, WIDTH, NPC1, XF_CV_DEPTH_OUT_1>(imgOutput, img_out);
}

Which NVMe does AES-ACC-HSIO-M2-G accessory board accommodate?

Ratin — Tue, 29 Oct 2024 21:06:03 GMT

Looks like the one I bought from Amazon (see attached) is a hair wide so it wont go into the slot. Is there any preferred model of NVMe 2260 for Key-B that I should buy (Amazon link preferred?
Thank you.

ZUB1CG board file or ref design, Vivado 2019.2 version

Ratin — Mon, 28 Oct 2024 18:33:44 GMT

Hello, Is there any support for this board for Vivado / Vitis 2019.2 version?

I found some ref design / board files in the repo but they are from 2017 and 2018 versions.

Thanks much

Ratin

Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): solve xsdb segmentation fault

Jan Cumps — Sat, 19 Oct 2024 17:16:45 GMT

You can run Vivado and Vitis on WSL2. One reason to do that, is that you can run the provided build scripts as is.
You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7).
It 'll also allow you to build a PetaLinux image.

On my WSL2 install, I got a segmentation fault when the xilinx debugger service started: I got this message in XSDB console:
xsdb: line 82: 4572 Segmentation fault Core dumped...

This is a known issue, and AMD provides a fix.

Navigate to the Vitis install

cd /tools/Xilinx/Vitis/2024.1/bin/unwrapped/lnx64.o

Then perform these steps to install a newer version of rlwrap:

sudo apt install rlwrap
sudo mv rlwrap rlwrap.old
sudo ln -s /usr/bin/rlwrap rlwrap

That's it, from now on, the XSDB console works:

Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): connect to the USB debugger as a normal user

Jan Cumps — Sat, 19 Oct 2024 13:54:13 GMT

When you try to connect to your debugger from WSL2, you 'll notice that Vitis and Vivado only find your board, if you run the programs via sudo. There is a solution though:

prerequisite: know how to attach your USB board / debugger to WSL2: Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): attach and detach your USB debugger

The udev service should run on WSL2. This is the mechanism that will allow user level access to the USB device, according to rules.

sudo /etc/wsl.conf

[boot]
command="service udev start"

Restart is not needed at this point. The service will be (re)started a bit later.

Enable rules for the device:

Most PYNQ compatible boards have an FTDI USB JTAG / COM device. You can just use the OpenOCD instructions.

Unplug the device, then from a WSL2 terminal prompt:

curl -fsSL https://raw.githubusercontent.com/openocd-org/openocd/master/contrib/60-openocd.rules | sudo tee /etc/udev/rules.d/60-openocd.rules
sudo service udev restart
sudo usermod -aG plugdev $USER

Plug the board into your computer, and hand the USB device over to WSL2: Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): attach and detach your USB debugger .

You are now able to start Vivado or Vitis with your normal Linux user account. The programs will be able to connect and control your FPGA.

Easiest way to test, is to open a Vivado project, and connect the hardware manager:

Happy signal:

You only need to set this up once. From now on, WSL2 will start up with these settings.

Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): attach and detach your USB debugger

Jan Cumps — Sat, 19 Oct 2024 13:30:54 GMT

If you also want to program or debug your design from Vivado or Vitus on WSL2, you will find that it's not able to detect your board / debugger USB.
You will first have to hand over control of the USB port to WSL2. Follow instructions of Connecting USB devices to WSL to get the necessary commands set up in Windows, and how to use them.

Create Windows shortcuts to attach and detach your debugger to WSL2

assumption: you are able to attach and detach your USB debugger to WSL2 from an administrator Windows command line, as described in the instructions above.

First, create a batch file that can run the attach and detach instructions:

I called mine attachpynq.bat , and placed it in the C:\Xilinx folder

"C:\Program Files\usbipd-win\usbipd.exe" wsl %1 --busid %2

Then I created 2 Windows shortcuts, one for attach, one for detach:

I first created the attach one. I right-clicked in the folder where I wanted to create it, and selected Windows ShortCut.

Target: C:\Xilinx\attachpynq.bat attach 2-1 & pause

Start in: my home folder (it's not relevant in this scenario)

Advanced -> Run as administrator

Rename it (I use "attach PYNQ to WSL2").

Confirm and test it:

Start WSL2, if not running yet. You can do this by opening a WSL2 terminal.

When you execute the shortcut (double-click it), you'll first be prompted to run it as admin. Select Yes.

Then the script will ask you to enter the WSL2 root / sudo user's password.

If you manage to enter the right password, the USB port will be passe through to WSL2:

Now create a detach shortcut:

Copy the attach one. Rename it (I use "detach PYNQ to WSL2"). Right click, select Properties.

In the Target field, replace attach by detach.

Test, by executing the shortcut. The USB device should now disappear in the WSL2 /dev directory:

That's it. Enjoy.

Why the need of the batch file?

We need to achieve two things:

Run the usbipd command as Windows administrator, and
allow you to enter the Linux root / sudo password

Creating the shortcut is an easy way to execute the commands as admin.

If I would not use a batch script and put all commands in the Target of the shortcut, it would not prompt for the password. When you put the commands in a batch file and call that from the shortcut, it waits.

Windows experts may know a better way to handle this. Comment if you have an easier solution.