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Learning FPGA

danielpgleason — Mon, 04 May 2026 18:33:04 GMT

Does anyone know of any good learning resources about how to start learning FPGA? I've been a software engineer for several years and the FPGA world is quite new to me. I'm trying to implement RMII but have been struggling a lot. I purchased a logic analyzer but I don't know what I'm looking at. I need something that will tell me how to properly understand and read datasheets, know how to debug signals, how to understand what VHDL is good and what is bad. How to read RTL generations..Etc

I'm starting from the beginning. Any resources or materials are greatly appreciated.

RE: Learning FPGA

michaelkellett — Wed, 06 May 2026 08:35:25 GMT

Hello Daniel,

I see that you are a new member at E14. You posted this question in two E14 groups which is not a good thing to do because it splits the thread so people do not see each others' answers.

On E14 you will almost always get a better result by posting once in about the right place 🙂

My answer to your question is in the other group !

RE: Learning FPGA

fpgaguru — Tue, 05 May 2026 17:34:50 GMT

Retired engineer with 35 years of FPGA design experience here, 24 of them at Xilinx/AMD. Tooting my own horn, you may want to take a look at the Element14 blog "The Art of FPGA Design", quite old now but still very relevant. In particular Post 3 has a link to the book I used to learn VHDL in 1995, Peter Ashenden's "The VHDL Cookbook"

What I really want to point out is that "learning FPGA", or "learning VHDL" or Verilog or whatever should not be a goal in itself, it's like saying "I need to learn to use a hammer", what you should aim for is "I want to learn how to build a house". What you really want is to learn digital hardware design, especially if you come from a software engineering background. VHDL is just another programming language and FPGA design is the ability to use a tool like Vivado or Vitis, how to use these tools and skills is the actual challenge.

RE: Learning FPGA

saramic — Mon, 04 May 2026 22:47:35 GMT

I have no expertise in this area, but from my research I am planning (in some future) to follow this path:

I have this book
Getting Started with FPGAs
Digital Circuit Design, Verilog, and VHDL for Beginners
by Russell Merrick
September 2023, 320 pp.
ISBN-13:
9781718502949
The author recommends his board for getting started
The Go Board -> https://nandland.com/the-go-board/ ~$70
The Best FPGA Development Board For Beginners
Quick overview by the author
My book Getting Started with FPGAs is NOW AVAILABLE! - nandland
https://youtu.be/4UpMB9kNt0s
the code
https://github.com/nandland/getting-started-with-fpgas

As I mentioned - I have 0 experience but this looks like the learning path I would take to get a good understanding - hope that helps

What is the latest Lattice eval board?

Jayfox — Fri, 06 Mar 2026 10:41:09 GMT

Looking for a low-cost FPG eval board to start learning Verilog/VHDL and work with soft-core .

Lattice seems to be low cost / low power: what is the latest eval board?

RE: What is the latest Lattice eval board?

dang74 — Sun, 08 Mar 2026 15:49:30 GMT

Some of their other newer families have added similar packages. Good move on their part... because BGA imposes a barrier of entry in terms of board cost and assembly.

RE: What is the latest Lattice eval board?

michaelkellett — Sun, 08 Mar 2026 14:32:59 GMT

I too would have sworn on my favourite pet's life that the ECP5 was only available in BGA but it seems to also exist in TQFP144:

I looked it up on Octopart and Mouser have stock at a reasonable price. The prices from Microchip USA and Worldway are hard to understand.

Mouser warn of long delivery times on the website but the 292 in stock seems to be true.

RE: What is the latest Lattice eval board?

dang74 — Sun, 08 Mar 2026 13:34:19 GMT

[quote userid="121623" url="~/technologies/fpga-group/f/forum/56744/what-is-the-latest-lattice-eval-board/234274"]Lattice offer hand solderable (just) 48 pin packages for the iCE49UP5k, easier to use and install tools and lower entrance costs[/quote]

One Lattice family I am interested in is the ECP5 series. It's what I'd characterize as medium density. At any rate I could have sworn that they were only available in BGA package. I checked again yesterday and the 24,000 and 44,000 LE devices are available in 144 pin TQFP packages... needless to say, I was very happy to see this.

RE: What is the latest Lattice eval board?

michaelkellett — Sun, 08 Mar 2026 09:46:01 GMT

Hello dang74

I did notice it and dismissed it as not being in line with the OP's aims (VHDL.Verilog, learing and interest in soft cores.

It is just possible that Cologne Chip will get this architecture off the ground but right now it just doesn't have the support and eco system to make it an attractive proposition for small scale or DIY use.

They will need to offer a range of packages and support for industry standard IO (which still definitely includes 3.3V).

The only mainstream distribution is via Digi key and the only package is 324 ball 0.8mm BGA (at $21.59 10off).

It's just a lot easier to get started with Efinix, Lattice, Altera, Xilinx or Gowin.

Lattice offer hand solderable (just) 48 pin packages for the iCE49UP5k, easier to use and install tools and lower entrance costs.

The GateMate part is interesting in that it has an architecture quite a bit different from the others but it isn't where I would recommend a beginner to start.

RE: What is the latest Lattice eval board?

dang74 — Sat, 07 Mar 2026 16:53:19 GMT

michaelkellett when you were at the olimex site did you notice the GateMateA1-EVB board. (Full disclaimer, it's not Lattice so it's a bit off topic). Anyway, on the positive side it has 20,480 logic cells and 64Mbit of PSRAM. Of course you have to use open source YOSYS for development so that will be a commitment for some. On my end, I am still wrapping my mind around what exactly PSRAM is and whether or not I can use it as easily SRAM. Perhaps the most disappointing thing for me is that the GPIO tops out at 2.5V... does that mean I've lived long enough to see the phasing out of 3.3V for single ended logic?

RE: What is the latest Lattice eval board?

venkat01 — Sat, 07 Mar 2026 15:23:58 GMT

Nandland's Go Board along with the book is best for beginners.

RE: What is the latest Lattice eval board?

michaelkellett — Sat, 07 Mar 2026 09:53:10 GMT

The biggest FPGA that Olimex support with a board is on the iCE40HX8K-EVB

But this is an early generation ICE40 and not as useful (in most cases ) as the later iCE40UltraPlus parts.

Look here for Lattice's suggestions for iCE40 boards:

https://www.latticesemi.com/solutionsearch?qiptype=982db688d64345bbb3af29e62fee1dc3&active=board

The iCE40 is not very suitable for soft_core work but that has no relevance if you are just starting to learn VHDL or Verilog.

(There is some soft core support for soft-cores on the iCE40UP5 but the UP5 is really too small for a decent soft-core)

This boards is all you need to get started:

https://tinyvision.ai/products/fpga-development-board-upduino-v3-1

There are much cheaper boards based on the Gowin FPGAs available from AliExpress

https://www.aliexpress.com/w/wholesale-fpga-dev-board.html

They also have pretty cheap Altera or AMD/Xilinx boards as well but you might find that it is hard to get going with the level of support you will get from these. But you will get a much bigger FPGA for your money.

IMO the Lattice tools are the easiest for a complete beginner to get started.

RE: What is the latest Lattice eval board?

dang74 — Sat, 07 Mar 2026 07:56:27 GMT

Good old Olimex. It's been some time since I checked them out. Thanks for bringing them back on my radar. 🙂

RE: What is the latest Lattice eval board?

shabaz — Sat, 07 Mar 2026 04:46:58 GMT

It may be worth to check out Olimex, they offer a couple of low-cost dev boards for Lattice parts (quite nice, the Olimex boards include SRAM too).

RE: Ultra96-V2 – VART not found / Unable to run .xmodel

iksevas — Fri, 13 Feb 2026 21:36:31 GMT

Could you start with a Ultra96v2 BSP and add the necessary libraries to that?

Ultra96-V2 – VART not found / Unable to run .xmodel

wael_gu — Fri, 13 Feb 2026 20:34:44 GMT

Hello everyone,

I am working with an Ultra96-V2 (Zynq UltraScale+ MPSoC) board and trying to deploy an AI model using Vitis AI.

Here is my current situation:

I successfully quantized and compiled my model on my PC using Vitis AI Docker (CPU version 2.5.0).
I transferred the generated .xmodel file (resnet50.xmodel) to the Ultra96-V2 board.
The board is running a Linux image (ultra96v2-2020-1).
When I try to run:

I get:

I also checked for VART libraries using:

No results were found.

It seems that Vitis AI Runtime (VART) is not installed in the current image.

My questions are:

What is the recommended Vitis AI image for Ultra96-V2?
Is there a prebuilt SD card image that includes VART and DPU support?
If manual installation is required, what is the correct procedure for installing VART on Ultra96-V2 (aarch64)?

Any help or guidance would be greatly appreciated.

Thank you.

In hackathalon FPGA projects, I dont know why but i only see health or disease based projects saying that it will save 2 to 5 minutes of processing,and they even win many times

Aniket_kumar_raj — Tue, 06 Jan 2026 11:26:04 GMT

Judges should not select health based projects as Saviour to the world, something more can be done with FPGA if a person is creative,i recently hosted a offline FPGA hackathon ane everyone made a project on Boilogy realated thing, and this is what made me hate every project which is health based project

I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

micheal.embedded — Sun, 04 Jan 2026 17:48:45 GMT

I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

On paper, using the PL for acceleration always looks like the right move. In practice, I keep finding that the integration cost—AXI plumbing, cache coherency, DMA setup, and tool friction—ends up dominating the project far more than the accelerator itself.

I’ve had projects where the hardware worked, but performance was still disappointing because the PS–PL interface became the bottleneck, or where workflow choices (Vivado vs Vitis) boxed me into painful rework later.

So my question is: at what point do you personally decide that moving functionality into the PL is worth it on Zynq, and when do you step back and keep things in software instead?

I’d really like to hear what decision signals or failure experiences others use to make that call.

RE: I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

venkat01 — Mon, 05 Jan 2026 13:11:07 GMT

Well, I mostly deal with the designs targeting the PL only and I prefer using Microblaze instead of the PS, power profile and the latency are the key factors for the designs in my line of work.

For resolving the latency issues it's preferable to move onto the US/US+ MPSoC's , the throughput over the PS-PL bridge is much better with min optimisations.

RE: I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

wolfgangfriedrich — Mon, 05 Jan 2026 02:45:59 GMT

The only way to win the performance game is, when the data is entering the PL side directly from external sources. I have fast ADCs connected straight to the PL through QSPI, do the expensive filtering in the PL side and the pipe it through a AXI-FIFO to the PS side for storage.

As you said, moving data PS -> PL -> processing -> PS is not efficient.

RE: I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

micheal.embedded — Sun, 04 Jan 2026 23:41:33 GMT

😂😂😂
thought we all like a challange

RE: I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

embeddedguy — Sun, 04 Jan 2026 18:22:24 GMT

For me TBH reaching at the point where you are with these FPGA is itself challenging. So congratulations that you have reached that point.

I have some Xilinx boards and I reach a point where I have to give up..!

Suggestion needed regarding Zynq ultrascale+ FPGAs

Praj — Fri, 24 Oct 2025 21:11:46 GMT

Hello, I am looking for a Zynq Ultrascale+ based FPGA with the following features

1) (PS + PL)

2) RDIMM slots

3) PL can access the RDIMM

I am implementing a custom memory controller, so I need an FPGA with an ARM core and programmable logic wth DIMM slots.

Please let me know if anyone is aware of FPGAs that meet the above specifications.

Thanks,

Issues with outputs on new ZCU104 eval kit

Akropolidis — Mon, 13 Oct 2025 15:57:00 GMT

I just obtained a new ZCU104 Eval kit (AMD Zynq Ultrascale+ MPSoC ZCU104 Evaluation Kit) and I'm running into some issues with my bitstreams.

I have a bitstream implementation of a ARM Cortex-M0 mcu and tested this on the board and observed the expected results. Now I want to move development to another ZCU104 eval board that I've just obtained, I flashed the exact bitstream but the I/Os don't seem to be working. In debugging, I tested with a simpler design below:

`timescale 1ns/1ps
module test(
input logic clk_p,
input logic clk_n,
output logic clk_50,
// output logic sys_clk,
// output logic locked,
output logic [2:0] led
);
logic sys_clk;
logic locked;
IBUFGDS osc_clk (
.O(sys_clk),
.I(clk_p),
.IB(clk_n)
);
clk_wiz_1 clock_test
(
// Clock out ports
.clk_out1(clk_50), // output clk_out1
// Status and control signals
.locked(locked), // output locked
// Clock in ports
.clk_in1(sys_clk) // input clk_in1
);
assign led[0] = locked;
assign led[1] = 1'b1;
assign led[2] = 1'b1;
endmodule

# Clock - ZCU104 125MHz System Clock (Differential)
set_property PACKAGE_PIN F23 [get_ports clk_p]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property PACKAGE_PIN E23 [get_ports clk_n]
set_property IOSTANDARD LVDS [get_ports clk_n]
##############################################################
# Status LEDs - ZCU104 User LEDs
##############################################################
set_property PACKAGE_PIN D6 [get_ports clk_50]
set_property IOSTANDARD LVCMOS33 [get_ports clk_50]
set_property PACKAGE_PIN D5 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN A5 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN B5 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]

What's interesting is I did observe an expected output from driving the pins of the led directly with assign statements as shown above. But the led connected to locked which is an output driven by the clock wiz module is not set. Running post synthesis and implementation simulations indicate the locked signal and clock wizard work fine so I'm confused.

I think the issue is in the hardware configuration, are there additional bringup steps that I'm missing? I've referenced the documentation and SW6 is set to JTAG mode (0000/0x0) but I can't seem to find the issue.

Avnet UltraZed-EG PCIe Carrier Card - Golden Constraints

slavikolev-ilt — Tue, 16 Sep 2025 12:14:58 GMT

Hello all,

Thank you so much for the help on my previous post! Unfortunately, I am still missing some very important reference design files. Namely, I am looking for a golden constraints file, meaning constraints for every peripheral of the PCIe card. However, if you're able to point me to a resource on official reference designs for UltraZed and the PCIe card more broadly (or even an unofficial reference design), I would very much appreciate that. Most of the links on the official product page are dead, sadly.

Thank you very much!

Slavi