FPGA

FPGAhttps://community.element14.com/technologies/fpga-group/FPGA discusses the latest trends in programmable logic devices, and offers access to education, workshops, webinars on FPGAs, SoCs, and other programmable devices.en-USTelligent Community 12<link>https://community.element14.com/technologies/fpga-group/b/blog/posts/fast-vhdl-cordic-sine-and-cosine-component-on-lattice-xp2-device-using-diamond-3-12-part-2?CommentId=f131aa04-2bef-4518-a80a-56135f08fffe</link><pubDate>Sun, 07 Jun 2026 14:46:00 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:f131aa04-2bef-4518-a80a-56135f08fffe</guid><dc:creator>jc2048</dc:creator><description>Here is the sine and cosine in more detail and here's the spectrum view with, and this surprised me, a THD figure of 0.005% (if you look closely, there isn't anything much at the actual harmonics). So the CORDIC calculation of the sine must be fairly accurate. Presumably the other lines, clustered around the fundamental, are intermodulation products (but what would be the source of the interference?).</description></item><item><title /><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/lattice-icestick-evb-generating-three-phase-sinewaves-with-sigma-delta-dacs-using-icecube2-and-vhdl?CommentId=3b6a72ee-455d-4ec0-a60b-63bb196905af</link><pubDate>Sun, 07 Jun 2026 14:42:00 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3b6a72ee-455d-4ec0-a60b-63bb196905af</guid><dc:creator>jc2048</dc:creator><description>Here are two of the output waveforms in higher resolution than my 8-bit Tek scope can manage. Quite nice looking sine waves, though if we look at it in the spectrum view there are enough harmonics present for a THD figure of about 0.6%. The resolution of the PicoScope is good enough to show me some intriguing, regular sidebands around the fundamental at 50Hz. This next spectrum view, over a wider span, is also interesting because it shows some output aliasing at multiples of my sample rate (12kbps). Although they're fairly well down, the simple RC filter hasn't totally wiped them out.</description></item><item><title>Wiki Page: Featured Content Triptych Setup Dochttps://community.element14.com/technologies/fpga-group/w/setup/26642/featured-content-triptych-setup-docThu, 28 May 2026 12:55:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7e3dbc4b-ad3d-4d73-aeac-6597508eadc2e14sbhargavPath to Programmable III Collaborated with Path III is the third session in the element14 Community’s structured FPGA-based SoC training. The first Path was held in 2018 and focused on programmable logic devices PLDs and featured the AVNET MiniZed development board, based on AMD’s Zynq-7000 SoC. Path II convened in 2019 and offered more advanced learning opportunities and featured the AVNET Ultra96-V2 development board, based on AMD’s Zynq UltraScale+ MPSoC. Path III will double the fun by offering structured training on both the MiniZed and Ultra96-V2 boards. Each training track will be followed by a design/build phase. Learn More Achieving Deterministic Latency with the AMD Kria ™ ︎ K24 SOM Adaptive Computing The Bulls Eye® High Performance Test System Samtec Flyover® Technology for FPGA Apps Memory Storage for FPGA Applications Accelerating Embedded Vision with the CrossLink ™ -NX FPGA On Demand Webinars: Getting Started with the AMD Spartan ™ ︎ UltraScale+ ™ ︎ FPGA SCU35 Eval Kit PYNQ-Z2 Workshop Series: FPGA Experiments With Xilinx Pynq-Z2 Power Integrity Effects on FPGA Functionality and Performance Leveling-Up Your FPGA Skills: An Expert Panel Discussion Getting Started with FPGAs: An Expert Panel Discussion Summer of FPGA: Software and FPGA: How to Get the Bits to Flip? Intro to Smart Embedded Vision (SEV) Using a PolarFire ® FPGA Building Processor Based Systems on Lattice FPGAs Using PropelForum Post: RE: AMD Changes Vivado License - Locks out Linux Support from Basic tierhttps://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235724Thu, 21 May 2026 13:46:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:1cef9723-cb6b-41e0-bf69-d4cbf4ddaec3wolfgangfriedrich[quote userid="36226" url="~/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235702"]Now I'm slightly less envious of the four people who won those nice Xilinx boards recently.[/quote] The option is to use 2025.2.1 and not upgrade any further.Forum Post: RE: AMD Changes Vivado License - Locks out Linux Support from Basic tierhttps://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235722Thu, 21 May 2026 13:03:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:0aa099f7-10a3-4df9-95da-d35d089ef3cfkk99Maybe hobbyists that do not want to use VM or switch environments will start with other alternatives, like Gowin.Forum Post: RE: AMD Changes Vivado License - Locks out Linux Support from Basic tierhttps://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235717Thu, 21 May 2026 12:38:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:32d1609e-0dff-4af5-a111-0275cc766308bradfordmillerParticularly if you are using PetaLinux or the new EDF. Maybe paying for EDF (too bad "classic" MicroBlaze users) is why they're pushing the paid CORE package? At least 2025.2 and before are still available free (for the smaller chips anyway)! I wouldn't mind paying for CORE so much if it was something I could do every 3 years which is about how I use the current upgrade cycle (i'm still on 2023.1). But for that "privilege" I'd have to spring for ENTERPRISE...Forum Post: RE: AMD Changes Vivado License - Locks out Linux Support from Basic tierhttps://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235702Thu, 21 May 2026 08:05:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:137f8965-a423-4e27-9724-8c97a405cce2jc2048Now I'm slightly less envious of the four people who won those nice Xilinx boards recently. "Are there alternatives?" Lattice, Microchip, et al. I've got the no-cost editions of Diamond (Lattice) and Radiant (Lattice) running happily on Xubuntu 22.04. Libero (Microchip) installed ok, but I haven't done the licence serving part yet, so can't say for sure it runs happily. I think the basic level of Altera's Quartus (Lite edition) is available for Linux, but the 3rd party simulator is not for 22.04 (you'd need Red Hat, or one of its derivatives). I might give it a try as I've got the Vidor 4000 board and at some point my old Windows 8.1 laptop will probably die.Forum Post: RE: AMD Changes Vivado License - Locks out Linux Support from Basic tierhttps://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235695Wed, 20 May 2026 22:25:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:e560dd00-0353-4dd0-a12d-b0133a23b4bddyessggAny word as to why Linux support is excluded from the Basic tier? I would think Linux would be the primary platform people use these tools on.Forum Post: AMD Changes Vivado License - Locks out Linux Support from Basic tier, Edit: Maybe nothttps://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier-edit-maybe-notWed, 20 May 2026 22:11:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8e4fe275-4a78-4bb2-9c72-c65999a11d1estantoWhat was arguably an avenue into free development, being able to use Linux and then Vivado, is now locked down into buying a supported Windows license to use free Vivado. If you want Linux support you now have to pay for it. $1,200+. Existing installations will likely still work. https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado/vivado-licensing-options.html Are there alternatives? Maybe it works with Wine? Edit: 1st June 2026 Looks like they changed their minds! https://www.linkedin.com/posts/vivado-licensing-options-share-7466166724040564736-4D76/ https://adaptivesupport.amd.com/s/article/Adding-LINUX-support-back-for-the-BASIC-free-version-of-Vivado?language=en_USlinux supportlicensevivadoamdForum Post: RE: Learning FPGAhttps://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpga/235382Wed, 06 May 2026 08:35:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:0ec8336b-4a9d-46be-9590-4b781d57e1a7michaelkellettHello Daniel, I see that you are a new member at E14. You posted this question in two E14 groups which is not a good thing to do because it splits the thread so people do not see each others' answers. On E14 you will almost always get a better result by posting once in about the right place My answer to your question is in the other group ! MKForum Post: RE: Learning FPGAhttps://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpga/235369Tue, 05 May 2026 17:34:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b882eff2-6bfe-4710-b8c7-f2b4ab91ef18fpgaguruRetired engineer with 35 years of FPGA design experience here, 24 of them at Xilinx/AMD. Tooting my own horn, you may want to take a look at the Element14 blog "The Art of FPGA Design" , quite old now but still very relevant. In particular Post 3 has a link to the book I used to learn VHDL in 1995, Peter Ashenden's "The VHDL Cookbook" What I really want to point out is that "learning FPGA", or "learning VHDL" or Verilog or whatever should not be a goal in itself, it's like saying "I need to learn to use a hammer", what you should aim for is "I want to learn how to build a house". What you really want is to learn digital hardware design, especially if you come from a software engineering background. VHDL is just another programming language and FPGA design is the ability to use a tool like Vivado or Vitis, how to use these tools and skills is the actual challenge.File: My book Getting Started with FPGAs is NOW AVAILABLE!https://community.element14.com/technologies/fpga-group/m/managed-videos/151290Mon, 04 May 2026 22:48:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:9ca51cc4-3fc4-4920-81d4-131561d48d4esaramicBuy the Book: https://nandland.com/book-getting-started-with-fpga/ Buy the Go Board: https://nandland.com/the-go-board/ After 2 years my book Getting Started with FPGAs is now available for order! This is by far the most comprehensive and best con...Forum Post: RE: Learning FPGAhttps://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpga/235335Mon, 04 May 2026 22:47:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b729cb0c-126e-4b3d-8313-c9e018f33f98saramicI have no expertise in this area, but from my research I am planning (in some future) to follow this path: I have this book Getting Started with FPGAs Digital Circuit Design, Verilog, and VHDL for Beginners by Russell Merrick September 2023, 320 pp. ISBN-13: 9781718502949 The author recommends his board for getting started The Go Board -> https://nandland.com/the-go-board/ ~$70 The Best FPGA Development Board For Beginners Quick overview by the author My book Getting Started with FPGAs is NOW AVAILABLE! - nandland https://youtu.be/4UpMB9kNt0s the code https://github.com/nandland/getting-started-with-fpgas As I mentioned - I have 0 experience but this looks like the learning path I would take to get a good understanding - hope that helpsForum Post: Learning FPGAhttps://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpgaMon, 04 May 2026 18:33:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8c12b4b4-1164-425d-93a2-f6d2eb05bbeddanielpgleasonDoes anyone know of any good learning resources about how to start learning FPGA? I've been a software engineer for several years and the FPGA world is quite new to me. I'm trying to implement RMII but have been struggling a lot. I purchased a logic analyzer but I don't know what I'm looking at. I need something that will tell me how to properly understand and read datasheets, know how to debug signals, how to understand what VHDL is good and what is bad. How to read RTL generations..Etc I'm starting from the beginning. Any resources or materials are greatly appreciated.<link>https://community.element14.com/technologies/fpga-group/b/blog/posts/lattice-ice40up5k-evb-evaluation-board---part-2-using-the-dsp-multiplier?CommentId=eaad09f6-87fb-4c10-bcfc-3a8152d764b0</link><pubDate>Sun, 19 Apr 2026 14:22:00 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:eaad09f6-87fb-4c10-bcfc-3a8152d764b0</guid><dc:creator>jc2048</dc:creator><description>I mentioned in the blog that what I was generating with my simple, single multiply of two signed quantities wasn't straight amplitude modulation, but rather double-sideband, suppressed-carrier. Here I've reworked the VHDL to give some actual AM. This multiplies the envelope by 0.3, adds 0.5 to make it purely positive, and then multiplies it with the carrier. You can see now, from the FFT, that there's a carrier (7kHz) and two sidebands, each spaced 440Hz away from the carrier. Here's the VHDL ---------------------------------------------------------------------- -- ***** ice40up5k_evn_test_mult.vhd ***** -- -- -- -- Lattice ICE40UP5K evaluation board multiplier test. -- -- Generates fixed pair of CORDIC 16-bit sine waves, multiplies them-- -- and formats result for an S/PDIF serial optical link. -- -- -- ---------------------------------------------------------------------- -- (C)2026 Jon Clift -- -- Free to use however you want. No warranty as to correctness. -- -- No guarantee of fitness for any purpose. No obligation to support-- ---------------------------------------------------------------------- -- Rev Date Comments -- -- 01 25-Mar-2026 based on ice40up5k_evn_test.vhd -- -- 02 12-Apr-2026 hacked to give amplitude modulation -- ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity ice40up5k_evn_test is port( clk_12: in STD_LOGIC; --- system clock in (from 12MHz oscillator) clk_12_288: in STD_LOGIC; --- clock in (from my 12.288MHz oscillator) tp1: out STD_LOGIC; --- scope trigger at start of frame spdif_out: out STD_LOGIC); --- s/pdif data stream (to optical tx) end ice40up5k_evn_test; architecture arch_ice40up5k_evn_test of ice40up5k_evn_test is constant sig_resol: POSITIVE := 16; --- signal resolution (bits) constant pha_resol: POSITIVE := 32; --- phase resolution (bits) signal theta: SIGNED(pha_resol-1 downto 0); --- phase accumulator signal theta_left: SIGNED(pha_resol-1 downto 0); --- left phase accumulator signal theta_right: SIGNED(pha_resol-1 downto 0); --- right phase accumulator signal phase_increment_left: SIGNED(pha_resol-1 downto 0); --- left phase increment signal phase_increment_right: SIGNED(pha_resol-1 downto 0); --- right phase increment signal sine: SIGNED(sig_resol-1 downto 0); --- CORDIC generated sine signal cosine: SIGNED(sig_resol-1 downto 0); --- CORDIC generaated cosine signal sample_left: SIGNED(15 downto 0); --- left sample signal sample_right: SIGNED(15 downto 0); --- right sample signal sample_2: SIGNED(15 downto 0); --- right sample signal temp: SIGNED(31 downto 0); --- signal temp2: SIGNED(31 downto 0); --- signal mult_result: SIGNED(31 downto 0); --- signal sample_temp: SIGNED(15 downto 0); --- signal delay_i: STD_LOGIC; --- signal delay_o: STD_LOGIC; --- signal delay_o_1: STD_LOGIC; --- signal delay_o_2: STD_LOGIC; --- signal delay_o_3: STD_LOGIC; --- signal spdif_clk_en: STD_LOGIC; --- signal spdif_sample_en: STD_LOGIC; --- signal sample_en_del1: STD_LOGIC; --- signal sample_en_del2: STD_LOGIC; --- signal prescale_count: UNSIGNED(1 downto 0); --- --- declare the s/pdif output component component spdif_out_component is generic( in_res: POSITIVE); --- audio sample resolution port ( clk_in: in STD_LOGIC; --- clock clk_en: in STD_LOGIC; --- clock enable l_data: in SIGNED(in_res-1 downto 0); --- left audio data in r_data: in SIGNED(in_res-1 downto 0); --- right audio data in next_sample_en: out STD_LOGIC; --- trigger sample update spdif_data_out: out STD_LOGIC); --- output bitstream end component; --- declare the CORDIC component component cordic is generic( input_resol: POSITIVE; --- input resolution output_resol: POSITIVE); --- output resolution port( clk_in: in STD_LOGIC; --- clock in delay_in: in STD_LOGIC; --- delay in delay_out: out STD_LOGIC; --- delay out theta: in SIGNED(pha_resol-1 downto 0); --- phase in sine: out SIGNED(sig_resol-1 downto 0); --- sine out cosine: out SIGNED(sig_resol-1 downto 0)); --- cosine out end component; begin --- main process --- runs two phase accumulators (440Hz envelope and 7kHz carrier) --- CORDIC component calculates sine of each --- first multiplier used to scale envelope (to give lesss than 100% mod), and offset then added so that it's only positive --- second multiplier then multiplies new envelope and carrier to generate amplitude modulation --- result and envelope handed to spdif component for output formatting --- (putting envelope on other channel gives scope something sensible to trigger on) evb_test_stuff: process (clk_12_288) is begin if (clk_12_288'event and clk_12_288 = '1') then --- divide clock by 2 to run SPDIF at 6.144MHz for 48ksps if(spdif_clk_en = '0') then spdif_clk_en sig_resol) --- audio sample resolution port map( clk_in => clk_12_288, clk_en => spdif_clk_en, l_data => sample_left, r_data => sample_right, next_sample_en => spdif_sample_en, spdif_data_out => spdif_out); --- instantiate and connect the CORDIC component cordic_1: component cordic generic map( input_resol => pha_resol, --- input resolution output_resol => sig_resol) --- output resolution port map( clk_in => clk_12_288, --- clock in delay_in => delay_i, --- delay in delay_out => delay_o, --- delay out theta => theta, --- phase in sine => sine, --- sine out cosine => cosine); --- cosine out tp1 <= spdif_sample_en; end arch_ice40up5k_evn_test;</description></item><item><title /><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2-post-21?CommentId=245f7184-8633-4376-8134-10d2c7dd7cc9</link><pubDate>Sun, 19 Apr 2026 13:31:00 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:245f7184-8633-4376-8134-10d2c7dd7cc9</guid><dc:creator>fpgaguru</dc:creator><description>An errata for the stability condition for the second order all pass section with transfer function H(z)=(c2+c1*z^-1+z^-2)/(1+c1*z^-1+c2*z^-2), the two conditions are abs(c2)<1 and abs(c1)<1+c2, not abs(c1)<1 as stated in the post.</description></item><item><title /><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/lattice-ice40up5k-evb-evaluation-board---part-2-using-the-dsp-multiplier?CommentId=b7192c6e-75f1-40c8-9d2e-349b9045fea9</link><pubDate>Mon, 30 Mar 2026 13:02:00 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:b7192c6e-75f1-40c8-9d2e-349b9045fea9</guid><dc:creator>jc2048</dc:creator><description>I'm simply using the multiply operator in VHDL (look for the '*' on line 128), knowing that the synthesis will be sensible and do it by utilising the multiplier in the DSP block. That's inference. I infer in the code that that's what I want it to do and hope the synthesis understands what I want. For something like this it will, provided there are hard multipliers there that can be used, because it's a very obvious thing that people are going to do. I do check afterwards that it has given me what I want. The synthesis has quite lot of clues as to how to go about connecting it because of the nature of VHDL (heavily typed). It knows the wordsize and that the words are signed quantities from the signal declaration. I also help it by picking up the result with a 32-bit signed signal, and only afterwards reducing it to the 16 bits I need for the s/pdif. In terms of using the registers or not, it can decide whether to use them or not based on the code - my code is all step-by-step running on a clock, so there are going to be registers, but not necessarily the ones in the DSP block.</description></item><item><title /><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/lattice-ice40up5k-evb-evaluation-board---part-2-using-the-dsp-multiplier?CommentId=61382acd-2988-46b9-96bb-2898b4403f0b</link><pubDate>Mon, 30 Mar 2026 12:13:00 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:61382acd-2988-46b9-96bb-2898b4403f0b</guid><dc:creator>shabaz</dc:creator><description>Nice work! And that looks like a great dev board for experimenting/learning.</description></item><item><title /><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/lattice-ice40up5k-evb-evaluation-board---part-2-using-the-dsp-multiplier?CommentId=31c397c2-d5bc-4f0b-8953-ea27dcdd8882</link><pubDate>Mon, 30 Mar 2026 11:40:00 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:31c397c2-d5bc-4f0b-8953-ea27dcdd8882</guid><dc:creator>Jan Cumps</dc:creator><description>Where do you define that it uses the DSP IP block? note to self: It's been too long since I last used VHDL, and I'm losing the knowledge fast.</description></item><item><title>File: MVI_4281https://community.element14.com/technologies/fpga-group/m/managed-videos/151085Mon, 30 Mar 2026 11:29:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:3810f1e8-edff-4437-b7a4-231fdd6b797djc2048