https://community.element14.com/technologies/fpga-group/FPGA discusses the latest trends in programmable logic devices, and offers access to education, workshops, webinars on FPGAs, SoCs, and other programmable devices.en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/tang-nano-series-and-gowin-fpgas-for-beginners-part-2-double-blinky-a-vhdl-walk-throughSun, 11 Oct 2026 16:15:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:850d5de0-5e34-46d6-8487-3a8abc2f9a14shabazTable of Contents Introduction Start a Project Library and Package Declarations IO Ports List (Entity and Port Declaration) VHDL Architecture Body Architecture Declaration (Constants and Internal Signals) Architecture Statement Region (Concurrent Statements) VHDL Code Summary Physical Constraints (Pins) Synthesis Assigning Pins Constraints using the FloorPlanner Timing Constraints Place and Route Programming the Bitfile (Bitstream) Instrumenting with GAO: Gowin Analyzer Oscilloscope Summary Click here for Part 1 Introduction The Tang Nano series of boards were introduced in FPGA for Beginners Part 1 , and in particular, it was covered what pins do what, and how the FPGA works at a high level. Now it was time to start coding a simple demo. The demo will just blink a couple of LEDs. I’ll walk through the VHDL code line-by-line, so it’s hopefully clear what is going on. To recap from the previous blog post, ensure you’ve got a good quality USB-A-to-C cable, and register, download and install the Gowin FPGA Designer (also known as Gowin EDA) app; I installed the "Education build". Start a Project For a first experiment with the Tang Nano, launch the Gowin application, and click File->New->Project . A prompt appears for the device; I decided to target the Tang Nano 9k, and selected the GW1NR series (there's a table in the previous blog post listing which FPGA is in which Tang Nano board). You might need to fill in more parameters until all that’s left is one selection that matches your FPGA, then select it. The IDE is easy to use. Notice the left pane has Design , Process and Hierarchy tabs underneath it. In the Design tab, it is possible to right-click and add existing or new files. In the Process tab, you can perform actions to ultimately transform those source files all the way through to the final bitstream/bitfile that needs to be transferred to the FPGA. I right-clicked, and selected New File , selected VHDL , and gave it a name of double_blinky (a .vhd suffix will get appended). Double-click on that file in the Design tab, and the text editor pane will appear on the right. Here is the HDL code I used (I am not a VHDL engineer, so please don’t assume I’m using best practise!). I’ll go through this line-by-line next, but it's best to keep a separate window open with that entire code in view, so it's easier to mentally navigate through it. Library and Package Declarations First off, the following is boilerplate and is generally required for VHDL projects. The 1164 refers to an IEEE standard. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; IO Ports List (Entity and Port Declaration) Like most digital circuits, double_blinky makes use of a clock to progress the circuitry along, and a reset line is very normal too, to make it start in a desired state. Therefore, double_blinky is expected to have four physical connections to the outside world: clock, reset, and two LED signals. The LED signals can be expressed as a two-bit array (called a vector in VHDL). The entity declaration, including its port list, describes these four input or output signals. The reset signal is named reset_n just to make it clear that the signal is expected to go low to perform the reset action. This is commonly called an active-low reset. entity TOP is port ( led : out STD_LOGIC_VECTOR(1 downto 0); clk : in STD_LOGIC; reset_n : in STD_LOGIC ); end TOP; VHDL Architecture Body Here's where the FPGA developer gets to type out how they wish the circuit to function! The architecture has a name, and in this example I've called it RTL . The name can be almost anything you like, but RTL is common. It stands for Register Transfer Level, which basically means describing the circuit in terms of registers and the logic operating between them. This is a very normal way to describe digital circuits intended for implementation in an FPGA. architecture RTL of TOP is The architecture body is split into two sections: the declarative region and the statement region. They will both be described next. Architecture Declaration (Constants and Internal Signals) These are fairly self-explanatory. Since the clock input may be running at a high speed, a counter is needed. The constants here are used to indicate how many clock pulses are needed before the LED state will be changed: -- CONSTANTS constant CLK_FREQ_HZ : integer := 27_000_000; constant MSEC_CONST : integer := CLK_FREQ_HZ / 1000; constant LED_DELAY_CONST : integer := MSEC_CONST * 500; It stands to reason that signals representing the binary count value will be required, and that those signals will probably come from a register, since flip-flops/registers are normally used for anything that needs to remember a state, such as the current counter value. For that reason I called the signal counter_reg , just to make it clear that the value is stored in a register. Although I've declared it as an integer, the synthesis tool will work out how many bits are needed to implement it in hardware. Similarly, an internal signal is needed to hold the LED states, so I called it led_reg . This is a two-bit vector, containing the individual bits led_reg(1) and led_reg(0) . -- INTERNAL SIGNALS signal counter_reg : integer range 0 to LED_DELAY_CONST - 1 := 0; -- LEDs are active-low: '1' = off, '0' = on. -- Start with only the rightmost LED on. signal led_reg : STD_LOGIC_VECTOR(1 downto 0) := "10"; Architecture Statement Region (Concurrent Statements) Here is where all the meat of the project resides. Unlike conventional software code, which executes instructions sequentially, a different way of thinking is needed with HDL. All the main statements underneath the following begin keyword are concurrent, meaning they operate alongside one another rather than executing one after the other. When the design is synthesized, these statements describe hardware that operates in parallel within the FPGA. There are two main elements in this example. begin The first element is a concurrent signal assignment, which effectively describes a permanent connection from the internal LED register outputs to the LED output ports declared at the start of the VHDL. -- Continuously connect the internal LED register outputs to the LED signals led Save , to save the changes to that .rao file ( GAO Config File ). After that, I went into the Process pane, did a clean Synthesize, followed by a clean Place & Route, and then programmed the board as before. GAO did not work for me using SRAM load , so I selected Flash when programming the device. The LEDs blinked as before, i.e. the VHDL code was running fine. To connect to the embedded logic analyzer, I went to Tool->Gowin Analyzer Oscilloscope , and selected the same value channel to connect to as I had used for the programmer, which in my case was numbered 289 . The logic analyzer pane appeared, and there was a blue icon to start a capture, and a ‘continuous capture’ icon next to that. The animated GIF here shows what I saw with the continuous capture. Summary Several of the Tang Nano boards were introduced in the first blog post. This second blog explored the Gowin software which is needed to build projects and transfer them onto the board. For creating projects targeting FPGAs such as those on Tang nano boards, the Gowin FPGA Designer software is quite user-friendly, and straightforward to use. It doesn’t take up much space on the PC either (ballpark 2 GB, which is small in FPGA world! Xilinx software takes up tenfold space). In this blog post, a VHDL project was created from scratch, to make a couple of LEDs perform a double-blinky sequence. The Gowin software was then used to synthesize the design, and graphical tools were used to set the pin and clock constraints, before doing the placement/routing. The programming went fine, but the Tang Nano boards are quirky in that a normal USB-C-to-C cable might not always work, and I don’t think the supplied USB-A-to-C cables are trustworthy either. Best to use your own known working USB-A-to-C cable. Finally, the ability to debug hardware in action, using the Gowin Analyzer Oscilloscope (GAO), was briefly explored. Thanks for reading!GW1NRtang nanofpgagowinGW2ARGW1NZGAOfpga basicshttps://community.element14.com/technologies/fpga-group/b/blog/posts/tang-nano-9k-using-internal-psram-in-gowin-fpgasThu, 08 Oct 2026 20:58:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:777db40d-df82-4686-8796-456a9951fa69shabazTable of Contents Introduction PSRAM Overview Adding Gowin IP VHDL Walk-Through Entity: Ports to the Outside World PLL Component PSRAM Component Process: Asynchronous Reset Function Process: Registered Portion Read Operation Underway Calibration and PSRAM Write PSRAM Read during the Verification Phase PSRAM Read: Playback Building It Does it Work? Summary Introduction Some Gowin FPGA parts contain not only the FPGA itself, but inside the package the manufacturer has fitted a PSRAM chip too! That’s really convenient if you need more RAM space than block RAM may ordinarily provide, but don’t want the overhead of designing in another chip onto the circuit board. PSRAM is easier to use than SDRAM, but that can be simplified further by making use of Gowin’s ready-made “API” or library, better known in FPGA-world as IP. This blog post walks through an example project that makes use of the PSRAM, not for any real purpose, but it exercises it by first writing data and filling up the entire PSRAM, and then checking the PSRAM contains what is expected, and then finally playing out each bit sequentially, using a couple of outputs on the FPGA, all ready to be observed with an oscilloscope. I used a Tang Nano 9k board, which contains the Gowin LittleBee series GW1NR part (the full part code is GW1NR-LV9QN88PC6/I5). If you're new to Tang Nano boards, this blog post provides an introduction: (+) Tang Nano Series and Gowin FPGAs for Beginners: A Practical Guide, Part 1 - element14 Community Disclaimer: I used AI significantly to help me with the HDL code. This article however was written by myself, and I checked the VHDL code pretty much line-by-line to ensure it does what I expected it to do. PSRAM Overview PSRAM is cheaper than SRAM, because it doesn’t dedicate as many transistors per memory cell, and easier to use than SDRAM, because the refresh circuitry is on-chip. The PSRAM inside the GW1NR part has 64 Mbits of space, and those bits can be organized in a number of ways; In the screenshot further below it can be seen that I configured two channels of 32 Mbits each. The data bus is 32-bit wide (let’s call it a 32-bit “word”) and I chose to read/write in blocks of 8 words (this can be considered a “burst” of 32 bytes, but it’s easier for the rest of the blog post to express it as 8 words). Since 8 words will be read or written, this means 8 clock pulses will be used to transfer the data in or out (plus however many pulses are needed beforehand to send the read or write command, and delay until the data is available). The PSRAM requires a clock to operate, and it needs to be between 50 and 160 MHz. I went with 81 MHz, which isn’t completely arbitrary, because 81 MHz happens to be three times 27 MHz, which is the frequency of the crystal on the Tang Nano 9k board. An integer multiple like 3 is an easy thing for a phase-locked-loop (PLL) to achieve. Using the PLL entails using PLL IP incidentally, so now that’s two sets of IP that need to be included in the project, not a problem of course, that’s what the manufacturer’s IP library is there for. Adding Gowin IP After you’ve clicked on File->New and created a new project, you might create a first VHDL file called (say) top.vhd (this is assuming the VHDL language is being used for this project). Next, click on Tools->IP Core Generator , and then navigate to the PSRAM Memory Interface HS selection as shown here and double-click to launch it. Incidentally, if you want to ever review the configuration at a later date, go to Tools->IP Core Generator again, but this time look for a little folder icon above the IP list (the icon is shown boxed in orange in the screenshot above) and then navigate to a file with suffix .ipc which will contain your IP settings. The screenshot shows the adjustments I made, and then I clicked on the Options tab. Within the Options tab, I set the Burst Mode to 32 bytes (i.e. 8 words). When you click OK, a few things happen. Firstly, the IP is generated and your project folder will now contain a src/psram_memory_interface_hs folder (or similar), and secondly the generator will dump some temporary content into the code pane. That temporary code contains a component definition and instantiation, both of which need to be copy-pasted into your main VHDL code somewhere. You can see where it needs to go by looking at my example top.vhd source file in the Github repo. Adding the PLL IP is just as easy: As before, a temporary file will appear and the VHDL there can be copy-pasted into your code. VHDL Walk-Through The VHDL code (the word code is being used colloquially, the term HDL source is often used) is far easier to understand by looking at a block diagram, split up to follow it better. The project implements within the FPGA three main phases of operations: (1) Fill the entire PSRAM memory with a test pattern (the second channel uses an inverted version of the test pattern) (2) Read the entire PSRAM contents, comparing each word with the test pattern (3) Repeatedly read the entire PSRAM contents, outputting each bit serially onto a pin to observe with an oscilloscope; this is done for both channels, so a 2-channel ‘scope should show one signal inverted compared to the other. The full block diagram is viewable here (open it in a separate window, and then you can pinch-to-zoom or whatever, while following the explanation in the rest of this blog post), and click here to see the top.vhd code . Entity: Ports to the Outside World The salmon-colored part, the entity called TOP , defines the external-facing ports for the hardware, in other words, the names of the signals that will make their way out to physical wires on the FPGA. You can see on the right side that led[1..0] refers to an array of two signals, so those obviously will be attached to two LEDs (these happen to be already soldered on the Tang Nano 9k board). The out_ch1 and out_ch2 will go to pins that can attach to an oscilloscope to see the bit pattern that is played out from the PSRAM. All the ports labelled O_psram or IO_psram are actually not connected to physical pins on the Gowin part, but rather are connections from the FPGA chip inside, wired to the PSRAM chip next to it inside the package. PLL Component The two blue-colored items are known as components in VHDL, and one is the PLL, and the other is the PSRAM component. The PLL one is very simple externally, all it needs is a clock input (shown on the left side; I’m using the convention that all left side signals are inputs, and the right side signals are outputs). The PLL will multiply that clock input by three (provided it is configured for that in the IP configuration window, which I’ll get to). There is a PLL lock output, which is pretty important because it’s not a good idea to attempt memory writes with unstable clocking. PSRAM Component The PSRAM component looks complex, but (a) no code needed to be typed to create that component instance, since that was auto-generated as part of using that IP, and (b) if you look closely, a lot of the signals are doubled-up simply because the memory is being used in two channels. All the signals are simple enough to follow. You can see from the diagram that the 81 MHz clock output from the PLL is wired to the memory_clk input to the PSRAM component. Many of the other signals are self-explanatory, for instance, you can see from the thick pink/magenta lines that there are two 21-bit address buses called addr0[20..0] and addr1[20..0] , for the two channels. The VHDL code happens to connect them together, i.e. I intend to treat these two channels in a similar way (an example would be for left and right audio data) so I can access memory locations across the two channels in parallel. The 32-bit data buses are shown with thick orange and light-blue connections attached. The orange ones are inputs to the PSRAM component for writing data, and the light-blue ones are outputs. The init_calib0/1 signals go high when the PSRAM has initialized, and so the VHDL code will need to wait for that (and wait for the PLL lock) before performing read/write operations. Also, the PSRAM component provides a clock output that is a divided-by-two version of its input clock, therefore it will be 40.5 MHz in my case. That clock is expected to be used as the clock for the rest of the user VHDL code (at least, that is what Gowin intends the user to do according to their documentation, so that’s what I did). The remaining input signals cmd0 , cmd1 , cmd_en0 , cmd_en1 are 1-bit signals that are used to control whether the memory is being read or written. The cmd0/1 signal needs to be high to perform writes, and low to read. The cmd_en0/1 signal needs to go high (i.e. asserted) for one clock cycle, to instruct the PSRAM component to accept the command. I've now covered a fair portion of the project, and really very little VHDL needed to be written to achieve that, since those particular component declarations were created by the Gowin IP generator feature. It’s time to look at another part of the VHDL code. Process: Asynchronous Reset A VHDL process is a way of grouping up things that run sequentially. You can have many processes, they all operate concurrently with each other, but sequentially internally. The great thing about processes is that they allow the developer to implement registers that can store results, i.e. retain state, from one clock cycle, to be used in the next. This is super-important because without a clock, there could be glitches and you wouldn’t know precisely when results are valid, due to small delays in signals arriving at different inputs of logic gates. With clocked logic such delays do not matter, since there is time for logic outputs to settle, provided that happens faster than the controlled clock speed. Registers are automatically inferred into a design, whenever the developer uses a pattern in their VHDL code that looks like this: process(clk_out, reset_n) begin if reset_n = '0' then -- reset code sits here cmd0 ‘0’); is a way of setting a signal array all to zero but there are other ways too; you could write databyte Create Clock . Give it any name, and then importantly change the Collection to pins as shown in the screenshot below, and then you'll be able to search for that clock name (capitalization is important) as shown here. After it is added and you click OK, set the frequency to 40.5 MHz for that constraint. Does it Work? Yes : ) After building it (i.e. in the Process pane, double-click on the Synthesis tab, and then double-click on Place&Route , and hope they both change to green-circled check-marks) the Gowin Programmer was used to transfer it into the Tang Nano 9k. If you’ve not used the Programmer before, be aware that the Tang Nano boards seem to require a USB-A-to-C cable (despite USB-C-to-C appearing to initially work), the supplied cable may be faulty (mine was), and when launched, the Programmer chooses one of two communication channels; I had to swap to the second channel for successful programming). Anyway, once it was programmed, all LEDs were off, which at least meant there was a chance the code was successfully running! I attached the oscilloscope probes (not very well) and you can see the two outputs are complementary and at the expected data rate. I didn’t try to capture with a logic analyzer and decode it back to the original data. Summary Some of the Gowin parts feature built-in PSRAM. The Tang Nano uses a GW1NR device with 64 Mbits of PSRAM, and it is quite easy to use by adding Gowin IP to the project. PLL IP was also used, to multiply the crystal clock source to a usable frequency. The PSRAM was configured to operate with 32-bit wide data buses, in two 32 Mbit channels. The VHDL code implemented a state machine that waited for the PSRAM to be ready/calibrated, and then the entire two channels were filled with test pattern data, in bursts of 8 words. The state then transitioned to allow reading of the memory to confirm it was correctly filled, and then the memory could be repeatedly read out at a slower rate for serializing the data out of a couple of FPGA pins. Obviously, this project on its own doesn’t serve a useful purpose, but hopefully with the VHDL description and diagrams, it is now easier to use the PSRAM in other projects. Thanks for reading!ramPSRAMGW1NRtang nanofpgagowinfpga basics