https://community.element14.com/technologies/fpga-group/FPGA discusses the latest trends in programmable logic devices, and offers access to education, workshops, webinars on FPGAs, SoCs, and other programmable devices.en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/hardware-accelerator-for-hyperspectral-image-processingTue, 14 Jul 2026 07:12:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:098d4647-1d97-4032-a5a7-20edd71cfbcbafernandezHi, community! I’m writing this post because I’d like to share one of the projects I have been working on, a hardware accelerator written in SystemVerilog for processing hyperspectral image vectors. First of all, I want to give some context about this project. Unlike a normal RGB image, a hyperspectral image can contain tens or even hundreds of spectral bands for each pixel. This makes this technology very useful for agriculture, environmental monitoring, remote sensing or material identification, but it also generates a large amount of data that must be processed. For this reason, I wanted to explore how some vector operations could be moved from software to dedicated hardware, reducing the workload of the main processor. The accelerator The current version supports two operations: Dot product Cross product The design uses two input FIFOs and one output FIFO. Internally, a finite-state machine controls the complete process, from reading the vectors to calculating and storing the result. I also developed a wrapper with an OBI-compatible register interface, allowing the processor to configure the operation, select the number of bands, start the accelerator and read its busy, done and error status. The accelerator was integrated into the X-HEEP ecosystem, using a RISC-V processor for control and a DMA controller to transfer the input and output data without requiring continuous CPU intervention. Verification For verification, I used Verilator together with C++ testbenches. I created individual tests for: The FIFO memories The vector processing core The OBI wrapper The complete integrated accelerator The testbenches verify normal operations, invalid configurations, empty and full FIFO conditions, signed calculations and register access. The simulations achieved more than 90% coverage over the instrumented lines and signals. I also generated VCD files to inspect the internal behaviour using GTKWave. Results The functional tests confirmed that the accelerator correctly performs the dot and cross products and responds correctly to invalid operations and boundary conditions. For the cross product, the latency per pixel becomes stable once the finite-state machine has started processing data. For the dot product, the latency increases linearly with the number of spectral bands because the multiply-accumulate operations are performed sequentially. The tests also showed something very important: the vector core itself was not the main bottleneck in the evaluated workloads. The largest limitation came from moving data between memory and the accelerator. The DMA introduces a fixed startup delay for every transfer. Because each operation requires two input transfers and one output transfer, this overhead has a significant impact when processing only a small number of vectors. As a result, the software version can still be competitive for small datasets. The hardware accelerator becomes more useful with medium or large datasets, when the initial DMA cost can be distributed across more operations. The measurements up to 4000000 vectors also showed a mostly linear behaviour, without clear memory saturation or cache-related steps in the evaluated range. Image above shows the latency vs the compute data size for the vectorial product operations. Conclusions The main conclusion from this project is that developing the arithmetic unit is only one part of hardware acceleration. The complete system performance also depends heavily on the memory architecture, bus bandwidth and data-transfer strategy. The accelerator demonstrated that a custom SystemVerilog block can be successfully integrated into an open RISC-V platform and operate autonomously through an OBI interface and DMA transfers. However, using dedicated hardware does not automatically make every workload faster. For small datasets, the communication overhead can cancel out the benefit of the accelerator. For larger workloads, the hardware solution becomes more interesting because the fixed transfer cost is amortised and the CPU is released to perform other tasks. In future versions, I would like to explore double buffering and overlapping DMA transfers with computation. I also want to support larger spectral vectors, improve the internal accumulator and finally synthesise the design on an FPGA to analyse resource usage, maximum frequency and power consumption. One of the biggest lessons I learned is that a good accelerator must not only calculate quickly: it must also receive and return data efficiently. I’m very happy with the results so far, and I would love to hear your feedback and suggestions! If any person want to get mor info about this project I can share the github link.fpga_projectsfpgavhdlfpga-projectdspsystemverilogveriloghardware_acceleratorshttps://community.element14.com/technologies/fpga-group/f/forum/25947/barriers-to-designing-with-fpgas/236239Fri, 26 Jun 2026 08:57:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7fb1b810-129b-49de-bb49-b02570b56cb6ShishirReading all these comments, experienced developers sharing their experiences and views, looks like having found a lost treasure. Great knowledge.https://community.element14.com/technologies/fpga-group/w/setup/26642/featured-content-triptych-setup-docThu, 28 May 2026 12:55:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7e3dbc4b-ad3d-4d73-aeac-6597508eadc2e14sbhargavPath to Programmable III Collaborated with Path III is the third session in the element14 Community’s structured FPGA-based SoC training. The first Path was held in 2018 and focused on programmable logic devices PLDs and featured the AVNET MiniZed development board, based on AMD’s Zynq-7000 SoC. Path II convened in 2019 and offered more advanced learning opportunities and featured the AVNET Ultra96-V2 development board, based on AMD’s Zynq UltraScale+ MPSoC. Path III will double the fun by offering structured training on both the MiniZed and Ultra96-V2 boards. Each training track will be followed by a design/build phase. Learn More Achieving Deterministic Latency with the AMD Kria ™ ︎ K24 SOM Adaptive Computing The Bulls Eye® High Performance Test System Samtec Flyover® Technology for FPGA Apps Memory Storage for FPGA Applications Accelerating Embedded Vision with the CrossLink ™ -NX FPGA On Demand Webinars: Getting Started with the AMD Spartan ™ ︎ UltraScale+ ™ ︎ FPGA SCU35 Eval Kit PYNQ-Z2 Workshop Series: FPGA Experiments With Xilinx Pynq-Z2 Power Integrity Effects on FPGA Functionality and Performance Leveling-Up Your FPGA Skills: An Expert Panel Discussion Getting Started with FPGAs: An Expert Panel Discussion Summer of FPGA: Software and FPGA: How to Get the Bits to Flip? Intro to Smart Embedded Vision (SEV) Using a PolarFire ® FPGA Building Processor Based Systems on Lattice FPGAs Using Propelhttps://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235724Thu, 21 May 2026 13:46:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:1cef9723-cb6b-41e0-bf69-d4cbf4ddaec3wolfgangfriedrich[quote userid="36226" url="~/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235702"]Now I'm slightly less envious of the four people who won those nice Xilinx boards recently.[/quote] The option is to use 2025.2.1 and not upgrade any further.https://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235722Thu, 21 May 2026 13:03:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:0aa099f7-10a3-4df9-95da-d35d089ef3cfkk99Maybe hobbyists that do not want to use VM or switch environments will start with other alternatives, like Gowin.https://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235717Thu, 21 May 2026 12:38:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:32d1609e-0dff-4af5-a111-0275cc766308bradfordmillerParticularly if you are using PetaLinux or the new EDF. Maybe paying for EDF (too bad "classic" MicroBlaze users) is why they're pushing the paid CORE package? At least 2025.2 and before are still available free (for the smaller chips anyway)! I wouldn't mind paying for CORE so much if it was something I could do every 3 years which is about how I use the current upgrade cycle (i'm still on 2023.1). But for that "privilege" I'd have to spring for ENTERPRISE...https://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235702Thu, 21 May 2026 08:05:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:137f8965-a423-4e27-9724-8c97a405cce2jc2048Now I'm slightly less envious of the four people who won those nice Xilinx boards recently. "Are there alternatives?" Lattice, Microchip, et al. I've got the no-cost editions of Diamond (Lattice) and Radiant (Lattice) running happily on Xubuntu 22.04. Libero (Microchip) installed ok, but I haven't done the licence serving part yet, so can't say for sure it runs happily. I think the basic level of Altera's Quartus (Lite edition) is available for Linux, but the 3rd party simulator is not for 22.04 (you'd need Red Hat, or one of its derivatives). I might give it a try as I've got the Vidor 4000 board and at some point my old Windows 8.1 laptop will probably die.https://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier/235695Wed, 20 May 2026 22:25:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:e560dd00-0353-4dd0-a12d-b0133a23b4bddyessggAny word as to why Linux support is excluded from the Basic tier? I would think Linux would be the primary platform people use these tools on.https://community.element14.com/technologies/fpga-group/f/forum/56972/amd-changes-vivado-license---locks-out-linux-support-from-basic-tier-edit-maybe-notWed, 20 May 2026 22:11:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8e4fe275-4a78-4bb2-9c72-c65999a11d1estantoWhat was arguably an avenue into free development, being able to use Linux and then Vivado, is now locked down into buying a supported Windows license to use free Vivado. If you want Linux support you now have to pay for it. $1,200+. Existing installations will likely still work. https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado/vivado-licensing-options.html Are there alternatives? Maybe it works with Wine? Edit: 1st June 2026 Looks like they changed their minds! https://www.linkedin.com/posts/vivado-licensing-options-share-7466166724040564736-4D76/ https://adaptivesupport.amd.com/s/article/Adding-LINUX-support-back-for-the-BASIC-free-version-of-Vivado?language=en_USlinux supportlicensevivadoamdhttps://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpga/235382Wed, 06 May 2026 08:35:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:0ec8336b-4a9d-46be-9590-4b781d57e1a7michaelkellettHello Daniel, I see that you are a new member at E14. You posted this question in two E14 groups which is not a good thing to do because it splits the thread so people do not see each others' answers. On E14 you will almost always get a better result by posting once in about the right place My answer to your question is in the other group ! MKhttps://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpga/235369Tue, 05 May 2026 17:34:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b882eff2-6bfe-4710-b8c7-f2b4ab91ef18fpgaguruRetired engineer with 35 years of FPGA design experience here, 24 of them at Xilinx/AMD. Tooting my own horn, you may want to take a look at the Element14 blog "The Art of FPGA Design" , quite old now but still very relevant. In particular Post 3 has a link to the book I used to learn VHDL in 1995, Peter Ashenden's "The VHDL Cookbook" What I really want to point out is that "learning FPGA", or "learning VHDL" or Verilog or whatever should not be a goal in itself, it's like saying "I need to learn to use a hammer", what you should aim for is "I want to learn how to build a house". What you really want is to learn digital hardware design, especially if you come from a software engineering background. VHDL is just another programming language and FPGA design is the ability to use a tool like Vivado or Vitis, how to use these tools and skills is the actual challenge.https://community.element14.com/technologies/fpga-group/m/managed-videos/151290Mon, 04 May 2026 22:48:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:9ca51cc4-3fc4-4920-81d4-131561d48d4esaramicBuy the Book: https://nandland.com/book-getting-started-with-fpga/ Buy the Go Board: https://nandland.com/the-go-board/ After 2 years my book Getting Started with FPGAs is now available for order! This is by far the most comprehensive and best con...https://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpga/235335Mon, 04 May 2026 22:47:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b729cb0c-126e-4b3d-8313-c9e018f33f98saramicI have no expertise in this area, but from my research I am planning (in some future) to follow this path: I have this book Getting Started with FPGAs Digital Circuit Design, Verilog, and VHDL for Beginners by Russell Merrick September 2023, 320 pp. ISBN-13: 9781718502949 The author recommends his board for getting started The Go Board -> https://nandland.com/the-go-board/ ~$70 The Best FPGA Development Board For Beginners Quick overview by the author My book Getting Started with FPGAs is NOW AVAILABLE! - nandland https://youtu.be/4UpMB9kNt0s the code https://github.com/nandland/getting-started-with-fpgas As I mentioned - I have 0 experience but this looks like the learning path I would take to get a good understanding - hope that helpshttps://community.element14.com/technologies/fpga-group/f/forum/56910/learning-fpgaMon, 04 May 2026 18:33:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8c12b4b4-1164-425d-93a2-f6d2eb05bbeddanielpgleasonDoes anyone know of any good learning resources about how to start learning FPGA? I've been a software engineer for several years and the FPGA world is quite new to me. I'm trying to implement RMII but have been struggling a lot. I purchased a logic analyzer but I don't know what I'm looking at. I need something that will tell me how to properly understand and read datasheets, know how to debug signals, how to understand what VHDL is good and what is bad. How to read RTL generations..Etc I'm starting from the beginning. Any resources or materials are greatly appreciated.