• Not-as-expensive FPGA Boards

    I haven't done a poll in a while so I thought it would be fun and instructive to do one about less-expensive FPGA boards.  One of the challenges of getting into FPGA design is that the boards are usually a lot more expensive than a Raspberry Pi or…

  • How to change FPGA timing with Excel file?

    Hi,

    I heard that the timing of FPGA signals can be changed via a MS Office Excel file.

    The timing of the signals could be designed in an Excel file and then, maybe after conversion, uploaded via RS232 or SPI to the FPGA.

    In this way the timing could be changed…

  • Difficulties with interfacing external devices using Altera FPGAs

    How can I interface external analog signals (from a potentiometer for example) and display the bits on the user LEDs? Is it also possible to apply fourier transform on these analog signals? I have both Cyclone 10 LP evaluation kit and the DE 10 Nano standard…

  • Altera FPGA & CPLD Power Management Solutions

    Altera FPGA & CPLD Power Management Solutions

    Texas Instruments works closely with AlteraRegistered to recommend the best power  solutions for a wide variety of end-equipment applications. TI's diverse power  management portfolio adequately supports the power…

  • PDF

    Lancero SGDMA PCI Express IP core with Windows, Linux and QNX device drivers

    Lancero SGDMA PCI Express IP core with Windows, Linux, QNX drivers.

  • PDF

    USB BitJet Lite (Download cable for Altera devices)

    Faster  download with  quick configuration of Altera devices will shorten your  design cycle and  allow you to deliver the products in the market at  desired time.   SLS  BitJet Lite will make this possible.  Visit http://www.slscorp.com/pages/usbbitjet_lite.…

  • PDF

    USB 3.0 Development Board with Cyclone IV FPGA

    SLS recently launched USB 3.0 Development board with Cyclone IV FPGA.  Additional peripherals included make the board much more suitable for this age product prototyping.  Peripherals include: DDR2 SDRAM, NAND Flash, CFI FLASH, SDRAM, SD Host and many more…

  • Cheap Entry into FPGA

    There's been quite  a lot of talk in the FPGA group about cheap ways to get started so a couple of weeks ago I decided to forsake the professional setup I use for real work and try one of the cheapest routes I could find. The idea was to try something…

  • FPGA Modular Firmware Skeleton for multiple instruments - Morph-IC-II, YouTube videos.

    I have developed the following design as the framework for the bus interface of USB2 interfaced FPGA based instruments.

     

    This firmware in intended to aid the design of instrumentation using the Morph-IC-II module and other fpga systems interfaced to the…

  • FPGA Dev Kits

    So if you have been following my series of post on what a FPGA is and which is better VHDL or Verilog then you should by now be thinking about the next step - actually buying a development kit. In this post I will talk about the three kits I think you…

  • Multiplication on FPGA

    FPGA gets its power from the flexibility. The design process can be time-consuming but you can design basically anything. In this project, I will give some examples of the multiplication and flexibility of FPGAs.

     

    Multiplication consumes time and sometimes…

  • Introduction to FPGA with Unboxing DE0-NANO P0082

    I have been chosen as a roadtester for DEO-NANO P0082 and my kit has arrived. I decided before going roadtest project, it will be nice to give a heartbeat and step into FPGA world. Before you go reading, I want to say I am not an FPGA expert but I want…

  • Review of the new Terasic flagship: DE10-Standard FPGA-SoC Developing Board

    Hello.

    I had a great opportunity to test and to review the Terasic new flagship, the DE10-Standard FPGA-SoC board.

    We will take a look at what this product has to offer, what is its target group and if it is worth its money.

    …

  • Trigger pulse generation inside FPGA

    Hello, i am facing small problem with FPGA programming.

     

    Problem is simple, i have unknown length trigger pulse (1ns-5us) that should start CCD readout. What i need is to be able to make that signal as short as possible, so i don't waste clock cycles to…

  • Interfacing a circuit in an FPGA to a PC.

    If you have an interest in exchanging data between circuitry in an FPGA and a PC, I have written a simple GUI that demonstrates transfers at full USB2 rates to and from an FPGA interfaced with an FTDI FT2232H USB2 interface chip (i.e. the  FTDI Morph-IC…

  • Altera selects two-pronged process technology strategy for 28nm FPGAs

    In addition to its previously announced support for TSMC's 28nm High Performance (28HP) process technology for high-end FPGA products, Altera plans to use TSMC's 28nm Low Power (28LP) process technology for use in its low cost and mid-range families.…

  • Altera Unveils FPGA Design Flow that will Support Embedded Processors Based on ARM, Intel and MIPS Architectures

    With its new Embedded initiative announced yesterday Altera is providing designers a single FPGA design flow based on its Quartus II development software—including the new Qsys system-level integration tool-- a common FPGA intellectual property (IP) library…

  • Altera Launches Stratix V 28nm FPGA

    Altera this morning announced Stratix V, their first 28nm FPGA. The new FPGA family provides up to 1.1 million logic elements, 53-Mbits embedded memory, 3,680 18x18 multipliers and integrated transceivers. The full press release can be found in the documents…

  • ARM DesignStart soft core

    I'm still a complete noob with FPGAs, but as part of my digging around I came across ARM's new DesignStart program. It appears to be a royalty free ARM M0 or M3 core for Altera and Xilinx FPGAs. I thought it might interest a few people here.

     

    https…