https://community.element14.com/technologies/fpga-group/w/documents/5399/summer-of-fpgas-2-minute-fpgas-with-whitney-knitteren-USTelligent Community 12https://community.element14.com/technologies/fpga-group/w/documents/5399/summer-of-fpgas-2-minute-fpgas-with-whitney-knitterTue, 21 Sep 2021 14:48:55 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:fb6f11c8-99d3-436a-85f9-a8eb25286ed5tariq.ahmadhttps://community.element14.com/technologies/fpga-group/w/documents/5399/summer-of-fpgas-2-minute-fpgas-with-whitney-knitter#commentsCurrent Revision posted to Documents by tariq.ahmad on 9/21/2021 2:48:55 PM<br /> <p style="margin:0;"><a href="/technologies/fpga-group/"><img alt="image" src="/e14/assets/legacy/2021/SummerofFPGA_profile.png" style="float:left;width:80px;padding-right:8px;padding-bottom:8px;" /></a></p><p style="margin:0;font-size:18px;font-weight:bold;padding-bottom:4px;"><a class="jivecontainerTT-hover-container jive-link-socialgroup-small" href="/technologies/fpga-group/">Summer of FPGAs</a><a name="top"></a></p><p style="margin:0;"><a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda">Main Agenda</a> | <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda#essentials">Essentials</a> | <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda#quiz">Quiz</a> | <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda#roadtest">RoadTests</a> | <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda#techspotlight">Tech Spotlights</a> | <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda#webinars">Webinars</a> | <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda#other">Other Related Programs</a></p><hr style="clear:both;margin-top:12px;border-top:1px solid rgba(0, 0, 0, 0.2);border-bottom:0px solid rgba(255, 255, 255, 0.1);" /><p style="margin:0;padding:0px;">&nbsp;</p><p style="margin:0;"><strong>Get a bite sized introduction to FPGAs.</strong></p><p style="margin:0;padding-top:4px;">Learn about FPGAs in 2 minutes with Whitney Knitter.</p><p style="margin:0;padding:0px;">&nbsp;</p><table border="0px" class="jiveBorder" style="border:0px solid #ffffff;width:100%;"><thead><tr><th colspan="2" style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;color:#ffffff;background-color:#eb7a3d;text-align:left;" valign="middle"><strong>Blocking vs Nonblocking Statements in Verilog</strong></th></tr></thead><tbody><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"><a href="/technologies/fpga-group/w/documents/5396/2-minute-fpgas-blocking-vs-nonblocking-statements-in-verilog"><span><a href="https://community.element14.com/resized-image/__size/402x226/__key/communityserver-wikis-components-files/00-00-00-00-32/5025.contentimage_5F00_213249.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/00/32/5025.contentimage_213249.jpg-402x226.jpg?sv=2016-05-31&amp;sr=b&amp;sig=xkKBaZsBWb6jA5zEyi9n9xlMs7fxw4j6DbBrK2JtrIs%3D&amp;se=2026-09-16T23%3A59%3A59Z&amp;sp=r&amp;_=UmscTGOzGx1MnPMbA6v2KQ==" style="max-height: 226px;max-width: 402px;" /></a></span></a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;">Video:&nbsp; <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5396/2-minute-fpgas-blocking-vs-nonblocking-statements-in-verilog">2-Minute FPGAs: Blocking vs Nonblocking Statements in Verilog</a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;">Blog:&nbsp; <a class="jive-link-blog-small" href="/technologies/fpga-group/b/blog/posts/getting-started-with-the-tinyfpga-lattice-diamond-3-12-on-ubuntu-18-04">Getting Started with the TinyFPGA &amp; Lattice Diamond 3.12 on Ubuntu 18.04</a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr></tbody></table><p style="margin:0;padding:0px;">&nbsp;</p><p style="margin:0;padding:0px;">&nbsp;</p><table border="0px" class="jiveBorder" style="border:0px solid #ffffff;width:100%;"><thead><tr><th colspan="2" style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;color:#ffffff;background-color:#eb7a3d;text-align:left;" valign="middle"><strong>Logical vs Bitwise Operations in RTL</strong></th></tr></thead><tbody><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"><a href="/technologies/fpga-group/w/documents/5413/2-minute-fpgas-logical-vs-bitwise-operations-in-rtl"><span><a href="https://community.element14.com/resized-image/__size/393x221/__key/communityserver-wikis-components-files/00-00-00-00-32/0257.contentimage_5F00_213250.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/00/32/0257.contentimage_213250.jpg-393x221.jpg?sv=2016-05-31&amp;sr=b&amp;sig=0rpW%2B%2BZVEDaFRluMXon4GZuJty9jRnIlACU1CHo%2FxI0%3D&amp;se=2026-09-16T23%3A59%3A59Z&amp;sp=r&amp;_=7vogUkPVZ2Wdgc4V2dT3+A==" style="max-height: 221px;max-width: 393px;" /></a></span></a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;">Video:&nbsp; <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5413/2-minute-fpgas-logical-vs-bitwise-operations-in-rtl">2-Minute FPGAs: Logical vs Bitwise Operations in RTL</a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr></tbody></table><p style="margin:0;padding:0px;">&nbsp;</p><p style="margin:0;padding:0px;">&nbsp;</p><table border="0px" class="jiveBorder" style="border:0px solid #ffffff;width:100%;"><thead><tr><th colspan="2" style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;color:#ffffff;background-color:#eb7a3d;text-align:left;" valign="middle"><strong>Synchronous vs Asynchronous Flip Flops</strong></th></tr></thead><tbody><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"><span><a href="https://community.element14.com/resized-image/__size/395x222/__key/communityserver-wikis-components-files/00-00-00-00-32/6114.contentimage_5F00_213251.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/00/32/6114.contentimage_213251.jpg-395x222.jpg?sv=2016-05-31&amp;sr=b&amp;sig=sBW5nk6ObCpG7tUdNVFV3H%2BSIHQY8m0jEmjY%2BPI5xhY%3D&amp;se=2026-09-16T23%3A59%3A59Z&amp;sp=r&amp;_=uUaPFW0TOIc87nn0FOOZSg==" style="max-height: 222px;max-width: 395px;" /></a></span></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;">Video:&nbsp; <a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5414/2-minute-fpgas-synchronous-vs-asynchronous-flip-flops">2-Minute FPGAs: Synchronous vs Asynchronous Flip Flops</a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr></tbody></table><p style="margin:0;padding:0px;">&nbsp;</p><p style="margin:0;padding:0px;">&nbsp;</p><table border="0px" class="jiveBorder" style="border:0px solid #ffffff;width:100%;"><thead><tr><th colspan="2" style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;color:#ffffff;background-color:#eb7a3d;text-align:left;" valign="middle"><strong>Verilog Code for Basic Logic Gates</strong></th></tr></thead><tbody><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"><span><a href="https://community.element14.com/resized-image/__size/397x223/__key/communityserver-wikis-components-files/00-00-00-00-32/4061.contentimage_5F00_213252.png"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/00/32/4061.contentimage_213252.png-397x223.png?sv=2016-05-31&amp;sr=b&amp;sig=yDc3n3SuuuWiMzaarW30AhYMEyyHGSC%2BNBCqBHTZDmA%3D&amp;se=2026-09-16T23%3A59%3A59Z&amp;sp=r&amp;_=OJjs57Rsx1xlhYr0+W/6qQ==" style="max-height: 223px;max-width: 397px;" /></a></span></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;">Video:&nbsp; <a class="jive-link-wiki-small" href="/challenges-projects/element14-presents/secret-element14-presents/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates">Verilog Code for Basic Logic Gates</a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr></tbody></table><p style="margin:0;padding:0px;">&nbsp;</p><p style="margin:0;padding:0px;">&nbsp;</p><table border="0px" class="jiveBorder" style="border:0px solid #ffffff;width:100%;"><thead><tr><th colspan="2" style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;color:#ffffff;background-color:#eb7a3d;text-align:left;" valign="middle"><strong>Clock Divider Circuits &amp; Their Timing Constraints</strong></th></tr></thead><tbody><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"><span><a href="https://community.element14.com/resized-image/__size/407x229/__key/communityserver-wikis-components-files/00-00-00-00-32/7288.contentimage_5F00_213253.png"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/00/32/7288.contentimage_213253.png-407x229.png?sv=2016-05-31&amp;sr=b&amp;sig=vZFph7Dj%2BRF6LXLUDb8aYv7fR0Arv1Fn33%2Bqpe0wsXo%3D&amp;se=2026-09-16T23%3A59%3A59Z&amp;sp=r&amp;_=Hu4tZ2j3IzRD/q3uBU2gqQ==" style="max-height: 229px;max-width: 407px;" /></a></span></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr><tr><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;">Video:&nbsp; <a class="jive-link-wiki-small" href="/challenges-projects/element14-presents/secret-element14-presents/w/documents/5416/2-minute-fpgas-clock-divider-circuits-their-timing-constraints">2-Minute FPGAs: Clock Divider Circuits &amp; Their Timing Constraints</a></td><td style="border:0pxpx solid black;border:0px solid #ffffff;padding:6px;"></td></tr></tbody></table><div style="clear:both;"></div> <div style="font-size: 90%;">Tags: 2-minute_fpgas, whitney_knitter</div>