<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/"><channel><title>2-Minute FPGAs: Verilog Code for Basic Logic Gates</title><link>https://community.element14.com/technologies/fpga-group/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>2-Minute FPGAs: Verilog Code for Basic Logic Gates</title><link>https://community.element14.com/technologies/fpga-group/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates</link><pubDate>Tue, 23 Nov 2021 16:56:02 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:9ba546dd-4550-4aa6-aac5-6364580665b3</guid><dc:creator>pchan</dc:creator><comments>https://community.element14.com/technologies/fpga-group/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates#comments</comments><description>Current Revision posted to Documents by pchan on 11/23/2021 4:56:02 PM&lt;br /&gt;
&lt;div style="background:#ffffff;border:1px solid #dadada;margin:0;padding:14px 16px 16px 18px;vertical-align:top;"&gt;
&lt;div style="display:inline-block;float:left;padding:0px 25px 8px 0px;"&gt;&lt;a href="/technologies/fpga-group/"&gt;&lt;img style="height:56px;width:56px;" alt="Summer of FPGA" height="56" src="/e14/assets/legacy/2021/SummerofFPGA_profile.png" width="56" /&gt;&lt;/a&gt;&lt;/div&gt;
&lt;div style="display:inline-block;vertical-align:top;width:70%;"&gt;&lt;span style="font-size:18px;font-weight:bold;"&gt;Verilog Code for Basic Logic Gates&lt;/span&gt;
&lt;p style="margin:0;"&gt;&lt;a class="jivecontainerTT-hover-container jive-link-socialgroup-small" href="/technologies/fpga-group/"&gt;FPGA Group&lt;/a&gt; | &lt;a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda"&gt;The Summer of FPGAs - Agenda&lt;/a&gt;&lt;/p&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;
&lt;p style="margin:0;"&gt;&lt;span id="da1792fd_b797_419f_8697_56983a9bf8c5"&gt;&lt;span&gt;&lt;a href="https://players.brightcove.net/1362235890001/NkxiVJdjx_default/index.html?videoId=6271310696001"&gt;players.brightcove.net/.../index.html&lt;/a&gt;&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;
&lt;p style="background-color:#e9f6fc;border:1px solid #b8d7e5;margin:0;max-width:744px;padding:8px;"&gt;&lt;span style="color:#000000;font-family:&amp;#39;Open Sans&amp;#39;, Arial, sans-serif;text-align:justify;"&gt;Join Whitney Knitter of Knitronics for two minutes as we discuss the logic and computer science behind programming with Verilog for Basic Logic Gates! Today we discuss the logical vs Bit wise operations in RTL! This&amp;#39;s the second part in a series of videos and blog posts over the course of the Summer of FPGA.&lt;/span&gt;&lt;/p&gt;
&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;
&lt;h2&gt;&lt;span style="color:#3334ca;"&gt;Supplemental Content&lt;/span&gt;&lt;/h2&gt;
&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5399/summer-of-fpgas-2-minute-fpgas-with-whitney-knitter"&gt;Summer of FPGAs: 2-Minute FPGAs with Whitney Knitter&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;ul&gt;
&lt;li&gt;&lt;a class="jive-link-blog-small" href="/technologies/fpga-group/b/blog/posts/getting-started-with-the-tinyfpga-lattice-diamond-3-12-on-ubuntu-18-04"&gt;Getting Started with the TinyFPGA &amp;amp; Lattice Diamond 3.12 on Ubuntu 18.04&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;
&lt;h2&gt;&lt;span style="color:#3334ca;"&gt;Additional Parts:&lt;/span&gt;&lt;/h2&gt;
&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;
&lt;table class="jiveBorder" style="border:1px solid #000000;width:100%;" border="1"&gt;
&lt;thead&gt;
&lt;tr&gt;
&lt;th style="background-color:#6690bc;border:1px solid #000000;color:#ffffff;padding:2px;text-align:left;" valign="middle"&gt;&lt;strong&gt;Product Name&lt;/strong&gt;&lt;/th&gt;
&lt;/tr&gt;
&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr&gt;
&lt;td style="border:1px solid #000000;padding:2px;"&gt;&lt;span&gt;&lt;span id="addProduct-eYm9O66r-linked" class="e14-init-shown" style="white-space:nowrap;"&gt;&lt;a class="jive-link-product-addtolist" href="https://www.element14.com/community/view-product.jspa?fsku=2355207&amp;amp;nsku=07X1682&amp;amp;COM=noscript" rel="noopener noreferrer" target="_blank"&gt;&lt;span class="pf-widget-map pf-productlink-cart-icon"&gt;&lt;/span&gt;&lt;/a&gt;&lt;a class="jive-link-product pf-embedded-product-link" href="https://www.element14.com/community/view-product.jspa?fsku=2355207&amp;amp;nsku=07X1682&amp;amp;COM=noscript" rel="noopener noreferrer" target="_blank"&gt;iCE40 FPGA&lt;/a&gt;&lt;/span&gt;&lt;span id="addProduct-eYm9O66r-unlinked" class="e14-init-hidden"&gt;iCE40 FPGA&lt;/span&gt;&lt;/span&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;tr&gt;
&lt;td style="border:1px solid #000000;padding:2px;"&gt;&lt;span&gt;&lt;span id="addProduct-9thMqbuQ-linked" class="e14-init-shown" style="white-space:nowrap;"&gt;&lt;a class="jive-link-product-addtolist" href="https://www.element14.com/community/view-product.jspa?fsku=&amp;amp;nsku=96AC6418&amp;amp;COM=noscript" rel="noopener noreferrer" target="_blank"&gt;&lt;span class="pf-widget-map pf-productlink-cart-icon"&gt;&lt;/span&gt;&lt;/a&gt;&lt;a class="jive-link-product pf-embedded-product-link" href="https://www.element14.com/community/view-product.jspa?fsku=&amp;amp;nsku=96AC6418&amp;amp;COM=noscript" rel="noopener noreferrer" target="_blank"&gt;tinyFPGA&lt;/a&gt;&lt;/span&gt;&lt;span id="addProduct-9thMqbuQ-unlinked" class="e14-init-hidden"&gt;tinyFPGA&lt;/span&gt;&lt;/span&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;
&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;
&lt;h2&gt;&lt;span style="color:#3334ca;"&gt;&lt;a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda"&gt;Summer of FPGA&lt;/a&gt; 2-Minute FPGAs - More Videos Coming Soon!&lt;/span&gt;&lt;/h2&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;

&lt;div style="font-size: 90%;"&gt;Tags: tinyfpga, summer_of_fpgas, whitney knitter, e14presents_whitney, fpga, knitronics, whitney_knitter&lt;/div&gt;
</description></item><item><title>2-Minute FPGAs: Verilog Code for Basic Logic Gates</title><link>https://community.element14.com/technologies/fpga-group/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates/revision/1</link><pubDate>Tue, 07 Sep 2021 15:51:01 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:9ba546dd-4550-4aa6-aac5-6364580665b3</guid><dc:creator>tariq.ahmad</dc:creator><comments>https://community.element14.com/technologies/fpga-group/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates#comments</comments><description>Revision 1 posted to Documents by tariq.ahmad on 9/7/2021 3:51:01 PM&lt;br /&gt;
&lt;div style="background:#ffffff;padding:14px 16px 16px 18px;margin:0;vertical-align:top;border:1px solid #dadada;"&gt;&lt;div style="float:left;display:inline-block;padding:0px 25px 8px 0px;"&gt;&lt;a href="/technologies/fpga-group/"&gt;&lt;img alt="Summer of FPGA" height="56" src="/e14/assets/legacy/2021/SummerofFPGA_profile.png" style="height:56px;width:56px;" width="56" /&gt;&lt;/a&gt;&lt;/div&gt;&lt;div style="display:inline-block;vertical-align:top;width:70%;"&gt;&lt;span style="font-size:18px;font-weight:bold;"&gt;Verilog Code for Basic Logic Gates&lt;/span&gt;&lt;p style="margin:0;"&gt;&lt;a class="jivecontainerTT-hover-container jive-link-socialgroup-small" href="/technologies/fpga-group/"&gt;FPGA Group&lt;/a&gt; | &lt;a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda"&gt;The Summer of FPGAs - Agenda&lt;/a&gt;&lt;/p&gt;&lt;/div&gt;&lt;/div&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;span id="da1792fd_b797_419f_8697_56983a9bf8c5"&gt;&lt;span&gt;&lt;a href="https://players.brightcove.net/1362235890001/NkxiVJdjx_default/index.html?videoId=6271310696001"&gt;players.brightcove.net/.../index.html&lt;/a&gt;&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;border:1px solid #b8d7e5;background-color:#e9f6fc;padding:8px;max-width:744px;"&gt;&lt;span style="color:#000000;font-family:&amp;#39;Open Sans&amp;#39;, Arial, sans-serif;text-align:justify;"&gt;Join Whitney Knitter of Knitronics for two minutes as we discuss the logic and computer science behind programming with Verilog for Basic Logic Gates! Today we discuss the logical vs Bit wise operations in RTL! This&amp;#39;s the second part in a series of videos and blog posts over the course of the Summer of FPGA.&lt;/span&gt;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;h2&gt;&lt;span style="color:#3334ca;"&gt;Supplemental Content&lt;/span&gt;&lt;/h2&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;ul&gt;&lt;li&gt;&lt;a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5399/summer-of-fpgas-2-minute-fpgas-with-whitney-knitter"&gt;Summer of FPGAs: 2-Minute FPGAs with Whitney Knitter&lt;/a&gt;&lt;/li&gt;&lt;/ul&gt;&lt;ul&gt;&lt;li&gt;&lt;a class="jive-link-blog-small" href="/technologies/fpga-group/b/blog/posts/getting-started-with-the-tinyfpga-lattice-diamond-3-12-on-ubuntu-18-04"&gt;Getting Started with the TinyFPGA &amp;amp; Lattice Diamond 3.12 on Ubuntu 18.04&lt;/a&gt;&lt;/li&gt;&lt;/ul&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;h2&gt;&lt;span style="color:#3334ca;"&gt;Additional Parts:&lt;/span&gt;&lt;/h2&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;table border="1" class="jiveBorder" style="border:1px solid #000000;width:100%;"&gt;&lt;thead&gt;&lt;tr&gt;&lt;th style="border:1px solid black;border:1px solid #000000;padding:2px;color:#ffffff;background-color:#6690bc;text-align:left;" valign="middle"&gt;&lt;strong&gt;Product Name&lt;/strong&gt;&lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;padding:2px;"&gt;&lt;span&gt;&lt;span class="e14-init-shown" id="addProduct-eYm9O66r-linked" style="white-space:nowrap;"&gt;&lt;a class="jive-link-product-addtolist" href="https://www.element14.com/community/view-product.jspa?fsku=2355207&amp;amp;nsku=07X1682&amp;amp;COM=noscript" target="_blank"&gt;&lt;span class="pf-widget-map pf-productlink-cart-icon"&gt;&lt;/span&gt;&lt;/a&gt;&lt;a class="jive-link-product pf-embedded-product-link" href="https://www.element14.com/community/view-product.jspa?fsku=2355207&amp;amp;nsku=07X1682&amp;amp;COM=noscript" target="_blank"&gt;iCE40 FPGA&lt;/a&gt;&lt;/span&gt;&lt;span class="e14-init-hidden" id="addProduct-eYm9O66r-unlinked"&gt;iCE40 FPGA&lt;/span&gt;&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;padding:2px;"&gt;&lt;span&gt;&lt;span class="e14-init-shown" id="addProduct-9thMqbuQ-linked" style="white-space:nowrap;"&gt;&lt;a class="jive-link-product-addtolist" href="https://www.element14.com/community/view-product.jspa?fsku=&amp;amp;nsku=96AC6418&amp;amp;COM=noscript" target="_blank"&gt;&lt;span class="pf-widget-map pf-productlink-cart-icon"&gt;&lt;/span&gt;&lt;/a&gt;&lt;a class="jive-link-product pf-embedded-product-link" href="https://www.element14.com/community/view-product.jspa?fsku=&amp;amp;nsku=96AC6418&amp;amp;COM=noscript" target="_blank"&gt;tinyFPGA&lt;/a&gt;&lt;/span&gt;&lt;span class="e14-init-hidden" id="addProduct-9thMqbuQ-unlinked"&gt;tinyFPGA&lt;/span&gt;&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;h2&gt;&lt;span style="color:#3334ca;"&gt;&lt;a class="jive-link-wiki-small" href="/technologies/fpga-group/w/documents/5341/the-summer-of-fpgas---agenda"&gt;Summer of FPGA&lt;/a&gt; 2-Minute FPGAs - More Videos Coming Soon!&lt;/span&gt;&lt;/h2&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;

&lt;div style="font-size: 90%;"&gt;Tags: tinyfpga, summer_of_fpgas, whitney knitter, fpga, knitronics, whitney_knitter&lt;/div&gt;
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