https://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-docen-USTelligent Community 12https://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-docSun, 14 Nov 2021 19:04:43 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7d125c7c-45fc-49a8-a132-1c3b9688746adychenhttps://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-doc#commentsCurrent Revision posted to Setup by dychen on 11/14/2021 7:04:43 PM<br /> <div style="margin:-10px -10px -11px -10px;padding:0px;"> <div class="xs-flex md-flex-row xs-flex-column xs-border xs-p1 xs-w100"> <div class="xs-pt2 md-pt0 xs-m1 xs-border-top md-border-top-none xs-w100 md-w100"><center><img class="xs-mr1 xs-mb1 xs-w65" alt="design challenge tile" src="/e14/assets/legacy/2021/5knitter_triptec.png" /></center> <div class="xs-text-3 xs-pb0 xbold"><a href="/technologies/fpga-group/w/documents/5399/summer-of-fpgas-2-minute-fpgas-with-whitney-knitter?ICID=fpga-featured-widget">Two Minute Tutorials</a></div> <ul> <li><a href="/technologies/fpga-group/w/documents/5416/2-minute-fpgas-clock-divider-circuits-their-timing-constraints?ICID=fpga-featured-widget">Clock Divider Circuits &amp; Their Timing Constraints</a></li> <li><a href="/technologies/fpga-group/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates?ICID=fpga-featured-widget">Verilog Code for Basic Logic Gates</a></li> <li><a href="/technologies/fpga-group/w/documents/5414/2-minute-fpgas-synchronous-vs-asynchronous-flip-flops?ICID=fpga-featured-widget">Synchronous vs Asynchronous Flip Flops</a></li> <li><a href="/technologies/fpga-group/w/documents/5413/2-minute-fpgas-logical-vs-bitwise-operations-in-rtl?ICID=fpga-featured-widget">Logical vs Bit wise Operations in RTL</a></li> <li><a href="/technologies/fpga-group/w/documents/5396/2-minute-fpgas-blocking-vs-nonblocking-statements-in-verilog?ICID=fpga-featured-widget">Blocking vs Nonblocking Statements in Verilog</a></li> </ul> </div> </div> </div><div style="clear:both;"></div> https://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-doc/revision/3Sun, 14 Nov 2021 17:10:38 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7d125c7c-45fc-49a8-a132-1c3b9688746adychenhttps://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-doc#commentsRevision 3 posted to Setup by dychen on 11/14/2021 5:10:38 PM<br /> <div style="margin:-10px -10px -11px -10px;padding:0px;"> <div class="xs-flex md-flex-row xs-flex-column xs-border xs-p1 xs-w100"> <div class="xs-pt2 md-pt0 xs-m1 xs-border-top md-border-top-none xs-w100 md-w100"><center><img class="xs-mr1 xs-mb1 xs-w65" alt="design challenge tile" src="/e14/assets/legacy/2021/5knitter_triptec.png" /></center> <div class="xs-text-3 xs-pb0 xbold"><a href="/2-minute-fpgas-clock-divider-circuits-their-timing-constraints?ICID=fpga-featured-widget">Two Minute Tutorials</a></div> <ul> <li><a href="/challenges-projects/element14-presents/secret-element14-presents/w/documents/5416/2-minute-fpgas-clock-divider-circuits-their-timing-constraints">Clock Divider Circuits &amp; Their Timing Constraints</a></li> <li><a href="/challenges-projects/element14-presents/secret-element14-presents/w/documents/5415/2-minute-fpgas-verilog-code-for-basic-logic-gates">Verilog Code for Basic Logic Gates</a></li> <li><a href="/technologies/fpga-group/w/documents/5414/2-minute-fpgas-synchronous-vs-asynchronous-flip-flops">Synchronous vs Asynchronous Flip Flops</a></li> <li><a href="/2-minute-fpgas-logical-vs-bit-wise-operations-in-rt?ICID=fpga-featured-widget">Logical vs Bit wise Operations in RTL</a></li> <li><a href="/2-minute-fpgas-getting-started-with-tinyfpga?ICID=fpga-featured-widget">Blocking vs Nonblocking Statements in Verilog</a></li> </ul> </div> </div> </div><div style="clear:both;"></div> https://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-doc/revision/2Sun, 14 Nov 2021 16:28:02 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7d125c7c-45fc-49a8-a132-1c3b9688746aChristyZhttps://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-doc#commentsRevision 2 posted to Setup by ChristyZ on 11/14/2021 4:28:02 PM<br /> <div style="margin:-10px -10px -11px -10px;padding:0px;"> <div class="xs-flex md-flex-row xs-flex-column xs-border xs-p1 xs-w100"> <div class="xs-pt2 md-pt0 xs-m1 xs-border-top md-border-top-none xs-w100 md-w100"><center><img class="xs-mr1 xs-mb1 xs-w65" alt="design challenge tile" src="/e14/assets/legacy/2021/5knitter_triptec.png" /></center> <div class="xs-text-3 xs-pb0 xbold"><a href="/2-minute-fpgas-clock-divider-circuits-their-timing-constraints?ICID=fpga-featured-widget">Two Minute Tutorials</a></div> <ul> <li><a href="/2-minute-fpgas-clock-divider-circuits-their-timing-constraints?ICID=fpga-featured-widget">Clock Divider Circuits &amp; Their Timing Constraints</a></li> <li><a href="/2-minute-fpgas-verilog-code-for-basic-logic-gates?ICID=fpga-featured-widget">Verilog Code for Basic Logic Gates</a></li> <li><a href="/2-minute-fpgas-synchronous-vs-asynchronous-flip-flops?ICID=fpga-featured-widget">Synchronous vs Asynchronous Flip Flops</a></li> <li><a href="/2-minute-fpgas-logical-vs-bit-wise-operations-in-rt?ICID=fpga-featured-widget">Logical vs Bit wise Operations in RTL</a></li> <li><a href="/2-minute-fpgas-getting-started-with-tinyfpga?ICID=fpga-featured-widget">Blocking vs Nonblocking Statements in Verilog</a></li> </ul> </div> </div> </div><div style="clear:both;"></div> https://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-doc/revision/1Sun, 14 Nov 2021 16:18:45 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7d125c7c-45fc-49a8-a132-1c3b9688746aChristyZhttps://community.element14.com/technologies/fpga-group/w/setup/27315/two-minute-tutorial-setup-doc#commentsRevision 1 posted to Setup by ChristyZ on 11/14/2021 4:18:45 PM<br /> <div style="margin:-10px -10px -11px -10px;padding:0px;"> <div class="xs-flex md-flex-row xs-flex-column xs-border xs-p1 xs-w100"> <div class="xs-pt2 md-pt0 xs-m1 xs-border-top md-border-top-none xs-w100 md-w100"><center><img class="xs-mr1 xs-mb1 xs-w65" alt="design challenge tile" src="/e14/assets/legacy/2018/techConnection_techspotLogo.png" /></center> <div class="xs-text-3 xs-pb0 xbold">Tech Spotlights</div> <ul> <li><a href="/summer-of-fpgas-tech-spotlight-adaptive-computing?ICID=fpga-featured-widget">Adaptive Computing</a></li> <li><a href="/tech-spotlight-summer-of-fpgas-the-bulls-eye-high-performance-test-system?ICID=fpga-featured-widget">The Bulls Eye&reg; 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