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Path III is the third session in the element14 Community’s structured FPGA-based SoC training. The first Path was held in 2018 and focused on programmable logic devices PLDs and featured the AVNET MiniZed development board, based on AMD’s Zynq-7000 SoC.

Path II convened in 2019 and offered more advanced learning opportunities and featured the AVNET Ultra96-V2 development board, based on AMD’s Zynq UltraScale+ MPSoC.

Path III will double the fun by offering structured training on both the MiniZed and Ultra96-V2 boards. Each training track will be followed by a design/build phase.

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    First, I would like to thank element14 for providing me one of the ten boards for the Arty-s7 series webinar. I was glad to be a part of the webinar and attended all three. I was also learning FPGA because of their several advantages and flexibility …
  • Blog: ZYNQ Stereo Camera Platform - Part1

    Stereopsis is the inference of depth by comparing two images from slightly different perspectives. There are a number of local and global algorithms used to obtain a real time stereo depth map. The computational requirements for stereo however are qu…
  • Blog: Image processing on ZC702 using PYNQ

    IntroductionThis project is a follow up from the previous project on porting the PYNQ framework to the ZC702 development board.In this article we will show how to leverage the xOpenCV framework in conjunction with the PYNQ framework  to implemen...
  • Blog: Porting PYQN to ZC702

    In this project we will port the PYNQ framework to the ZC702 development board.  Introduction The ZC702 is an official development board from Xilinx. This board sports a ZC7020 ZYNQ FPGA SoC. It comes with a number of peripherals including ...
  • Blog: FPGA camera lane detection with ZYNQ ZC702

    A couple of months back I received a ZC702 Xilinx development board from Randall after pitching an idea on how to build an embedded vision project. The board arrived a couple of weeks later (thank you Randall) and I started working on the steps to bu…