RE: XMOS's New Batch: xCORE-200 !

johnbeetem — Wed, 25 Mar 2015 00:06:31 GMT

As is usual with XMOS, it's difficult to understand what "16 cores" or "32 cores" really means. As I understand it, the xCORE-200 has one or more physical cores (what you'd normally think of as a "processor") and time-multiplexes 8 logical cores on each one. Each logical core runs an independent task and has independent processor registers. This is rather nice, because the independent tasks don't have to deal with register interlocks like you do in a high-performance pipelined single processor which makes the implementation a lot simpler and more efficient. So that 2000 MIPS from 16 cores is really two 1000 MIPS processors with enough registers to run 16 interleaved tasks.

All this interleaving must be handled by software and XMOS provides a suite of tools for that. In addition, my understanding is that the architecture is open so people can write their own general-purpose tools or specialized tools for a limited problem domain. This looks like a lot of fun and I'm hoping to check it out some day.

Please feel free to correct my misconceptions.

RE: XMOS's New Batch: xCORE-200 !

johnbeetem — Mon, 23 Mar 2015 23:26:46 GMT

Let us know when they come out with a cheap development board.

RE: XMOS's New Batch: xCORE-200 !

clem57 — Mon, 23 Mar 2015 22:28:51 GMT

Looking forward to what's new! Thanks [mention:b0bc65b9ecdc4307bd967592f00e340a:e9ed411860ed4f2ba0265705b8793d05]

Clem