Building A Direct Digital Synthesis Dual-Channel Signal Generator

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

hkhoshro — Sun, 02 Aug 2020 23:58:59 GMT

I would Like to add this figure which shows it works some of the times, One over 100 times. Which is weired for me

[View:/resized-image/__size/1159x712/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-78a3b0ed-c0d9-48ca-9b65-310c4cad377a/contentimage_5F00_188203.png:1159:712]

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

hkhoshro — Mon, 08 Jun 2020 02:15:38 GMT

Hello Shabaz,

Great work, I have watched some of your videos. Very impressive.
May I know how can I get access to the PCB or schematic of your DDS board with AD9954 ?
I have designed one for myself and I am not sure if that works as there are many important parameters related to the RF tracks.
I have found that Analogue device sells the evaluation kit for AD9954 which is too expensive for me. I will appreciate if you can share your board wo that I can use it in my project.

Thank you very much

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

colporteur — Fri, 10 Jan 2020 16:36:27 GMT

Impressive project. Not something I feel I could complete with the same level of commercial quality. Admirable.

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

derick007 — Thu, 09 Jan 2020 20:01:28 GMT

Hi Shabaz,

Tried your code. Results similar to mine. At 89MHz, the dc offset is still 1.4v and the sinewave sitting on top of it is 40mV pk to pk.

You will see from my table above I get the same values at 100 MHz using my code.

I think it could be an output filter on the DDS board or perhaps impedance mismatching at the higher frequencies ?

Regards, Derek

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

derick007 — Thu, 09 Jan 2020 16:46:48 GMT

Hi Michael, Shabaz

I would confirm the output from the board does have a 1.4 dc offset, which can be taken out by the scopes 1 megaohm ac input. This makes pk-pk measurements easier.

However even though the scope is an old Tektronix 2465 (300 MHz), there is also a 50 ohm input, presumably for cases there is undesirable reflections due to load mismatching.

Unfortunately this input does not have any dc blocking capacitor, making ac measurements that wee bit more difficult. I thought that was the reason for the discussion on the blocking capacitor.

The scope does have a 20MHz bandwidth limit switch, which is not activated.

The scope probes are stamped at 100 MHz.

Regards, Derek

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

derick007 — Mon, 06 Jan 2020 20:32:47 GMT

Hi Shabaz, I have been changing the value of the frequency tuning word in my sketch to see the effect on the output :

[View:/resized-image/__size/404x580/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-78a3b0ed-c0d9-48ca-9b65-310c4cad377a/contentimage_5F00_188195.png:404:580]

As you can see the output filter must have a corner/break point somewhere between 1 and 10 MHz.

Still having difficulties changing the amplitude of the output sinewave by adjusting the contents of the Amplitude Scale Factor (ASF), reloading the sketch and monitoing the output on my scope.

I have changed bits 25 and 25 (Autoshaped ON OFF Keying Enable bit, Shaped ON OFF keying enable bit) in CFR1 as well as changing the values in the ASF register. All to no avail.

I am reasonably confident my sketch is ok because the frequency changes I make all work perfectly. I am wondering is there a bit in the configuration registers which has not been setup correctly ?

//************************************************

//* SCLK test code for MKRZERO

//* rev 0.1 December 2019

//************************************************

// DECLARING / DEFINING VARIABLES & THEIR TYPES

char clockpin = A1; // declaring or defining the variable named clockpin as a character type which has a value A1

char datapin = A2; // declaring or defining the variable named datapin as a character type which has a value A2

char resetpin = A3; // declaring or defining the variable named resetpin as a character type which has a value A3

char ioupdatepin = A4; // declaring or defining the variable named ioupdatepin as a character type which has a value A4

char chipselectpin = A5; // declaring or defining the variable named chipselectpin as a character type which has a value A5

// DECLARING / DEFINING DDS REGISTERS

// INTEGERS ARE THE PRIMARY DATA TYPE FOR NUMBER STORAGE

// THE DDS HAS 11 REGISTERS WHICH NEED TO BE PROGRAMMED

// REGISTERS HAVE VARIOUS LENGTHS FROM 2 BYTES TO 5 BYTES

// I HAVE DECLARED EACH REGISTER HAS AN ARRAY OF INTEGER TYPE

// THE NUMBERS IN THE ARRAYS ARE DECIMAL NUMBERS

byte CFR1 [] = {0, 167, 0, 112, 8}; // declaring or defining the variable named CFR1[] (control function register 1) as a 5 byte array and byte data type

byte CFR2 [] = {1, 0, 10, 164}; // declaring or defining the variable named CFR2[] (control function register 2) as a 4 byte array and byte data type

byte ASF [] = {2, 63, 255}; // declaring or defining the variable named ASF[] (amplitude scale factor) as a 3 byte array and byte data type

byte ARR [] = {3, 0}; // declaring or defining the variable named ARR[] (amplitude ramp rate) as a 2 byte array and byte data type

byte FTW0 [] = {4, 0, 0, 41, 241}; // declaring or defining the variable named FTW0[] (frequency tuning word 0) as a 5 byte array and byte data type

byte POW0 [] = {5, 0, 0}; // declaring or defining the variable named POW0[] (phase offset word) as a 3 byte array and byte data type

byte FTW1 [] = {6, 0, 0, 41, 241}; // declaring or defining the variable named FTW0[] (frequency tuning word 1) as a 5 byte array and byte data type

byte RSCW0 [] = {7, 0, 0, 0, 0}; // declaring or defining the variable named RSCW0[] (ram segment control word 0) as a 5 byte array and byte data type

byte RSCW1 [] = {8, 0, 0, 0, 0}; // declaring or defining the variable named RSCW1[] (ram segment control word 1) as a 5 byte array and byte data type

byte RSCW2 [] = {9, 0, 0, 0, 0}; // declaring or defining the variable named RSCW2[] (ram segment control word 2) as a 5 byte array and byte data type

byte RSCW3 [] = {10, 0, 0, 0, 0}; // declaring or defining the variable named RSCW3[] (ram segment control word 3) as a 5 byte array and byte data type

void setup() {

pinMode(clockpin, OUTPUT); // sets pin A1 as OUTPUT

pinMode(datapin, OUTPUT); // sets pin A2 as OUTPUT

pinMode(resetpin, OUTPUT); // sets pin A3 as OUTPUT

pinMode(ioupdatepin, OUTPUT); // sets pin A4 as OUTPUT

pinMode(chipselectpin, OUTPUT); // sets pin A4 as OUTPUT

//reset the AD9954

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1); // delay 1 ms

digitalWrite(resetpin, LOW);

delay(1); // delay 1 ms

digitalWrite(resetpin,HIGH);

delay(1);

digitalWrite(resetpin, LOW);

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// WRITE TO AD9954

// CFR1

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, CFR1[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to CFR1 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// CFR2

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<4; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, CFR2[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to CFR2 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// ASF

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<3; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, ASF[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to ASF register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// ARR

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<2; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, ARR[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to ARR register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// FTW0

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, FTW0[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to FTW0 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// POW0

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<4; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, POW0[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to FTW0 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// FTW1

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, FTW1[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to FTW1 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// RSCW0

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW0[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to RSCW0 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// RSCW1

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW1[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to RSCW1 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// RSCW2

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW2[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to RSCW2 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

// RSCW3

digitalWrite(chipselectpin, LOW); // toggle CS

delay(1);

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW3[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

digitalWrite(chipselectpin, HIGH); // toggle CS

delay(1); // delay 1 ms

// the next few lines transfer data from the i/o buffer latches to RSCW3 register memory

digitalWrite(ioupdatepin, LOW);

delay(1); // delay 1 ms

digitalWrite(ioupdatepin,HIGH);

delay(1);

digitalWrite(ioupdatepin, LOW);

}

void loop() {

}

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

spiralphenomena — Sat, 30 Nov 2019 19:04:08 GMT

Just a thought, for about $10 more you could feed a 10MHz OCXO into the DDS boards for a much more accurate signal, a programmable amplifier would also be really useful to include, I wonder if there are any small dev boards that could do this?

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

derick007 — Mon, 18 Nov 2019 20:23:33 GMT

Hi Shabaz,

I have re-written the sketch entirely. My understanding now is alot simpler than when I started 6 months ago - hopefully it is correct ?

It would appear all that is required is to get the ARDUINO to write data to the registers in the AD9954 ?

I have worked all the values for all the registers, for the AD9954, on a spreadsheet so that I only need to use the sketch to send these values to the DDS.

However there are a few things I still am not clear about.

1. UPD - is this required ? If so when do I activate it > at the end of every transfer for each register ?

2. Surely I only need to write the values to the AD9954 once ? This being the case, then the part of the sketch which writes the values should be included in the void setup, rather than the void loop ?

One other thing, I have an old Tetronix 2465 scope which I am using for this project. I bought it some time ago and have rarely used it. Unfortunately it doesnt appear to trigger so well as I am getting a lot of jitter. This is really just a hobby so I have a very limited budget for test equipment - any suggestions apart from the obvious.

Many thanks, Derek

//************************************************

//* SCLK test code for MKRZERO

//* rev 0.1 December 2019

//************************************************

// DECLARING / DEFINING VARIABLES & THEIR TYPES

char clockpin = A1; // declaring or defining the variable named clockpin as a character type which has a value A1

char datapin = A2; // declaring or defining the variable named datapin as a character type which has a value A2

char resetpin = A3; // declaring or defining the variable named resetpin as a character type which has a value A3

char ioupdatepin = A4; // declaring or defining the variable named ioupdatepin as a character type which has a value A4

// DECLARING / DEFINING DDS REGISTERS

// INTEGERS ARE THE PRIMARY DATA TYPE FOR NUMBER STORAGE

// THE DDS HAS 11 REGISTERS WHICH NEED TO BE PROGRAMMED

// REGISTERS HAVE VARIOUS LENGTHS FROM 2 BYTES TO 5 BYTES

// I HAVE DECLARED EACH REGISTER HAS AN ARRAY OF INTEGER TYPE

// THE NUMBERS IN THE ARRAYS ARE DECIMAL NUMBERS

int CFR1 [] = {128, 174, 0, 112, 8}; // declaring or defining the variable named CFR1[] (control function register 1) as a 5 byte array and integer data type

int CFR2 [] = {129, 0, 0, 164}; // declaring or defining the variable named CFR2[] (control function register 2) as a 4 byte array and integer data type

int ASF [] = {130, 0, 0}; // declaring or defining the variable named ASF[] (amplitude scale factor) as a 3 byte array and integer data type

int ARR [] = {131, 0}; // declaring or defining the variable named ARR[] (amplitude ramp rate) as a 2 byte array and integer data type

int FTW0 [] = {132, 26, 57, 224, 0}; // declaring or defining the variable named FTW0[] (frequency tuning word 0) as a 5 byte array and integer data type

int POW0 [] = {133, 0, 0}; // declaring or defining the variable named POW0[] (phase offset word) as a 3 byte array and integer data type

int FTW1 [] = {134, 26, 57, 224, 0}; // declaring or defining the variable named FTW0[] (frequency tuning word 1) as a 5 byte array and integer data type

int RSCW0 [] = {135, 0, 0, 0, 0}; // declaring or defining the variable named RSCW0[] (ram segment control word 0) as a 5 byte array and integer data type

int RSCW1 [] = {136, 0, 0, 0, 0}; // declaring or defining the variable named RSCW1[] (ram segment control word 1) as a 5 byte array and integer data type

int RSCW2 [] = {137, 0, 0, 0, 0}; // declaring or defining the variable named RSCW2[] (ram segment control word 2) as a 5 byte array and integer data type

int RSCW3 [] = {138, 0, 0, 0, 0}; // declaring or defining the variable named RSCW3[] (ram segment control word 3) as a 5 byte array and integer data type

void setup() {

pinMode(clockpin, OUTPUT); // sets pin A1 as OUTPUT

pinMode(datapin, OUTPUT); // sets pin A2 as OUTPUT

pinMode(resetpin, OUTPUT); // sets pin A3 as OUTPUT

pinMode(ioupdatepin, OUTPUT); // sets pin A4 as OUTPUT

//reset the AD9954

digitalWrite(resetpin, LOW);

delay(1);

digitalWrite(resetpin,HIGH);

delay(1);

digitalWrite(resetpin, LOW);

}

void loop() {

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, CFR1[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<4; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, CFR2[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<3; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, ASF[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<2; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, ARR[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, FTW0[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<4; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, POW0[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, FTW1[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW0[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW1[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW2[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

for (int i=0; i<5; i=i+1) {

shiftOut(datapin, clockpin, MSBFIRST, RSCW3[i]); // each bit is approximately 5us. The clock signal also has a period of 5us, 1.5 us ON and 3.5 us OFF.

}

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

neuromodulator — Fri, 30 Aug 2019 02:15:17 GMT

What did you do to generate those images with the cabling? It looks pretty neat.

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

michaelkellett — Tue, 16 Jul 2019 10:37:44 GMT

You've just updated your post and added a load of stuff to it.

That is a terrible idea because it makes the thread impossible to follow.

You have also asked in an open forum for people to contact you by private email - that defeats the whole point of a forum which is to have open, free access to all, discussions.

This looks like a student project and you seem to be hopelessly out of your depth. Your course work and tutors should have given you a road map or the tools to make one.

I suggest that you go back to your tutor and ask for help and guidance - that's what they are there for.

If you then need advice on specific aspects of the task then start a new thread.

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

jc2048 — Mon, 15 Jul 2019 16:52:36 GMT

Amplitude +/- 5Vpp

Do you intend to series terminate the drive to the output cable? If so, you'll need more than 5V on each rail to get the required swing at the load.

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

michaelkellett — Mon, 15 Jul 2019 12:32:22 GMT

The USB port will not provide a good 5V supply - it may be as low as 4.5V and it may be noisy.

There are plenty of power supply conversion chips that can take <5 V in and generate +/- 5V out. They are hard to prototype with - you will need a pcb.

The LT3463 or LT3463A from Analog Devices will do for your application but you will need to restrict the maximum input voltage from the USB with a series diode.

Alternatively you could just use the USB voltage for 5V and use a negative switcher to make the -5V. An LT1611 would do quite nicely. Or, if you can cope with maybe only -4V worst case then

a TPS60403 (Texas Instruments) might do.

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

balearicdynamics — Sun, 02 Jun 2019 21:51:11 GMT

Hi Shabaz, it's a while I point my attention to this project, another great creation from you [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-78a3b0ed-c0d9-48ca-9b65-310c4cad377a/contentimage_5F00_1.png:16:16] What I am thinking is if this project – maybe with soe changes – can be applied in the audio synth. As a matter of fact, I see that the components you use reach a very high frequency but start from 1Hz so I suppose if can produce the entire range of the audible. Does this question have sens in your opinion?

Enrico

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

derick007 — Sun, 02 Jun 2019 21:34:22 GMT

Hi Shabaz,

Took your advice and purchased the Arduino MKR zero.

I am a novice SIMULINK user and i was hoping to use it to learn a bit about the Arduino board. However I am not exactly sure how to program the arduino board to control the AD9954.

I can only imagine it is programed in coded in C / assembler and the coded is detailed, complex and quite long ?

I have never used the C programming language, but am willing to learn. Not sure if the whole task is a bit much but I would like to find out.

Any pointers / suggestions would be welcome. In the end, making some adjustments to your code may be the solution.

SIMULINK will communicate with the Arduino and control i/o, not sure if it will provide enough programming functionality to allow it to control the AD9954 board.

If at all possible I will like to connect the AD9954 board to a pc to learn a bit about it. Analog Devices seem to suggest a parallel port is required to do this ?

RE: Building A Direct Digital Synthesis Dual-Channel Signal Generator

derick007 — Sat, 01 Jun 2019 18:33:35 GMT

Hi shabaz

I have both the ad9954 and arduino boards now.

I have downloaded software from analog devices to evaluate the ad9954, but it looks like I need an lpt parallel port on my pc to do this.

I dont mind doing this but as far as i remember the parallel port is db 25 way connecter, whereas the ribbon cable for the ad9954 is only 14 pins ?

Is there a converter i need ?