https://community.element14.com/technologies/en-USTelligent Community 12https://community.element14.com/technologies/power-management/b/alt-energy-blog/posts/chinese-researchers-replicate-photosynthesis-using-a-new-catalystFri, 03 Apr 2026 06:59:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:c091d0de-9c8f-4b7a-b0c8-0b9abc91bb8bCatwellDiagram on the left represents a natural photosynthesis system. Meanwhile, the diagram on the right represents the team’s proposed catalyst system. (Image Credit: nature communications ) Researchers at the Chinese Academy of Sciences created a new catalyst system that harnesses sunlight and stores charge. It also helps convert water and carbon dioxide into a fuel molecule. The team says their catalyst system could have applications in solar fuel production. Inspired by natural photosynthesis, the researchers’ system uses a tungsten-based reservoir that stores and distributes electrons, leading to efficient light-generated charges. In this setup, the artificial analogue’s job involves decoupling photocarrier degeneration from carbon dioxide conversion. This enables the independent optimization of charge separation and storage. It’s also based on a tungsten oxide charge reservoir combined with a molecular CO 2 -reduction catalyst. Under hydrothermal conditions, tungsten trioxide (WO 3 ) is synthesized from tungsten hexachloride (WCl 6 ) in ethanol. Afterward, it’s calcined in air for the oxide phase production. The team prepared Ag/WO 3 via photoassisted reduction. This involved irradiating the WO 3 dispersion under Ar to produce reduced W 5+ sites. They then added AgNO 3 before washing, drying, and calcining the product. With this step, the team fabricated a tungsten-oxide solution capable of storing and releasing charge while adding silver into the final material. They completed the CO 2 -reduction catalyst by coupling Ag/WO 3 with cobalt phthalocyanine (CoPc). To create the composite CoPC/Ag/WO 3 , the team dissolved CoPc in ethanol, mixing it with Ag/WO 3 , before sonicating, ball milling, and drying it. These steps were carried out to prepare other catalysts like CoPc/WO 3 . Control studies used composites with Cu 2 0 and C 3 N 4 . Measurements showing that Ag/WO 3 has the correct structure, silver environment, light-induced charge behavior, and charge electrons required to function as a charge reservoir. (Image Credit: nature communications ) When the team subjected the tungsten-based charge reservoir to light, the tungsten cycled between W 6+ and W 5+ , enabling temporary electron storage rather than losing it to recombination. The stored charge then helps remove photogenerated holes from the CoPc side, preserving a high electron density at the CO 2 sites. The team used XRD, Raman, XPS, EPR, XAFS, UV-Vis, DRS, and transient absorption to verify the charge-reservoir structure and oxidation states. A charge management technique like this makes the system highly effective. Decoupling charge storage from catalytic turnover allows the reservoir to help the molecular catalyst function more efficiently under irradiation. According to the paper, the CoPc/Ag/WO 3 catalyst achieves a CO production rate of ~1.5 mmol g CoPc −1 h −1 , approximately 100 times higher than CopC alone. Additionally, the paper says that Ag/WO 3 greatly boosts CO 2 conversion when coupled with various catalysts. This suggests the charge reservoir effect is useful instead of a one-time result. The team also says the main CoPc system achieves a stable run over six cycles and three days with no deactivation. Post-reaction characterization reveals that the structure remained the same. The team believes this system could be useful for solar fuel production as it helps reduce charge loss and enhance CO 2 conversion. This may even work with other catalysts that lose efficiency due to electrons recombining too quickly. Have a story tip? Message me here at element14.naturebiomimicrypowerenergyphotosynthesishttps://community.element14.com/technologies/embedded/m/managed-videos/151138Wed, 01 Apr 2026 15:04:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:0c7e6b6b-ee74-4d64-8a83-c9bb0ffa8cd3shabazhttps://community.element14.com/technologies/fpga-group/w/setup/26642/featured-content-triptych-setup-docWed, 01 Apr 2026 13:35:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7e3dbc4b-ad3d-4d73-aeac-6597508eadc2JoRatcliffePath to Programmable III Collaborated with Path III is the third session in the element14 Community’s structured FPGA-based SoC training. The first Path was held in 2018 and focused on programmable logic devices PLDs and featured the AVNET MiniZed development board, based on AMD’s Zynq-7000 SoC. Path II convened in 2019 and offered more advanced learning opportunities and featured the AVNET Ultra96-V2 development board, based on AMD’s Zynq UltraScale+ MPSoC. Path III will double the fun by offering structured training on both the MiniZed and Ultra96-V2 boards. Each training track will be followed by a design/build phase. Learn More Adaptive Computing The Bulls Eye® High Performance Test System Samtec Flyover® Technology for FPGA Apps Memory Storage for FPGA Applications Accelerating Embedded Vision with the CrossLink ™ -NX FPGA On Demand Webinars: Getting Started with the AMD Spartan ™ ︎ UltraScale+ ™ ︎ FPGA SCU35 Eval Kit PYNQ-Z2 Workshop Series: FPGA Experiments With Xilinx Pynq-Z2 Power Integrity Effects on FPGA Functionality and Performance Leveling-Up Your FPGA Skills: An Expert Panel Discussion Getting Started with FPGAs: An Expert Panel Discussion Summer of FPGA: Software and FPGA: How to Get the Bits to Flip? Intro to Smart Embedded Vision (SEV) Using a PolarFire ® FPGA Building Processor Based Systems on Lattice FPGAs Using Propelhttps://community.element14.com/technologies/internet-of-things/f/forum/56812/converting-the-sensecap-to-standard-lora-wan-gatewayWed, 01 Apr 2026 02:47:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:1dbe580c-36c4-4b98-9bc7-9a53ae0dadc1meera_hussienI have a SenseCAP gateway that I used previously for Helium, but I am not using it anymore. I am planning to convert it into a standard LoRaWAN gateway. I searched online and found that it seems possible. Just wanted to ask if any members here have tried this before, and was it successful? The link for this product is below https://www.sensecapmx.com/docs/sensecap-m1/overview/heliumlorawanseeeduinosensecaphttps://community.element14.com/technologies/fpga-group/m/managed-videos/151085Mon, 30 Mar 2026 11:29:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:3810f1e8-edff-4437-b7a4-231fdd6b797djc2048https://community.element14.com/technologies/fpga-group/b/blog/posts/lattice-ice40up5k-evb-evaluation-board---part-2-using-the-dsp-multiplierMon, 30 Mar 2026 11:02:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:945974a6-316c-47b3-b406-1c55ba707e6bjc2048Introduction This is a follow-on from this blog and will make more sense if you read that one first. The hardware is exactly the same as in that previous blog, all I'm going to do with this one is adapt (hack might be a better word) the VHDL to perform a different task. Having used the logic elements in the device, I thought it would be interesting to try one of the hard multipliers - the device has eight DSP [digital signal processing] blocks, each of which features a multiplier and an accumulator (a MAC). Since the test code in that previous blog already generates two sine waves, a very easy thing to do would be to simply multiply them together. It's especially convenient in that the multiplier in the DSP block can be used with 16-bit signed values, which happens to be the size of the sines I'm generating with the CORDIC component. I'm going to leave one set to 440Hz and set the other to sixteen times that, plus a little bit (7040.1Hz) so that they move slowly relative to each other. This is the diagram of the DSP block from the family datasheet. It looks very complicated, but isn't really. If you take away the pipeline registers and the muxes, that are there to bypass them if they're not used, what's left is a 16x16 multiplier, made up of four 8-bit multipliers, on the left, and a 32-bit accumulator, made up of a pair of 16-bit accumulators, on the right. That allows the DSP block to work with a single 16 bit multiplier and single 32 bit accumulator, or to be split in two and operate with a pair of 8 bit multipliers, each with a 16-bit accumulator. The VHDL There are basically two ways I can use the multiplier. One is instantiation, the other inference. With instantiation, I create an instance of a DSP component and connect to it as we would for any component in VHDL. That uses a black box component supplied by Lattice that the synthesis and place-and-route know to map to the hard multiplier. That gives a lot of control over the DSP block, but does mean I'll need to read the documentation, and it locks us into the Lattice ecosystem. The 'IP Catalog' includes a multiplier part which is an easier way to set up the instantiation - I haven't tried that yet. With inference, we simply use the multiply operator within VHDL and trust that the synthesis will realise that it can use the hard multiplier within the DSP block and not try and build one out of logic. It almost certainly will do. The advantage of inference is a fair chance of portability (particularly in this case, where other, more expensive, FPGAs designed for serious DSP work generally have multipliers with a longer wordlength). Here's the top level code. It's not actually all that much different: a multiply operator to do the work, some manipulation of the result (which will be 32 bit) to take just the top half in order to reduce it to 16 bits again, and that's it. The other two, for the components, are the same as before. ---------------------------------------------------------------------- -- ***** ice40up5k_evn_test_mult.vhd ***** -- -- -- -- Lattice ICE40UP5K evaluation board multiplier test. -- -- Generates fixed pair of CORDIC 16-bit sine waves, multiplies them-- -- and formats result for an S/PDIF serial optical link. -- -- -- ---------------------------------------------------------------------- -- (C)2026 Jon Clift -- -- Free to use however you want. No warranty as to correctness. -- -- No guarantee of fitness for any purpose. No obligation to support-- ---------------------------------------------------------------------- -- Rev Date Comments -- -- 01 25-Mar-2026 based on ice40up5k_evn_test.vhd -- ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity ice40up5k_evn_test is port( clk_12: in STD_LOGIC; --- system clock in (from 12MHz oscillator) clk_12_288: in STD_LOGIC; --- clock in (from my 12.288MHz oscillator) tp1: out STD_LOGIC; --- scope trigger at start of frame spdif_out: out STD_LOGIC); --- s/pdif data stream (to optical tx) end ice40up5k_evn_test; architecture arch_ice40up5k_evn_test of ice40up5k_evn_test is constant sig_resol: POSITIVE := 16; --- signal resolution (bits) constant pha_resol: POSITIVE := 32; --- phase resolution (bits) signal theta: SIGNED(pha_resol-1 downto 0); --- phase accumulator signal theta_left: SIGNED(pha_resol-1 downto 0); --- left phase accumulator signal theta_right: SIGNED(pha_resol-1 downto 0); --- right phase accumulator signal phase_increment_left: SIGNED(pha_resol-1 downto 0); --- left phase increment signal phase_increment_right: SIGNED(pha_resol-1 downto 0); --- right phase increment signal sine: SIGNED(sig_resol-1 downto 0); --- CORDIC generated sine signal cosine: SIGNED(sig_resol-1 downto 0); --- CORDIC generaated cosine signal sample_left: SIGNED(sig_resol-1 downto 0); --- left sample signal sample_right: SIGNED(sig_resol-1 downto 0); --- right sample signal mult_result: SIGNED(31 downto 0); --- output sample (left * right) signal delay_i: STD_LOGIC; --- signal delay_o: STD_LOGIC; --- signal delay_o_1: STD_LOGIC; --- signal spdif_clk_en: STD_LOGIC; --- signal spdif_sample_en: STD_LOGIC; --- signal sample_en_del1: STD_LOGIC; --- signal sample_en_del2: STD_LOGIC; --- signal prescale_count: UNSIGNED(1 downto 0); --- --- declare the s/pdif output component component spdif_out_component is generic( in_res: POSITIVE); --- audio sample resolution port ( clk_in: in STD_LOGIC; --- clock clk_en: in STD_LOGIC; --- clock enable l_data: in SIGNED(in_res-1 downto 0); --- left audio data in r_data: in SIGNED(in_res-1 downto 0); --- right audio data in next_sample_en: out STD_LOGIC; --- trigger sample update spdif_data_out: out STD_LOGIC); --- output bitstream end component; --- declare the CORDIC component component cordic is generic( input_resol: POSITIVE; --- input resolution output_resol: POSITIVE); --- output resolution port( clk_in: in STD_LOGIC; --- clock in delay_in: in STD_LOGIC; --- delay in delay_out: out STD_LOGIC; --- delay out theta: in SIGNED(pha_resol-1 downto 0); --- phase in sine: out SIGNED(sig_resol-1 downto 0); --- sine out cosine: out SIGNED(sig_resol-1 downto 0)); --- cosine out end component; begin --- main process --- runs two phase accumulators, one for left and one for right --- CORDIC component calculates sine of each --- results stored and handed to spdif component for output formatting evb_test_stuff: process (clk_12_288) is begin if (clk_12_288'event and clk_12_288 = '1') then --- divide clock by 2 to run SPDIF at 6.144MHz for 48ksps if(spdif_clk_en = '0') then spdif_clk_en sig_resol) --- audio sample resolution port map( clk_in => clk_12_288, clk_en => spdif_clk_en, l_data => sample_left, r_data => sample_right, next_sample_en => spdif_sample_en, spdif_data_out => spdif_out); --- instantiate and connect the CORDIC component cordic_1: component cordic generic map( input_resol => pha_resol, --- input resolution output_resol => sig_resol) --- output resolution port map( clk_in => clk_12_288, --- clock in delay_in => delay_i, --- delay in delay_out => delay_o, --- delay out theta => theta, --- phase in sine => sine, --- sine out cosine => cosine); --- cosine out tp1 <= spdif_sample_en; end arch_ice40up5k_evn_test; Results Here's the signal generated. As before, I've passed it through a mixer to clean up the noise. Note that this isn't straight amplitude modulation: the result is double-sideband-suppressed-carrier [the sum and the difference between the two frequencies, without a carrier between them]. For amplitude modulation, the sine envelope would need to be offset so that it was all positive - I might try that later if I get a bit of time. Here's the FFT of that waveform which shows the two sidebands and the absence of a carrier. Quite noisy, though it's difficult to quantify with a fairly basic 8-bit oscilloscope. So the multiplier works fine. The synthesis has definitely used the real multiplier because I can see the use of a single DSP block reported by the place-and-route and see the connections to a DSP block on the physical view. Here's a rather boring video showing the resulting waveform. Unfortunately, I think I have my right and left on the audio swapped - what I'm referring to as 'right' in the code comes out on the white RCA rather than the red one. Ho hum! If you copy this, you'll need to do some simple faultfinding and make a few minor corrections. community.element14.com/.../MVI_5F00_4281.MOV Conclusions Anyway, that's a very simple example of the DSP capabilities of the device in action. The other two elements of this FPGA that I haven't looked at yet are the (single) PLL [usually just used for multiplying-up an input clock] and the block RAM. I'm going to leave the PLL for the moment and in the next blog do something with a block RAM. Further information [1] https://community.element14.com/technologies/fpga-group/b/blog/posts/lattice-ice40up5k-evb-evaluation-board-outputing-audio-sine-waves-over-an-optical-s-pdif-interface [2] https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus [3] https://www.latticesemi.com/products/developmentboardsandkits/ice40ultraplusbreakoutboard [4] https://uk.farnell.com/lattice-semiconductor/ice40up5k-b-evn/breakout-board-ice40-ultraplus/dp/3770328 [�71.32 + VAT each, Feb 2026] [5] https://en.wikipedia.org/wiki/Double-sideband_suppressed-carrier_transmissionsinefpgacordicvhdldsplatticeice40up5ks/pdifhttps://community.element14.com/technologies/wireless/m/managed-videos/151083Mon, 30 Mar 2026 06:05:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:38dbe6f8-bc8f-444a-9cb0-65753cef0140CatwellFrequency Hopping with Nrf24l01+ https://paulplusx.wordpress.com/2017/03/19/frequency-hopping-with-nrf24l01/https://community.element14.com/technologies/embedded/b/blog/posts/esp32-cheap-yellow-display-cyd-guide-with-a-jellyfish-exampleSun, 29 Mar 2026 18:15:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b373b718-282b-48fa-9ac9-01f6c8638b5ashabazTable of Contents Introduction CYD Features Is It Any Good? CYD Connections Reference RGB LED Micro SD Socket UART and BOOT pin Audio Output Spare Input/Output Connections Touch Interface TFT Screen, Backlight and Light Sensor (Light Dependent Resistor) Install VS Code, and PlatformIO Extension Download the Jellyfish Project Open the Project Folder in VS Code Build the Project Uploading Firmware to the Board Summary Introduction The Cheap Yellow Display (CYD) is a very low-cost board with a 2.4” RGB TFT screen on one side, and an ESP32 module on the other! The formal name is ESP32-2432S028 but it’s known as the CYD for self-explanatory reasons. I recently saw a project on Hackaday.io (a site I usually ignore, because most projects documented there are incomplete, usually missing schematics or code) and was happy to see the author had provided a GitHub repository link to the code . The project used the CYD, and I thought it would be a nice gift for my little niece. https://youtu.be/K31UgdS-Uqc This blog post describes the CYD, the connections present on it, and how to go about using the CYD! It's a very short process; about an hour from start to finish. In brief, using the CYD entails connecting it to the PC using the supplied USB cable, and then in terms of the software environment, one can install Visual Studio Code (VS Code) , and then withing that select to install an extension called PlatformIO, and that will provide task items in a list, that can be clicked to build code, and upload it to the board. All the steps are described further below. The example project will be the jellyfish project as mentioned above. CYD Features The CYD diagram here shows what’s on the board, and it can be used as a pinout reference when coding. The component side has an ESP32 module ( PDF Datasheet ) with approximately 4 Mbyte Flash, and about 520k RAM, 2.4 GHz wireless LAN capability, and Bluetooth Low Energy (BLE). There is also an RGB LED, a 1W audio amplifier, Micro SD card socket (very useful for logging or configuration files for projects) and very few spare GPIO connections brought out to a couple of connectors. The board I purchased had both USB-C and Micro-USB connectors, but they are attached to the same signals, so both must not be used simultaneously. Power entry can come from either the connector labelled P5, or either of the USB sockets. Software can be debugged using the USB Serial interface present on the USB connectors, or using an external USB-UART adapter connected to P5. There are boot and reset buttons, which are needed during device programming. The other side contains just the TFT touchscreen, and a little light sensor (Light Dependent Resistor). Is It Any Good? The board arrives with a USB-C to Type A cable (a USB-C to USB-C cable will not work), and a short 4-wire cable if required for any external UART or GPIO connections, and a little plastic stylus, although the touchscreen can be pressed with fingers too. The 2.4” 240 x 320 resolution TFT screen is very basic, the contrast is quite poor, but that’s to be expected at such a low price. I think it is very good value for money, and the board can be used for user interfaces (for example). The board I purchased has space for an additional Flash chip to be installed, but that was not fitted on the board; the only Flash memory present is that inside the ESP32 module. CYD Connections Reference There isn’t an official schematic, but it’s possible to figure out the connections. Here they are! RGB LED There is a large RGB LED near the ESP32 module. The GPIO pins need to be pulled low to turn on the LEDs. GPIO# Connection 4 Red Cathode 16 Green Cathode 17 Blue Cathode Micro SD Socket The Micro SD interfaces uses a Serial Peripheral Interface (SPI): GPIO# Connection 5 *CS 23 MOSI 19 MISO 18 SCLK UART and BOOT pin The serial interface connects to both the USB connector (via a CH340C USB-to-Serial converter ) and to a board connector P5, through 100 ohm resistors. A supplied cable can be used. ESP32 Signal Name Description RDX0 ESP32 Board Rx, and P5 pin 3 (Blue wire) TXD0 ESP32 Board Tx, and P5 pin 2 (Yellow wire) The detail for connector P5: P5 Pin Description 1 5V Board Power Input (Red wire) 2 ESP32 Board Tx (Yellow wire) 3 ESP32 Board Rx (Blue wire) 4 GND (Black wire) The ESP32 boot pin is GPIO#0, and it is connected to a push-button to the left of the ESP32. It may need to be held down, while tapping RST, when programming the board. The boot pin is also connected to the CH340C chip to try to automate the boot control from the PC during device programming, but it didn’t work for me, and I had to use the push-button. Audio Output One pin (GPIO26) is wired to an SC8002B audio amplifier IC, which is a 1W 8-ohm bridge-tied-load amplifier, wired to a 2-pin connector labelled SPEAK. The connection is through an RC filter. GPIO26 can be operated in a DAC mode (peripheral signal name DAC_2) or perhaps PWM could be performed (no idea). Spare Input/Output Connections A few GPIO pins are brought out to two connectors, called CN1 and P3. CN1: CN1 Pin Connection 1 3.3V 2 GPIO27 3 GPIO22 (also present on conn P3) 4 GND P3: P3 Pin Connection 1 GPIO21 2 GPIO22 (also present on conn CN1) 3 GPIO35 4 GND Touch Interface There is a resistive touch layer on the TFT screen, and it can be pressed by fingers or using the supplied stylus. The touch interface uses an XPT2046 IC ( PDF datasheet ) in a TSSOP package. GPIO# Connection 36 Touch *PENIRQ (input to ESP32) 32 Touch DIN (MOSI output from ESP32) 39 Touch DOUT (MISO input to ESP32) 25 Touch DCLK (output from ESP32) 33 Touch *CS (output from ESP32) TFT Screen, Backlight and Light Sensor (Light Dependent Resistor) The TFT screen uses an ILI9341_2 software driver ( Driver IC PDF datasheet ). The reset pin is hard-wired to the board reset circuitry, i.e. a capacitor keeps it low at power-up briefly. The Light Dependent Resistor (LDR) is attached to GPIO pin that may need a pull-up configured in software, perhaps. GPIO# Connection 14 TFT SCLK 2 TFT DC (Data/*Command) 15 TFT *CS 13 TFT MOSI (ESP32 Output) 12 TFT MISO (ESP32 Input) 21 TFT Backlight PWM (High = ON) 34 (ADC1_CH6) Light Dependent Resistor to GND Install VS Code, and PlatformIO Extension To get going with the CYD, first install VS Code . Then, install the PlatformIO extension by following the steps shown in this screenshot: Then, restart VS Code! Later, you might see Installing PlatformIO Core messages at the bottom-right of the VS Code window at some point, such as when a project folder is opened. If you see that, let it complete, and then click Reload Now . Download the Jellyfish Project Create a general projects folder, for instance, C:\DEV\projects Ensure you have git installed (install it using https://git-scm.com/download/win ) Open PowerShell , navigate to that general projects folder, and type the following, which will create a folder called denki-kurage and the source code will be placed there by the command: git clone https://github.com/likeablob/denki-kurage.git Open the Project Folder in VS Code Go to File->Open Folder and select the downloaded project folder denki-kurage. Click to trust the folder if prompted. You can view the code, by clicking on the left side explorer view, for instance, click on src and select main.cpp . The code will appear in the main pane. You should see a load of messages appear in VS Code at the lower-right, regarding PlatformIO performing project configuration operations. It may take a quarter of an hour or so to complete, even on a fast PC, and it may well sit at 100% for quite a while, seemingly doing nothing, but let it complete. I wasn’t impressed by PlatformIO’s poor status messages and the crazily long install time. Eventually you should see this: Build the Project Click on the PlatformIO icon on the left side icon bar, it looks like an alien head. Then click on cyd->General and then select Build . You should see a load of messages appear at the bottom, followed by Success messages. Uploading Firmware to the Board Plug in the USB cable into to the board and into your PC. You should hear a Windows device installed sound after a few seconds. Windows Device Manager will show a port installed, in my case, it was COM3 but the number will vary. The display on the board should be lit up, and may display an image that is part of any factory firmware that may be in Flash memory. Look at the back of the board, and locate the two buttons. The top one is labelled RST (Reset) and the one below it is labelled BOOT . The plan will be to click on Upload in VS Code, and then when you see a Connecting… message appear, quickly press down BOOT, and while holding it down, press and immediately release RST. Then you can release BOOT. What this does, is essentially ensure that BOOT is pressed during a board reset. Click on cyd->General->Upload , and notice the Connecting… text at the bottom: Now, as soon as that text appears, hold down the lower button (BOOT), then tap the top button (RST) and then release BOOT. You should see some uploading messages appear, followed by Success messages: Take a look at the LCD on the board, and a jellyfish should be present! Tap the jellyfish to change its colour. The jellyfish happened to be on a white background which I didn't like, so I edited the src/config.h file, to add the following line: #define CYD_INVERT_DISPLAY After that, I re-built and re-uploaded the firmware, and all was well. Summary The Cheap Yellow Display is a very low cost ESP32 microcontroller board with built-in touchscreen TFT. To get going with it, VS Code was downloaded, a PlatformIO extension installed, and then it was just a matter of clicking to build and upload any code. My board required the BOOT and RST buttons to be used during the code upload process. For next steps, I'd like to personalize the display, and maybe get it to display the time at the bottom too, so it can function as a desk clock. For other unrelated projects, the code could perhaps be used as a template, for custom code. Thanks for reading!esp32platformioespressifCheap Yellow DisplayCYDESP32-2432S028https://community.element14.com/technologies/embedded/m/managed-videos/151081Sun, 29 Mar 2026 18:15:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:70969f06-d8f8-41fe-8165-b56ba702f71fshabazNot my project - see https://github.com/likeablob/denki-kurage for the details. I merely tried it out!