Programmable Electronic Load - Power Stage

Jan Cumps — Sun, 11 Oct 2020 08:07:25 GMT

Current Revision posted to Documents by Jan Cumps on 10/11/2020 8:07:25 AM

This blog documents focuses on the power stage of the electronic load that Robert Peter Oakes, jc2048 and Jan Cumps are designing.

In this post we're laying out a PCB for the power stage - as much as possible with surface mount components. The FET is close to the one Robert Peter Oakes uses in the original design.

The BOM

Component	Header 2	Header 3
P1	8 pin header, 2.54mm
P2 a	binding post, red	hirschmann 931714101hirschmann 931714101 - SOCKET, 4MM, BLACK, PK5 , MLS
P2 b	binding post, black	hirschmann 931714100hirschmann 931714100 - SOCKET, 4MM, BLACK, PK5 , MLS
P3 a	binding post, black	tenma 2301tenma 2301 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Black
P3 b	binding post, red	tenma 2302tenma 2302 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Red
TH1	NTC Thermistor, 10K	Vishay NTCS0805E3103JLTVishay NTCS0805E3103JLT - THERMISTOR, 10K, 5%, SMD, NTC
Q1	N-Channel Mosfet	Infineon IRF3205SPBFInfineon IRF3205SPBF - MOSFET Transistor, N Channel, 110 A, 55 V, 8 mohm, 10 V, 4 V
D1, D2	Diode	DIODES SBR2A40P1-7DIODES SBR2A40P1-7 - Standard Recovery Diode, Powerdi®, 40 V, 2 A, Single, 500 mV, 50 A
R1	100R	1206 any brand
R2	0R05	Vishay WSHP2818R0500FEBVishay WSHP2818R0500FEB - SMD Current Sense Resistor, 0.05 ohm, 10 W, 2818 [7146 Metric], ± 1%, WSHP2818 Series
	Cooler Heatsink	Startech.com FAN370PRO - Socket 7/370 CPU Cooler Heatsink and Fan

NTC

For a detailed description on the temperature protection mechanism, check Programmable Electronic Load - Temperature Protection.

The voltage sent to the ADC is very dependent on the NTC. I've selected a Vishay NTCS0805E3103JLTVishay NTCS0805E3103JLT - THERMISTOR, 10K, 5%, SMD, NTC.

I'll program the key values. The behaviour is non-linear and it's easier to make a lookup table if the firmware has to be able to deal with different components.

This will require access to flash to permanently store tha values, and a SCPI function to alter the table if another component is used.

For the first version I'm going to be selfish and just program for the device that I've ordered.

PCB

Exposed copper

For good thermal relief, and to get the NTC as good termally coupled to the FET as possible,

I placed a copper pour (here on the front, I'll do the same on the back and stitch them for thermal transport with vias)

Then i drew a pour on the front mask. The area of pour will expose copper. That means that the NTC has physical contact with the copper that the FET is soldered on.

In the fine-tuning I will place that NTC closer to the FET so that I can put a tad of heat paste in between. Or I could put a tad of paste between the NTC and exposed copper ...

Attention when placing the binding posts. For the power input, RED is 1 and BLACK is 2.

For the sense input, BLACK is 1 and RED is 2.

This is the result of me labeling pin 7 and 8 of the connectors between the driver board and FET board wrong, on both boards .

The documentation and KiCAD zips are now updated with corrected schematics.

I used these 2 Contextual Electronics videos to refresh how to expose copper layers and place VIA arrays:
www.youtube.com/watch	www.youtube.com/watch

Here's the top side of the completed design. I've drawn the FET in green to give perspective.

In red you see the copper layer, orange is where the solder mask is removed and copper exposed.

Pink are the drill holes. They are 0.9652 mm, in an array of 9 * 8, spaced 2 mm apart.

On the bottom, the copper pad (green) has the size of my heat sink + some. The removed mask (blue) has the exact size of the sink's bottom profile.

The pink lines are the mounting slots for the heat sink (see below).

Slots

My heat sink has brackets for mounting. I've cut out slots to allow the brackets to through the PCB and fix them on the top side.

I've put some exposed non-connected copper pour around the slots for strength.

The slot is drawn on the Edge.Cuts layer. I hope that the PCB fab interprets that as slots to be milled out ...

I've attached the KiCAD project, component libs and Gerbers in a single zip. Also the VIA lib that's used here as a separate file (because I share that one across projects).

Attachments:

community.element14.com/.../vias.pretty.zip
community.element14.com/.../eload_5F00_offboard_5F00_20171227.zip

Tags: mosfet, metrology, ntc, msp432, scpi, laboratory, instrument