HF Vector Network Analyzer - Performance

shabaz — Mon, 06 Jan 2020 22:36:21 GMT

Current Revision posted to Documents by shabaz on 1/6/2020 10:36:21 PM

Note: This document describes the performance of a DIY Vector Network Analyzer known as the N2PK VNA. This series of blog posts describes what you can use a VNA for and how the VNA internally functions. Subsequent posts will describe the circuit and construction.

This document's copyright belongs to Paul Kiciak, N2PK, pkiciak@adelphia.net, reproduced with his permission. Any minor changes are for converting to HTML content with page jumps or splitting content, adding hyperlinks and so on - i.e. purely readability related. Any word modifications more significant than that will always be indicated in some manner (e.g. highlighting or notes), so that the original text meaning or data is not lost. This document is also under version control. All diagrams/photos are clickable to increase the resolution. If you have any corrections or comments, or performance information to contribute, please comment below (it is possible to insert high-res inline photos/diagrams and videos in the comments below too).

Introduction
Master Oscillator(PCB Mount)
RF and LO DDSs
Detector
System Dynamic Range (10 MHz)
Interface
Control and Data Processing
Power Requirements
Warm-up and Temperature Sensitivities
Transmission Accuracy
Reflection Accuracy
Group Delay Accuracy
Summary

Introduction

This document summarizes the key performance related characteristics of the VNA described here: HF Vector Network Analyzer - Theory of Operation

Unless otherwise indicated, normal room ambient temperature is assumed. Due to limited hardware availability, typical measured values are shown.

There are some 2nd order thermal effects on Detector offset due to relatively small changes in DDS power dissipation with output frequency. As a result, frequency sweeps over narrow ranges may be slightly more accurate than sweeps done over wider ranges. Where applicable, narrowband or spot frequency testing was done in what follows.

Due to the broad range of options for bridges, their characteristics will not be included here, but in another document instead.

Where applicable and possible, the format used here follows that of a typical commercial VNA.

Master Oscillator(PCB Mount)

Frequency: 148.344 MHz
Type: 7th overtone BJT-FET Butler crystal oscillator
Output levels: CMOS compatible square wave, approx. 4.5 V pp minimum. centered on +2.5V DC, 45-55% duty cycle.
Loading: PCB traces, two 74AC74 Clk inputs, two AD9851 REFCLK inputs.

RF and LO DDSs

Frequency Range:
- VNA: 50 kHz – 60 MHz
- Usable: AC coupling limited, LO DDS is -3 dB at 0.2 Hz into a 1 Meg-Ω DC load. The RF DDS waveshape is limited by transformer saturation and is approx. sinusoidal down to 25 kHz with a 50 Ω load, lower frequency if more heavily loaded.
- RF and LO DDSs are independently frequency and phase programmable
Frequency resolution: approx. 0.035 Hz
Frequency Accuracy: +/-0.1 ppm with 10 MHz WWV, adjusted in software
Frequency Power-On Drift: -3 ppm or less
Frequency Temperature Coefficient: -0.1 ppm / °F or less after initial warm-up
Output levels @ 1 MHz into 50 Ω:
- RF DDS: 1.0 V pp (+3.9 dBm)
- LO DDS (each output): 0.5 V pp (-2.0 dBm)
DDS output level vs. Frequency:
- RF DDS

- LO DDS filtered output (approx. 6 dB below RF DDS thru 30 MHz)

Nominal RF and LO Source Impedance: 50 Ω.
DDS Return Loss vs. Frequency @ F/SMA
- RF DDS

- LO DDS, filtered output

RF DDS Spurious Outputs (50 Ω load):
- Harmonics
  - -55 dBc or better, Fo=50-60 kHz
  - -60 dBc or better, 0.06-10 MHz
  - -50 dBc or better, 10-60 MHz
  - 2nd harmonic dominant above 70 kHz
- Aliases
  - -50 dBc or better, 0.05-45 MHz
  - -30 dBc or better, 45-60 MHz
  - -45 dBc @ Fo = Fmo/3 = 49.448 MHz
- Other spurii
  - -70 dBc or better, 0.05-60 MHz
Phase Noise (measured at 10.2 MHz by W4ZCB)

Offset (Hz)	dBc / Hz
100	-120
200	-120
300	-120
400	-130
500	-132
600	-134
700	-134
800	-132
900	-132
1k	-136
2k	-137
4k	-141
5k	-140
10k	-142
50k	-142
100k	-121
101k	-142

Detector

Type: Narrowband, linear, and direct convert to DC
Effective RF bandwidth: approx. 5 Hz
Gain: approx. 9 dB, rms at Det. RF In to DC out at the ADC input
Offset voltage: +/- 3 mV DC or less @ ADC input
ADC Input Range: -1.25 to +1.25 VDC
ADC Resolution: 24 bits
Effective Number of Bits: approx. 20
Conversions/sec: 7 (equivalent to 3.5 frequencies per second)
Maximum RF Input Signal: Approx. +5.5 dBm
Nominal RF and LO Input Impedance: 50 Ω
RF In Return Loss vs. Frequency @ F/SMA:

Magnitude Linearity, Accuracy, and Noise (Kay SMA 0-135 dB attenuator measurements at 10 MHz with return losses of 38 and 40 dB)
- Mean of 32 samples

- With noise (No averaging)

Phase Linearity, Accuracy, and Noise (same DUT as above), no averaging)

Effect of averaging (noise limited)

Detector dynamic range (10 MHz)
- 114 dB, no averaging
- 121 dB, averaging 10 ADC readings

System Dynamic Range (10 MHz)

112 dB, no averaging (Less in some cases depending on the DUT characteristics and harmonic mixing)
119 dB, averaging 10 ADC readings

Interface

Parallel Port on an IBM compatible PC, recommend use of an IEEE 1284 compliant parallel cable.

Control and Data Processing

Software: DOS applications
Tested end use environments: DOS, Windows 95, 98, and Windows 2000 with a virtual device driver such as Direct I/O

Power Requirements

Input DC Voltages and Current
- +12 V (+9 V min. +15 V max) @ 25 mA and
- +5.0 V +/-5% @ approx. 310 mA
+5V Ripple and Noise
- approx.1 mV pp broadband on scope, 15 uV rms at switcher fundamental frequency (50 kHz) on spectrum analyzer

Warm-up and Temperature Sensitivities

Detected RF DDS output level power-on drift:

Detector offset voltage power-on drift:

Detected RF DDS output level temperature coefficient: -0.002 dB/°F after initial warm-up.
Detector offset temperature coefficient: -1.9 uV/°F after initial warm-up

The measurement examples at the beginning that showed correlation to simulation models and/or nominal component values as well as the Kay attenuator measurements in the Detector Performance Summary provide some indication of VNA measurement accuracy.

The following will present methodologies to quantify accuracy in a more general fashion for transmission, reflection, and group delay measurements with this VNA.

Transmission Accuracy

Transmission accuracy is difficult to determine without a specific understanding of the DUT in question. It also depends on:

Calibration technique and standards
Source and Load Match
Maximum usable DUT power
Linearity
Dynamic Range
Signal/Noise ratio (noise floor)
Averaging
Repeatability (connectors)
Drift (power-on and temperature)
Variability (cabling)
Analysis Method (RSS, Monte Carlo, or combination)

Armed with determinations for each of these, plus a calibration model, and an example DUT, a sample accuracy assessment will be made on what follows. The method presented here also permits a user to make accuracy estimates for other DUTs and parameter assumptions that may be of interest.

Calibration Technique: A modified response calibration is used where a Thru line is used to establish the unity gain at zero phase plus an open (or terminated) Detector RF input is used to establish the zero signal level.
Calibration Model. The following equations were derived for the modified response calibration used in this VNA

or equivalently

where

Gm is the measured complex voltage insertion gain,

S11 – S22 are the DUT S-parameters,

ΓS and ΓL are respectively the Source and Load Match of the VNA test ports at the DUT terminals.

SIN is the reflection coefficient at port 1 with ΓL terminating port 2.

Note that these are vector equations that permit angle error in Gm to be determined in addition to magnitude error. These equations show that Gm will approximate S21 of the DUT if ΓS and ΓL are both nearly zero, i.e. if the source and load impedance are both approx. 50 Ω. The equations also show that the DUT S-parameters also affect the degree of interaction or coupling due to matching errors at the VNA test ports.

Also critical to this analysis are assumptions regarding the rotation of error vectors. The standard assumption of arbitrary rotation to force worst-case additions or subtractions is valid for microwave frequencies, but possibly not at 50 kHz and into the lower HF range.

Since the source and load impedance are both approx. 50 Ω, Gm errors will be normalized to S21 in this example.

Analysis method: While Root Sum Square (RSS) is commonly used (see section 10 of this Keysight PDF VNA reference manual), an earlier Monte Carlo type statistical method (see B. P. Hand, “Developing Accuracy Specifications for Automatic Network Analyzer Systems,” Hewlett-Packard Journal, Feb. 1970) is used here. The Monte Carlo method allows the user to control the angles used for the various error vectors and also to determine the confidence level.
Averaging: None
Repeatability and Stability: Assumed negligible
Drift: Assumed negligible
Frequency: 10 MHz
DUT: Nominal 50 Ω 0-110 dB step attenuator with return losses exceeding 20 dB or 30 dB, 0 dB used as thru calibration standard, DUT is 5, 10, 20,…100, 110 dB
DUT input power: approx. +4 dBm
System dynamic range: 112 dB
Vectors
- ΓS: 0.054 @ -152° (measured with 2nd VNA)
- ΓL: 0.022 @ 82° (measured with 2nd VNA)
- S11: 0.10 or 0.032 @ 0 to 360°, uniformly distributed
- S21: magnitude per DUT attenuations above @ 0°
- S12 = S21
- S22: 0.10 or 0.032 @ 0 to 360°, uniformly distributed
Noise: Treated as a vector of constant magnitude with its phase as a random variable between 0 and 360° selected in the Monte Carlo algorithm. Its magnitude is scaled to S21 based on the DUT input power and the system dynamic range.
Gm Error with respect to S21
- Attenuator Return Loss = 20 dB

- Attenuator Return Loss = 30 dB

The errors seen here at 10 MHz will be larger at the 50 kHz and 60 MHz end frequency limits due to increased ΓS as seen in the RF DDS return loss plot. However, the error at the end frequencies can be reduced with the addition on the source side of either external pads or a pre-amp with an attenuator at its output.

More reflective devices, such as filters entering stopband, will also have greater Gm errors. Also, if the source and load match is degraded with external cabling or amplifiers, then the Gm error will again be larger.

Reflection Accuracy

Many of the dependencies listed for transmission accuracy also affect reflection accuracy. Reflection accuracy depends more critically on the quality and accuracy of the calibration

standards used. However, most of the other systematic errors, such as directivity. tracking and source and load match, are eliminated with the Open, Short, Load (OSL) calibration method that is used in this VNA.

With calibration standards of known accuracy, what is generally done is to supply the needed data to a calibration model and determine what are called “residual errors.” These residual or corrected errors are commonly quoted in a VNA specification.

Without purchased or NIST traceable calibration standards, that process described in a Keysight document 'Sensitivity Analysis of One-port Characterized Devices in Vector Network Analyzer Calibrations: Theory and Computational Analysis' is nearly impossible but can be pursued with appropriate standards.

Since calibration standards were not purchased nor were NIST traceable standards directly available, results of a correlation test with a commercial VNA with NIST traceable standards are presented here instead. Fortunately, this correlation activity also demonstrates that good quality SMA calibration standards can be constructed and used for the 0.05 – 60 MHz range. These calibration standards also have good accuracy through 1 GHz.

This activity was provided by me using my VNA and by Chip Owens, NW0O, using a commercial VNA. Chip’s data collection proved to be more time consuming than first anticipated. I am extremely grateful to Chip for the time and effort that he expended in collecting this data.

VNAs:
- Paul: N2PK VNA
- Chip Keysight/Agilent 8753C (this device is obsolete; as an alternative, see the 8753D datasheet).
Bridges:
- Paul: Wheatstone with a Mini-Circuits T1-1T transformer to VNA Detector
- Chip: Keysight/Agilent 85046A
Calibration technique: Open, Short, Load (OSL)
Calibration standards:
- Paul
  - Three Amphenol, PN 901-144-9RFX, SMA jacks with the center pin ground down flush with the dielectric at the back of the connector are used for each of the OSL calibration standards.
  - The Open is an SMA jack as above.
  - The Short is an SMA jack as above with a flat foil disk soldered to the center conductor and the entire periphery of the outer conductor and in contact with the teflon dielectric.
  - The 50 Ω load is an SMA jack as above with two 100 Ω, 0603, +/-0.1% resistors mounted diametrically opposed and each soldered to the center and outer conductors of the SMA and in contact with the teflon dielectric.
  - Very small amounts of Ambroid liquid cement were used to aid in mechanically securing the SMA center conductor on the Open and the resistors on the 50 Ω load.
- Chip
  - Agilent 85033C 3.5 mm cal kit. SMAs can be mated with 3.5 mm connectors.
DUT and its construction
- Series RC load on an Amphenol SMA jack same as my calibration standards construction. Consists of an 0805 SMD 24.9 Ω 1% resistor and two 0805 100 pf 5% NPO capacitors in parallel.
Method
- Paul: Used my calibration standards and measured DUT at spot frequencies of 1, 10, 20, …50, 60 MHz
- Chip: Used 85033C jack calibrations standards and measured my calibration standards and the DUT at the above spot frequencies plus higher frequencies through 1 GHz.
Source power at DUT
- Paul: 6 dB down from RF DDS level, or approx. -2 dBm up to 10 MHz dropping to –17 dBm at 60 MHz
- Chip: -23 dBm
Nominal reference plane locations
- Paul: The back of the SMA jack flush with the dielectric.
- Chip: Outer conductor mating surface on 3.5 mm connectors which nearly corresponds to the front of the SMA jack flush with the dielectric.
Reference plane offset
- Based on Chip’s 1 GHz measurement of my short, there is a 34.2 ps offset between our reference plane locations. This offset is used as needed to correct one or the other set to compare data at the same plane.
Chip’s data for my calibration standards
- Unfortunately, there were some erratic results during the test of my calibration standards that Chip later traced to a faulty cable in his VNA. Here are data that do not appear to have been affected:
- Open

F	\|rho\|	< rho	Corr. < rho
40	1.001	-1.05	-0.06
50	1.001	-1.28	-0.05
60	0.999	-1.58	-0.10
70	0.998	-1.87	-0.15
80	0.999	-2.06	-0.09
90	0.999	-2.29	-0.08
100	0.999	-2.62	-0.16
146	1.000	-3.81	-0.22
500	1.000	-13.05	-0.74
1000	1.000	-25.98	-1.36

The corrected angle data above in degrees accounts for the 34.2 ps offset in reference plane locations. It can be used to project an open fringing capacitance of 0.039 pF.

- Short

F	\|rho\|	< rho	Corr. < rho
40	0.998	178.90	179.88
50	0.997	178.70	179.93
60	0.998	178.40	179.88
70	0.998	178.20	179.92
80	0.998	177.90	179.87
90	0.997	177.70	179.92
146	0.998	176.38	179.98
500	0.997	167.67	179.98
1000	0.997	155.38	180.00

The 1 GHz angle data above was used to determine the 34.2 ps offset in reference plane locations and the corrected angles at the other frequencies as a result.

- 50 Ω load

F	Ret. Loss dB	< rho	Corr. < rho
30	62.8	119.5	120.3
40	68.2	167.4	168.3
50	62.1	131.1	132.4
60	64.9	164.2	165.7
70	67.2	-164.8	-163.1
80	62.8	167.7	169.7
90	59.5	163.6	165.8
100	62.4	158.3	160.8
146	60.7	134.0	137.5
500	51.0	94.4	106.7
1000	45.4	79.3	103.9

Chip also evaluated three other resistor configurations including 4x200-Ω and found the above to be the best for return loss through 1 GHz.

Common DUT data comparison:

Adjusting my reflection data to the front of the SMA jack to correspond to Chip’s reference plane results in:

F	\|rho\| Paul	\|rho\| Chip	\|rho\| delta	< rho deg Paul (cor)	< rho deg Chip	< rho deg delta
1	0.9961	0.9970	-0.0009	-7.15	-7.19	0.03
10	0.7641	0.7643	-0.0002	-60.82	-60.80	-0.02
20	0.5541	0.5537	0.0004	-94.70	-94.72	0.02
30	0.4575	0.4565	0.0010	-114.85	-115.07	0.22
40	0.4102	0.4107	-0.0005	-128.24	-128.27	0.03
50	0.3846	0.3838	0.0008	-137.72	-137.90	0.018
60	0.3695	0.3687	0.0008	-144.79	-144.90	0.11

and adjusting Chip’s reflection data to the back of the SMA jack to correspond to my reference plane location

F	Rs ohm Paul	Rs ohm Chip	Rs ohm delta	Cs pF Paul	Cs pF Chip	Cs pF delta
1	25.20	19.25	5.95	198.6	199.3	-0.7
10	24.98	24.97	0.01	199.2	199.1	0.1
20	24.96	24.97	-0.01	199.9	200.1	-0.2
30	24.97	24.98	-0.01	201.1	202.1	-1.0
40	24.98	24.95	0.03	202.9	202.9	0.0
50	24.98	25.00	-0.02	205.0	206.2	-1.2
60	24.97	25.00	-0.03	207.8	208.6	-0.8

Note that the difference in Rs at 1 MHz is mostly the result of a 0.0078 dB difference in return loss!

Correcting my Cs data using a stray Ls = 1.5 nH results in Cs’ = 198.9 +0.2 /-0.3 pF.

Correcting Chip’s Cs data using a stray Ls = 1.6 nH results in Cs’ = 199.2 +0.5/-0.4 pF.

Group Delay Accuracy

Generally, group delay accuracy depends on the rate of change of the transmission phase errors with frequency. While it is possible to use the transmission error methodology and apply it to two relatively close frequencies as typically used in a group delay calculation, the typical DUT of interest for group delay is a filter and the rate of change in phase error will depend on both its transmission and reflection dependencies on frequency which appear to be difficult to specify in any generally meaningful way.

Summary

This document described the specifications and the performance of the VNA constructed as described at HF Vector Network Analyzer - Theory of Operation

Tags: vector network analyzer, vna, n2pk