Codes are not from training but are copied from IDE Vivado 2023.1 /Vitis 2023.1 .
This blog is summarization and comparisons of Hardware Lab Training 2021.2 vs the latest version released on May 17, 2023 which I using, Vitis 2023.1/Vivado 2023.1. Also, lab exploration works done are mentioned.
Initially, I had written this blog as Blog 4 merged with Software Lab, and blog 3 initially written is moved to blog 5 as i m stuck in Computational fluid dynamics and finite element analysis of heatsink. I am also stuck in RTOS and elliptic curve and hyperelliptic curve cryptography/Galois Finite Field on Ultra96-v2G. This is taking some time.
So now Blog 4 which I had originally written is split in blog 3 and blog 4.
I have completed training Ultra96 Training Courses 2021.2 (Path to Programmable III) - Hardware. I liked videos as they were short and in these lessons I got what Ultra96V2 is. I really didn't wanted to go through long lessons. I passed short quiz exam with even scoring 100%. Though my board is on Ultra96, I even gave Minized short quiz exam, which also I passed without even going through minized videos based on Ultra96 training.
As I am using Vivado 2023.1 and there is also doubt among other qualified engineers whether the lab exercises and solutions which are provided with training material (Hardware) can be used with latest version Vivado 2023.1 or not. I have found differences in Vitis 2023.1/Vivado 2023.1 and training 2021.2. It takes extra time to figure out, and even there are changes in some base addresses (or these may be type/print error- dont know) etc. Still as I wanted to for the latest tool version, I used Vitis 2023.1/Vivado 2023.1.
Note : Some participants or readers thinking, they have only got Minized but Ultra96 have got so many things but all these JTAG (Ultra96 USB-to-JTAG/UART Pod AES-ACC-U96-JTAG ),SD, Click Mezzanine (96Boards Click Mezzanine Starter Kit AES-ACC-U96-ME-SK ) and power supply (96Boards 4A Supply AES-ACC-U96-4APWR ), are needed to do labs. But cables were not with Ultra96 which minized participants have got.
Hardware Lab: Training 2021.2 vs Vitis 2023.1/Vivado 2023.1
1. Lab1
In Vivado 2023.1, Zynq UltraScale+ MPSoC IP block is 3.5
In Vivado Training 2021.2, Zynq UltraScale+ MPSoC IP block is 3.2
2. Lab2 : Vivado 2023.1
1) In Vivado 2023.1, For UART1, I/O MIO is from MIO 0 .. 1 to MIO 72 .. 73 and also EMIO (extended MIO) but for lab, set to I/O set to MIO 0 .. 1.
UART1 MIO Connected can be seen by tick.
2) I/O Voltage for bank0 [ MIO 0 :25], bank1 [MIO 26 :51], bank2 [ MIO 52:77] and bank 3 is set to LVCMOS18, that is LVCMOS 1.8V . Page 5 of training says " set the I/O Voltage to LVCMOS 1.8V for all banks." but page 6 has error for bank3
3) Various clocks are set as per manual. Other details are mentioned in Research Paper, 'Synopsis of Current Consumption, PWM and DMA In Single Core, Dual Core and Multi Core Processors SoC'
4) From Blog of pandoramc " .... One of the first differences is the DRAM Bus Width.According to Vivado 2021.2, the LPDDR4 has a bus with of 32 bits while the manual only pictures the 16 bits width, for the DDR4 standard memory,.."
In vivado 2023.1, 16-bit LPDDR4 is in red. It has both options 16-bit and 32-bit if scrolled. In manual, it is not in red but black
5) What is the maximum speed the LPDDR4 interface can run at? Answer given in manual is 534 MHz but in settings of vivado 2023.1 and even on page 13, it is 533 MHz.
I dont why 1 MHz is less or print error.
6) Vivado log file
*** Running vivado
with args -log design2023_1_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design2023_1_wrapper.tcl
****** Vivado v2023.1 (64-bit)
**** SW Build 3865809 on Sun May 7 15:04:56 MDT 2023
**** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
**** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source design2023_1_wrapper.tcl -notrace
create_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2422.137 ; gain = 113.023 ; free physical = 3186 ; free virtual = 20924
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.1/data/ip'.
add_files: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2493.277 ; gain = 71.141 ; free physical = 3110 ; free virtual = 20850
Command: synth_design -top design2023_1_wrapper -part xczu3eg-sbva484-1-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Device 21-403] Loading part xczu3eg-sbva484-1-e
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 56189
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3599.492 ; gain = 254.832 ; free physical = 1749 ; free virtual = 19490
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'design2023_1_wrapper' [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/hdl/design2023_1_wrapper.vhd:18]
INFO: [Synth 8-3491] module 'design2023_1' declared at '/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/synth/design2023_1.vhd:15' bound to instance 'design2023_1_i' of component 'design2023_1' [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/hdl/design2023_1_wrapper.vhd:22]
INFO: [Synth 8-638] synthesizing module 'design2023_1' [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/synth/design2023_1.vhd:22]
INFO: [Synth 8-3491] module 'design2023_1_zynq_ultra_ps_e_0_0' declared at '/home/ab/Videos/amd_xilinx/project_1/synth_1/.Xil/Vivado-56092-ab06-X006X/realtime/design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl:6' bound to instance 'zynq_ultra_ps_e_0' of component 'design2023_1_zynq_ultra_ps_e_0_0' [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/synth/design2023_1.vhd:30]
INFO: [Synth 8-638] synthesizing module 'design2023_1_zynq_ultra_ps_e_0_0' [/home/ab/Videos/amd_xilinx/project_1/synth_1/.Xil/Vivado-56092-ab06-X006X/realtime/design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl:13]
INFO: [Synth 8-256] done synthesizing module 'design2023_1' (0#1) [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/synth/design2023_1.vhd:22]
INFO: [Synth 8-256] done synthesizing module 'design2023_1_wrapper' (0#1) [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/hdl/design2023_1_wrapper.vhd:18]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3665.430 ; gain = 320.770 ; free physical = 1662 ; free virtual = 19403
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3674.336 ; gain = 329.676 ; free physical = 1661 ; free virtual = 19402
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3674.336 ; gain = 329.676 ; free physical = 1661 ; free virtual = 19402
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3674.336 ; gain = 0.000 ; free physical = 1661 ; free virtual = 19402
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_in_context.xdc] for cell 'design2023_1_i/zynq_ultra_ps_e_0'
create_clock: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3715.258 ; gain = 0.000 ; free physical = 1635 ; free virtual = 19376
Finished Parsing XDC File [/home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_in_context.xdc] for cell 'design2023_1_i/zynq_ultra_ps_e_0'
Parsing XDC File [/home/ab/Videos/amd_xilinx/project_1/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/ab/Videos/amd_xilinx/project_1/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3715.258 ; gain = 0.000 ; free physical = 1635 ; free virtual = 19376
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3715.258 ; gain = 0.000 ; free physical = 1635 ; free virtual = 19376
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 3715.258 ; gain = 370.598 ; free physical = 1281 ; free virtual = 19110
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xczu3eg-sbva484-1-e
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 3715.258 ; gain = 370.598 ; free physical = 1281 ; free virtual = 19110
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for design2023_1_i. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for design2023_1_i/zynq_ultra_ps_e_0. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:58 ; elapsed = 00:01:01 . Memory (MB): peak = 3715.258 ; gain = 370.598 ; free physical = 1266 ; free virtual = 19096
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:58 ; elapsed = 00:01:01 . Memory (MB): peak = 3715.258 ; gain = 370.598 ; free physical = 1216 ; free virtual = 19064
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 360 (col length:72)
BRAMs: 432 (col length: RAMB18 72 RAMB36 36)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:03 ; elapsed = 00:01:06 . Memory (MB): peak = 3715.258 ; gain = 370.598 ; free physical = 1225 ; free virtual = 19096
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:35 ; elapsed = 00:01:45 . Memory (MB): peak = 4206.570 ; gain = 861.910 ; free physical = 577 ; free virtual = 18492
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:35 ; elapsed = 00:01:45 . Memory (MB): peak = 4206.570 ; gain = 861.910 ; free physical = 577 ; free virtual = 18492
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:35 ; elapsed = 00:01:45 . Memory (MB): peak = 4216.586 ; gain = 871.926 ; free physical = 568 ; free virtual = 18483
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:51 ; elapsed = 00:02:01 . Memory (MB): peak = 4230.461 ; gain = 885.801 ; free physical = 602 ; free virtual = 18485
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:51 ; elapsed = 00:02:01 . Memory (MB): peak = 4230.461 ; gain = 885.801 ; free physical = 602 ; free virtual = 18485
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:51 ; elapsed = 00:02:01 . Memory (MB): peak = 4230.461 ; gain = 885.801 ; free physical = 602 ; free virtual = 18485
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:51 ; elapsed = 00:02:01 . Memory (MB): peak = 4230.461 ; gain = 885.801 ; free physical = 602 ; free virtual = 18485
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:51 ; elapsed = 00:02:01 . Memory (MB): peak = 4230.461 ; gain = 885.801 ; free physical = 602 ; free virtual = 18485
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:51 ; elapsed = 00:02:01 . Memory (MB): peak = 4230.461 ; gain = 885.801 ; free physical = 602 ; free virtual = 18485
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+------+---------------------------------+----------+
| |BlackBox name |Instances |
+------+---------------------------------+----------+
|1 |design2023_1_zynq_ultra_ps_e_0_0 | 1|
+------+---------------------------------+----------+
Report Cell Usage:
+------+--------------------------------------+------+
| |Cell |Count |
+------+--------------------------------------+------+
|1 |design2023_1_zynq_ultra_ps_e_0_0_bbox | 1|
+------+--------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:51 ; elapsed = 00:02:01 . Memory (MB): peak = 4230.461 ; gain = 885.801 ; free physical = 602 ; free virtual = 18485
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:28 ; elapsed = 00:01:37 . Memory (MB): peak = 4230.461 ; gain = 844.879 ; free physical = 600 ; free virtual = 18481
Synthesis Optimization Complete : Time (s): cpu = 00:01:51 ; elapsed = 00:02:02 . Memory (MB): peak = 4230.469 ; gain = 885.801 ; free physical = 600 ; free virtual = 18481
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4230.469 ; gain = 0.000 ; free physical = 600 ; free virtual = 18483
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4263.180 ; gain = 0.000 ; free physical = 832 ; free virtual = 18726
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: 5de5c971
INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:14 ; elapsed = 00:02:20 . Memory (MB): peak = 4263.180 ; gain = 1769.902 ; free physical = 828 ; free virtual = 18724
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3765.697; main = 3478.201; forked = 362.381
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 5212.270; main = 4263.184; forked = 995.680
INFO: [Common 17-1381] The checkpoint '/home/ab/Videos/amd_xilinx/project_1/synth_1/design2023_1_wrapper.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file design2023_1_wrapper_utilization_synth.rpt -pb design2023_1_wrapper_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Jun 20 05:57:54 2023...
7) HDL Wrapper generated for Lab 2
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:zynq_ultra_ps_e:3.5
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design2023_1_zynq_ultra_ps_e_0_0 IS
PORT (
pl_clk0 : OUT STD_LOGIC
);
END design2023_1_zynq_ultra_ps_e_0_0;
ARCHITECTURE design2023_1_zynq_ultra_ps_e_0_0_arch OF design2023_1_zynq_ultra_ps_e_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design2023_1_zynq_ultra_ps_e_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zynq_ultra_ps_e_v3_5_0_zynq_ultra_ps_e IS
GENERIC (
C_DP_USE_AUDIO : INTEGER;
C_DP_USE_VIDEO : INTEGER;
C_MAXIGP0_DATA_WIDTH : INTEGER;
C_MAXIGP1_DATA_WIDTH : INTEGER;
C_MAXIGP2_DATA_WIDTH : INTEGER;
C_SAXIGP0_DATA_WIDTH : INTEGER;
C_SAXIGP1_DATA_WIDTH : INTEGER;
C_SAXIGP2_DATA_WIDTH : INTEGER;
C_SAXIGP3_DATA_WIDTH : INTEGER;
C_SAXIGP4_DATA_WIDTH : INTEGER;
C_SAXIGP5_DATA_WIDTH : INTEGER;
C_SAXIGP6_DATA_WIDTH : INTEGER;
C_USE_DIFF_RW_CLK_GP0 : INTEGER;
C_USE_DIFF_RW_CLK_GP1 : INTEGER;
C_USE_DIFF_RW_CLK_GP2 : INTEGER;
C_USE_DIFF_RW_CLK_GP3 : INTEGER;
C_USE_DIFF_RW_CLK_GP4 : INTEGER;
C_USE_DIFF_RW_CLK_GP5 : INTEGER;
C_USE_DIFF_RW_CLK_GP6 : INTEGER;
C_EN_FIFO_ENET0 : STRING;
C_EN_FIFO_ENET1 : STRING;
C_EN_FIFO_ENET2 : STRING;
C_EN_FIFO_ENET3 : STRING;
C_PL_CLK0_BUF : STRING;
C_PL_CLK1_BUF : STRING;
C_PL_CLK2_BUF : STRING;
C_PL_CLK3_BUF : STRING;
C_TRACE_PIPELINE_WIDTH : INTEGER;
C_EN_EMIO_TRACE : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_USE_DEBUG_TEST : INTEGER;
C_SD0_INTERNAL_BUS_WIDTH : INTEGER;
C_SD1_INTERNAL_BUS_WIDTH : INTEGER;
C_NUM_F2P_0_INTR_INPUTS : INTEGER;
C_NUM_F2P_1_INTR_INPUTS : INTEGER;
C_EMIO_GPIO_WIDTH : INTEGER;
C_NUM_FABRIC_RESETS : INTEGER
);
PORT (
maxihpm0_fpd_aclk : IN STD_LOGIC;
maxigp0_awid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp0_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
maxigp0_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
maxigp0_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp0_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp0_awlock : OUT STD_LOGIC;
maxigp0_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp0_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp0_awvalid : OUT STD_LOGIC;
maxigp0_awuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp0_awready : IN STD_LOGIC;
maxigp0_wdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
maxigp0_wstrb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp0_wlast : OUT STD_LOGIC;
maxigp0_wvalid : OUT STD_LOGIC;
maxigp0_wready : IN STD_LOGIC;
maxigp0_bid : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp0_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp0_bvalid : IN STD_LOGIC;
maxigp0_bready : OUT STD_LOGIC;
maxigp0_arid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp0_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
maxigp0_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
maxigp0_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp0_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp0_arlock : OUT STD_LOGIC;
maxigp0_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp0_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp0_arvalid : OUT STD_LOGIC;
maxigp0_aruser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp0_arready : IN STD_LOGIC;
maxigp0_rid : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp0_rdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
maxigp0_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp0_rlast : IN STD_LOGIC;
maxigp0_rvalid : IN STD_LOGIC;
maxigp0_rready : OUT STD_LOGIC;
maxigp0_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp0_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxihpm1_fpd_aclk : IN STD_LOGIC;
maxigp1_awid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp1_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
maxigp1_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
maxigp1_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp1_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp1_awlock : OUT STD_LOGIC;
maxigp1_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp1_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp1_awvalid : OUT STD_LOGIC;
maxigp1_awuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp1_awready : IN STD_LOGIC;
maxigp1_wdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
maxigp1_wstrb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp1_wlast : OUT STD_LOGIC;
maxigp1_wvalid : OUT STD_LOGIC;
maxigp1_wready : IN STD_LOGIC;
maxigp1_bid : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp1_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp1_bvalid : IN STD_LOGIC;
maxigp1_bready : OUT STD_LOGIC;
maxigp1_arid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp1_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
maxigp1_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
maxigp1_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp1_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp1_arlock : OUT STD_LOGIC;
maxigp1_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp1_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp1_arvalid : OUT STD_LOGIC;
maxigp1_aruser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp1_arready : IN STD_LOGIC;
maxigp1_rid : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp1_rdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
maxigp1_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp1_rlast : IN STD_LOGIC;
maxigp1_rvalid : IN STD_LOGIC;
maxigp1_rready : OUT STD_LOGIC;
maxigp1_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp1_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxihpm0_lpd_aclk : IN STD_LOGIC;
maxigp2_awid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp2_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
maxigp2_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
maxigp2_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp2_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp2_awlock : OUT STD_LOGIC;
maxigp2_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp2_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp2_awvalid : OUT STD_LOGIC;
maxigp2_awuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp2_awready : IN STD_LOGIC;
maxigp2_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
maxigp2_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp2_wlast : OUT STD_LOGIC;
maxigp2_wvalid : OUT STD_LOGIC;
maxigp2_wready : IN STD_LOGIC;
maxigp2_bid : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp2_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp2_bvalid : IN STD_LOGIC;
maxigp2_bready : OUT STD_LOGIC;
maxigp2_arid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp2_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
maxigp2_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
maxigp2_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp2_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp2_arlock : OUT STD_LOGIC;
maxigp2_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp2_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
maxigp2_arvalid : OUT STD_LOGIC;
maxigp2_aruser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp2_arready : IN STD_LOGIC;
maxigp2_rid : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
maxigp2_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
maxigp2_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
maxigp2_rlast : IN STD_LOGIC;
maxigp2_rvalid : IN STD_LOGIC;
maxigp2_rready : OUT STD_LOGIC;
maxigp2_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
maxigp2_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxihpc0_fpd_rclk : IN STD_LOGIC;
saxihpc0_fpd_wclk : IN STD_LOGIC;
saxihpc0_fpd_aclk : IN STD_LOGIC;
saxigp0_aruser : IN STD_LOGIC;
saxigp0_awuser : IN STD_LOGIC;
saxigp0_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp0_awaddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp0_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp0_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp0_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp0_awlock : IN STD_LOGIC;
saxigp0_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp0_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp0_awvalid : IN STD_LOGIC;
saxigp0_awready : OUT STD_LOGIC;
saxigp0_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp0_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxigp0_wlast : IN STD_LOGIC;
saxigp0_wvalid : IN STD_LOGIC;
saxigp0_wready : OUT STD_LOGIC;
saxigp0_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp0_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ddrc_ext_refresh_rank0_req : IN STD_LOGIC;
ddrc_ext_refresh_rank1_req : IN STD_LOGIC;
ddrc_refresh_pl_clk : IN STD_LOGIC;
saxigp0_bvalid : OUT STD_LOGIC;
saxigp0_bready : IN STD_LOGIC;
saxigp0_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp0_araddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp0_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp0_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp0_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp0_arlock : IN STD_LOGIC;
saxigp0_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp0_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp0_arvalid : IN STD_LOGIC;
saxigp0_arready : OUT STD_LOGIC;
saxigp0_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp0_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp0_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp0_rlast : OUT STD_LOGIC;
saxigp0_rvalid : OUT STD_LOGIC;
saxigp0_rready : IN STD_LOGIC;
saxigp0_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp0_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp0_rcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp0_wcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp0_racount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp0_wacount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxihpc1_fpd_rclk : IN STD_LOGIC;
saxihpc1_fpd_wclk : IN STD_LOGIC;
saxihpc1_fpd_aclk : IN STD_LOGIC;
saxigp1_aruser : IN STD_LOGIC;
saxigp1_awuser : IN STD_LOGIC;
saxigp1_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp1_awaddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp1_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp1_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp1_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp1_awlock : IN STD_LOGIC;
saxigp1_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp1_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp1_awvalid : IN STD_LOGIC;
saxigp1_awready : OUT STD_LOGIC;
saxigp1_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp1_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxigp1_wlast : IN STD_LOGIC;
saxigp1_wvalid : IN STD_LOGIC;
saxigp1_wready : OUT STD_LOGIC;
saxigp1_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp1_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp1_bvalid : OUT STD_LOGIC;
saxigp1_bready : IN STD_LOGIC;
saxigp1_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp1_araddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp1_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp1_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp1_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp1_arlock : IN STD_LOGIC;
saxigp1_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp1_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp1_arvalid : IN STD_LOGIC;
saxigp1_arready : OUT STD_LOGIC;
saxigp1_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp1_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp1_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp1_rlast : OUT STD_LOGIC;
saxigp1_rvalid : OUT STD_LOGIC;
saxigp1_rready : IN STD_LOGIC;
saxigp1_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp1_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp1_rcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp1_wcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp1_racount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp1_wacount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxihp0_fpd_rclk : IN STD_LOGIC;
saxihp0_fpd_wclk : IN STD_LOGIC;
saxihp0_fpd_aclk : IN STD_LOGIC;
saxigp2_aruser : IN STD_LOGIC;
saxigp2_awuser : IN STD_LOGIC;
saxigp2_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp2_awaddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp2_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp2_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp2_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp2_awlock : IN STD_LOGIC;
saxigp2_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp2_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp2_awvalid : IN STD_LOGIC;
saxigp2_awready : OUT STD_LOGIC;
saxigp2_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp2_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxigp2_wlast : IN STD_LOGIC;
saxigp2_wvalid : IN STD_LOGIC;
saxigp2_wready : OUT STD_LOGIC;
saxigp2_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp2_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp2_bvalid : OUT STD_LOGIC;
saxigp2_bready : IN STD_LOGIC;
saxigp2_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp2_araddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp2_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp2_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp2_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp2_arlock : IN STD_LOGIC;
saxigp2_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp2_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp2_arvalid : IN STD_LOGIC;
saxigp2_arready : OUT STD_LOGIC;
saxigp2_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp2_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp2_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp2_rlast : OUT STD_LOGIC;
saxigp2_rvalid : OUT STD_LOGIC;
saxigp2_rready : IN STD_LOGIC;
saxigp2_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp2_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp2_rcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp2_wcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp2_racount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp2_wacount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxihp1_fpd_rclk : IN STD_LOGIC;
saxihp1_fpd_wclk : IN STD_LOGIC;
saxihp1_fpd_aclk : IN STD_LOGIC;
saxigp3_aruser : IN STD_LOGIC;
saxigp3_awuser : IN STD_LOGIC;
saxigp3_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp3_awaddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp3_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp3_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp3_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp3_awlock : IN STD_LOGIC;
saxigp3_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp3_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp3_awvalid : IN STD_LOGIC;
saxigp3_awready : OUT STD_LOGIC;
saxigp3_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp3_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxigp3_wlast : IN STD_LOGIC;
saxigp3_wvalid : IN STD_LOGIC;
saxigp3_wready : OUT STD_LOGIC;
saxigp3_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp3_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp3_bvalid : OUT STD_LOGIC;
saxigp3_bready : IN STD_LOGIC;
saxigp3_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp3_araddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp3_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp3_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp3_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp3_arlock : IN STD_LOGIC;
saxigp3_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp3_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp3_arvalid : IN STD_LOGIC;
saxigp3_arready : OUT STD_LOGIC;
saxigp3_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp3_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp3_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp3_rlast : OUT STD_LOGIC;
saxigp3_rvalid : OUT STD_LOGIC;
saxigp3_rready : IN STD_LOGIC;
saxigp3_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp3_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp3_rcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp3_wcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp3_racount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp3_wacount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxihp2_fpd_rclk : IN STD_LOGIC;
saxihp2_fpd_wclk : IN STD_LOGIC;
saxihp2_fpd_aclk : IN STD_LOGIC;
saxigp4_aruser : IN STD_LOGIC;
saxigp4_awuser : IN STD_LOGIC;
saxigp4_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp4_awaddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp4_awlock : IN STD_LOGIC;
saxigp4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp4_awvalid : IN STD_LOGIC;
saxigp4_awready : OUT STD_LOGIC;
saxigp4_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp4_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxigp4_wlast : IN STD_LOGIC;
saxigp4_wvalid : IN STD_LOGIC;
saxigp4_wready : OUT STD_LOGIC;
saxigp4_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp4_bvalid : OUT STD_LOGIC;
saxigp4_bready : IN STD_LOGIC;
saxigp4_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp4_araddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp4_arlock : IN STD_LOGIC;
saxigp4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp4_arvalid : IN STD_LOGIC;
saxigp4_arready : OUT STD_LOGIC;
saxigp4_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp4_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp4_rlast : OUT STD_LOGIC;
saxigp4_rvalid : OUT STD_LOGIC;
saxigp4_rready : IN STD_LOGIC;
saxigp4_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp4_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp4_rcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp4_wcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp4_racount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp4_wacount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxihp3_fpd_rclk : IN STD_LOGIC;
saxihp3_fpd_wclk : IN STD_LOGIC;
saxihp3_fpd_aclk : IN STD_LOGIC;
saxigp5_aruser : IN STD_LOGIC;
saxigp5_awuser : IN STD_LOGIC;
saxigp5_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp5_awaddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp5_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp5_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp5_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp5_awlock : IN STD_LOGIC;
saxigp5_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp5_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp5_awvalid : IN STD_LOGIC;
saxigp5_awready : OUT STD_LOGIC;
saxigp5_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp5_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxigp5_wlast : IN STD_LOGIC;
saxigp5_wvalid : IN STD_LOGIC;
saxigp5_wready : OUT STD_LOGIC;
saxigp5_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp5_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp5_bvalid : OUT STD_LOGIC;
saxigp5_bready : IN STD_LOGIC;
saxigp5_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp5_araddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp5_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp5_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp5_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp5_arlock : IN STD_LOGIC;
saxigp5_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp5_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp5_arvalid : IN STD_LOGIC;
saxigp5_arready : OUT STD_LOGIC;
saxigp5_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp5_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp5_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp5_rlast : OUT STD_LOGIC;
saxigp5_rvalid : OUT STD_LOGIC;
saxigp5_rready : IN STD_LOGIC;
saxigp5_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp5_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp5_rcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp5_wcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp5_racount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp5_wacount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxi_lpd_rclk : IN STD_LOGIC;
saxi_lpd_wclk : IN STD_LOGIC;
saxi_lpd_aclk : IN STD_LOGIC;
saxigp6_aruser : IN STD_LOGIC;
saxigp6_awuser : IN STD_LOGIC;
saxigp6_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp6_awaddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp6_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp6_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp6_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp6_awlock : IN STD_LOGIC;
saxigp6_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp6_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp6_awvalid : IN STD_LOGIC;
saxigp6_awready : OUT STD_LOGIC;
saxigp6_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp6_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxigp6_wlast : IN STD_LOGIC;
saxigp6_wvalid : IN STD_LOGIC;
saxigp6_wready : OUT STD_LOGIC;
saxigp6_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp6_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp6_bvalid : OUT STD_LOGIC;
saxigp6_bready : IN STD_LOGIC;
saxigp6_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp6_araddr : IN STD_LOGIC_VECTOR(48 DOWNTO 0);
saxigp6_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp6_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp6_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp6_arlock : IN STD_LOGIC;
saxigp6_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp6_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxigp6_arvalid : IN STD_LOGIC;
saxigp6_arready : OUT STD_LOGIC;
saxigp6_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
saxigp6_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxigp6_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxigp6_rlast : OUT STD_LOGIC;
saxigp6_rvalid : OUT STD_LOGIC;
saxigp6_rready : IN STD_LOGIC;
saxigp6_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp6_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp6_rcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp6_wcount : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
saxigp6_racount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxigp6_wacount : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
saxiacp_fpd_aclk : IN STD_LOGIC;
saxiacp_awuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxiacp_aruser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxiacp_awid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
saxiacp_awaddr : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
saxiacp_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxiacp_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxiacp_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxiacp_awlock : IN STD_LOGIC;
saxiacp_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxiacp_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxiacp_awvalid : IN STD_LOGIC;
saxiacp_awready : OUT STD_LOGIC;
saxiacp_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
saxiacp_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
saxiacp_wlast : IN STD_LOGIC;
saxiacp_wvalid : IN STD_LOGIC;
saxiacp_wready : OUT STD_LOGIC;
saxiacp_bid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
saxiacp_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxiacp_bvalid : OUT STD_LOGIC;
saxiacp_bready : IN STD_LOGIC;
saxiacp_arid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
saxiacp_araddr : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
saxiacp_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saxiacp_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxiacp_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
saxiacp_arlock : IN STD_LOGIC;
saxiacp_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxiacp_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
saxiacp_arvalid : IN STD_LOGIC;
saxiacp_arready : OUT STD_LOGIC;
saxiacp_rid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
saxiacp_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
saxiacp_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
saxiacp_rlast : OUT STD_LOGIC;
saxiacp_rvalid : OUT STD_LOGIC;
saxiacp_rready : IN STD_LOGIC;
saxiacp_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
saxiacp_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_aclk : IN STD_LOGIC;
sacefpd_wuser : IN STD_LOGIC;
sacefpd_buser : OUT STD_LOGIC;
sacefpd_ruser : OUT STD_LOGIC;
sacefpd_awuser : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sacefpd_awsnoop : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
sacefpd_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
sacefpd_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
sacefpd_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sacefpd_awid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
sacefpd_awdomain : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sacefpd_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sacefpd_awbar : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sacefpd_awaddr : IN STD_LOGIC_VECTOR(43 DOWNTO 0);
sacefpd_awlock : IN STD_LOGIC;
sacefpd_awvalid : IN STD_LOGIC;
sacefpd_awready : OUT STD_LOGIC;
sacefpd_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sacefpd_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
sacefpd_wlast : IN STD_LOGIC;
sacefpd_wvalid : IN STD_LOGIC;
sacefpd_wready : OUT STD_LOGIC;
sacefpd_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sacefpd_bid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
sacefpd_bvalid : OUT STD_LOGIC;
sacefpd_bready : IN STD_LOGIC;
sacefpd_aruser : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sacefpd_arsnoop : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
sacefpd_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
sacefpd_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sacefpd_arid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
sacefpd_ardomain : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sacefpd_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sacefpd_arbar : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sacefpd_araddr : IN STD_LOGIC_VECTOR(43 DOWNTO 0);
sacefpd_arlock : IN STD_LOGIC;
sacefpd_arvalid : IN STD_LOGIC;
sacefpd_arready : OUT STD_LOGIC;
sacefpd_rresp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_rid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
sacefpd_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
sacefpd_rlast : OUT STD_LOGIC;
sacefpd_rvalid : OUT STD_LOGIC;
sacefpd_rready : IN STD_LOGIC;
sacefpd_acsnoop : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sacefpd_acprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
sacefpd_acaddr : OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
sacefpd_acvalid : OUT STD_LOGIC;
sacefpd_acready : IN STD_LOGIC;
sacefpd_cddata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
sacefpd_cdlast : IN STD_LOGIC;
sacefpd_cdvalid : IN STD_LOGIC;
sacefpd_cdready : OUT STD_LOGIC;
sacefpd_crresp : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sacefpd_crvalid : IN STD_LOGIC;
sacefpd_crready : OUT STD_LOGIC;
sacefpd_wack : IN STD_LOGIC;
sacefpd_rack : IN STD_LOGIC;
emio_can0_phy_tx : OUT STD_LOGIC;
emio_can0_phy_rx : IN STD_LOGIC;
emio_can1_phy_tx : OUT STD_LOGIC;
emio_can1_phy_rx : IN STD_LOGIC;
emio_enet0_gmii_rx_clk : IN STD_LOGIC;
emio_enet0_speed_mode : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_enet0_gmii_crs : IN STD_LOGIC;
emio_enet0_gmii_col : IN STD_LOGIC;
emio_enet0_gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet0_gmii_rx_er : IN STD_LOGIC;
emio_enet0_gmii_rx_dv : IN STD_LOGIC;
emio_enet0_gmii_tx_clk : IN STD_LOGIC;
emio_enet0_gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet0_gmii_tx_en : OUT STD_LOGIC;
emio_enet0_gmii_tx_er : OUT STD_LOGIC;
emio_enet0_mdio_mdc : OUT STD_LOGIC;
emio_enet0_mdio_i : IN STD_LOGIC;
emio_enet0_mdio_o : OUT STD_LOGIC;
emio_enet0_mdio_t : OUT STD_LOGIC;
emio_enet1_gmii_rx_clk : IN STD_LOGIC;
emio_enet1_speed_mode : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_enet1_gmii_crs : IN STD_LOGIC;
emio_enet1_gmii_col : IN STD_LOGIC;
emio_enet1_gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet1_gmii_rx_er : IN STD_LOGIC;
emio_enet1_gmii_rx_dv : IN STD_LOGIC;
emio_enet1_gmii_tx_clk : IN STD_LOGIC;
emio_enet1_gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet1_gmii_tx_en : OUT STD_LOGIC;
emio_enet1_gmii_tx_er : OUT STD_LOGIC;
emio_enet1_mdio_mdc : OUT STD_LOGIC;
emio_enet1_mdio_i : IN STD_LOGIC;
emio_enet1_mdio_o : OUT STD_LOGIC;
emio_enet1_mdio_t : OUT STD_LOGIC;
emio_enet2_gmii_rx_clk : IN STD_LOGIC;
emio_enet2_speed_mode : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_enet2_gmii_crs : IN STD_LOGIC;
emio_enet2_gmii_col : IN STD_LOGIC;
emio_enet2_gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet2_gmii_rx_er : IN STD_LOGIC;
emio_enet2_gmii_rx_dv : IN STD_LOGIC;
emio_enet2_gmii_tx_clk : IN STD_LOGIC;
emio_enet2_gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet2_gmii_tx_en : OUT STD_LOGIC;
emio_enet2_gmii_tx_er : OUT STD_LOGIC;
emio_enet2_mdio_mdc : OUT STD_LOGIC;
emio_enet2_mdio_i : IN STD_LOGIC;
emio_enet2_mdio_o : OUT STD_LOGIC;
emio_enet2_mdio_t : OUT STD_LOGIC;
emio_enet3_gmii_rx_clk : IN STD_LOGIC;
emio_enet3_speed_mode : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_enet3_gmii_crs : IN STD_LOGIC;
emio_enet3_gmii_col : IN STD_LOGIC;
emio_enet3_gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet3_gmii_rx_er : IN STD_LOGIC;
emio_enet3_gmii_rx_dv : IN STD_LOGIC;
emio_enet3_gmii_tx_clk : IN STD_LOGIC;
emio_enet3_gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet3_gmii_tx_en : OUT STD_LOGIC;
emio_enet3_gmii_tx_er : OUT STD_LOGIC;
emio_enet3_mdio_mdc : OUT STD_LOGIC;
emio_enet3_mdio_i : IN STD_LOGIC;
emio_enet3_mdio_o : OUT STD_LOGIC;
emio_enet3_mdio_t : OUT STD_LOGIC;
emio_enet0_tx_r_data_rdy : IN STD_LOGIC;
emio_enet0_tx_r_rd : OUT STD_LOGIC;
emio_enet0_tx_r_valid : IN STD_LOGIC;
emio_enet0_tx_r_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet0_tx_r_sop : IN STD_LOGIC;
emio_enet0_tx_r_eop : IN STD_LOGIC;
emio_enet0_tx_r_err : IN STD_LOGIC;
emio_enet0_tx_r_underflow : IN STD_LOGIC;
emio_enet0_tx_r_flushed : IN STD_LOGIC;
emio_enet0_tx_r_control : IN STD_LOGIC;
emio_enet0_dma_tx_end_tog : OUT STD_LOGIC;
emio_enet0_dma_tx_status_tog : IN STD_LOGIC;
emio_enet0_tx_r_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
emio_enet0_rx_w_wr : OUT STD_LOGIC;
emio_enet0_rx_w_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet0_rx_w_sop : OUT STD_LOGIC;
emio_enet0_rx_w_eop : OUT STD_LOGIC;
emio_enet0_rx_w_status : OUT STD_LOGIC_VECTOR(44 DOWNTO 0);
emio_enet0_rx_w_err : OUT STD_LOGIC;
emio_enet0_rx_w_overflow : IN STD_LOGIC;
emio_enet0_rx_w_flush : OUT STD_LOGIC;
emio_enet0_tx_r_fixed_lat : OUT STD_LOGIC;
fmio_gem0_fifo_tx_clk_to_pl_bufg : OUT STD_LOGIC;
fmio_gem0_fifo_rx_clk_to_pl_bufg : OUT STD_LOGIC;
emio_enet1_tx_r_data_rdy : IN STD_LOGIC;
emio_enet1_tx_r_rd : OUT STD_LOGIC;
emio_enet1_tx_r_valid : IN STD_LOGIC;
emio_enet1_tx_r_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet1_tx_r_sop : IN STD_LOGIC;
emio_enet1_tx_r_eop : IN STD_LOGIC;
emio_enet1_tx_r_err : IN STD_LOGIC;
emio_enet1_tx_r_underflow : IN STD_LOGIC;
emio_enet1_tx_r_flushed : IN STD_LOGIC;
emio_enet1_tx_r_control : IN STD_LOGIC;
emio_enet1_dma_tx_end_tog : OUT STD_LOGIC;
emio_enet1_dma_tx_status_tog : IN STD_LOGIC;
emio_enet1_tx_r_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
emio_enet1_rx_w_wr : OUT STD_LOGIC;
emio_enet1_rx_w_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet1_rx_w_sop : OUT STD_LOGIC;
emio_enet1_rx_w_eop : OUT STD_LOGIC;
emio_enet1_rx_w_status : OUT STD_LOGIC_VECTOR(44 DOWNTO 0);
emio_enet1_rx_w_err : OUT STD_LOGIC;
emio_enet1_rx_w_overflow : IN STD_LOGIC;
emio_enet1_rx_w_flush : OUT STD_LOGIC;
emio_enet1_tx_r_fixed_lat : OUT STD_LOGIC;
fmio_gem1_fifo_tx_clk_to_pl_bufg : OUT STD_LOGIC;
fmio_gem1_fifo_rx_clk_to_pl_bufg : OUT STD_LOGIC;
emio_enet2_tx_r_data_rdy : IN STD_LOGIC;
emio_enet2_tx_r_rd : OUT STD_LOGIC;
emio_enet2_tx_r_valid : IN STD_LOGIC;
emio_enet2_tx_r_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet2_tx_r_sop : IN STD_LOGIC;
emio_enet2_tx_r_eop : IN STD_LOGIC;
emio_enet2_tx_r_err : IN STD_LOGIC;
emio_enet2_tx_r_underflow : IN STD_LOGIC;
emio_enet2_tx_r_flushed : IN STD_LOGIC;
emio_enet2_tx_r_control : IN STD_LOGIC;
emio_enet2_dma_tx_end_tog : OUT STD_LOGIC;
emio_enet2_dma_tx_status_tog : IN STD_LOGIC;
emio_enet2_tx_r_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
emio_enet2_rx_w_wr : OUT STD_LOGIC;
emio_enet2_rx_w_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet2_rx_w_sop : OUT STD_LOGIC;
emio_enet2_rx_w_eop : OUT STD_LOGIC;
emio_enet2_rx_w_status : OUT STD_LOGIC_VECTOR(44 DOWNTO 0);
emio_enet2_rx_w_err : OUT STD_LOGIC;
emio_enet2_rx_w_overflow : IN STD_LOGIC;
emio_enet2_rx_w_flush : OUT STD_LOGIC;
emio_enet2_tx_r_fixed_lat : OUT STD_LOGIC;
fmio_gem2_fifo_tx_clk_to_pl_bufg : OUT STD_LOGIC;
fmio_gem2_fifo_rx_clk_to_pl_bufg : OUT STD_LOGIC;
emio_enet3_tx_r_data_rdy : IN STD_LOGIC;
emio_enet3_tx_r_rd : OUT STD_LOGIC;
emio_enet3_tx_r_valid : IN STD_LOGIC;
emio_enet3_tx_r_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet3_tx_r_sop : IN STD_LOGIC;
emio_enet3_tx_r_eop : IN STD_LOGIC;
emio_enet3_tx_r_err : IN STD_LOGIC;
emio_enet3_tx_r_underflow : IN STD_LOGIC;
emio_enet3_tx_r_flushed : IN STD_LOGIC;
emio_enet3_tx_r_control : IN STD_LOGIC;
emio_enet3_dma_tx_end_tog : OUT STD_LOGIC;
emio_enet3_dma_tx_status_tog : IN STD_LOGIC;
emio_enet3_tx_r_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
emio_enet3_rx_w_wr : OUT STD_LOGIC;
emio_enet3_rx_w_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
emio_enet3_rx_w_sop : OUT STD_LOGIC;
emio_enet3_rx_w_eop : OUT STD_LOGIC;
emio_enet3_rx_w_status : OUT STD_LOGIC_VECTOR(44 DOWNTO 0);
emio_enet3_rx_w_err : OUT STD_LOGIC;
emio_enet3_rx_w_overflow : IN STD_LOGIC;
emio_enet3_rx_w_flush : OUT STD_LOGIC;
emio_enet3_tx_r_fixed_lat : OUT STD_LOGIC;
fmio_gem3_fifo_tx_clk_to_pl_bufg : OUT STD_LOGIC;
fmio_gem3_fifo_rx_clk_to_pl_bufg : OUT STD_LOGIC;
emio_enet0_tx_sof : OUT STD_LOGIC;
emio_enet0_sync_frame_tx : OUT STD_LOGIC;
emio_enet0_delay_req_tx : OUT STD_LOGIC;
emio_enet0_pdelay_req_tx : OUT STD_LOGIC;
emio_enet0_pdelay_resp_tx : OUT STD_LOGIC;
emio_enet0_rx_sof : OUT STD_LOGIC;
emio_enet0_sync_frame_rx : OUT STD_LOGIC;
emio_enet0_delay_req_rx : OUT STD_LOGIC;
emio_enet0_pdelay_req_rx : OUT STD_LOGIC;
emio_enet0_pdelay_resp_rx : OUT STD_LOGIC;
emio_enet0_tsu_inc_ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_enet0_tsu_timer_cmp_val : OUT STD_LOGIC;
emio_enet1_tx_sof : OUT STD_LOGIC;
emio_enet1_sync_frame_tx : OUT STD_LOGIC;
emio_enet1_delay_req_tx : OUT STD_LOGIC;
emio_enet1_pdelay_req_tx : OUT STD_LOGIC;
emio_enet1_pdelay_resp_tx : OUT STD_LOGIC;
emio_enet1_rx_sof : OUT STD_LOGIC;
emio_enet1_sync_frame_rx : OUT STD_LOGIC;
emio_enet1_delay_req_rx : OUT STD_LOGIC;
emio_enet1_pdelay_req_rx : OUT STD_LOGIC;
emio_enet1_pdelay_resp_rx : OUT STD_LOGIC;
emio_enet1_tsu_inc_ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_enet1_tsu_timer_cmp_val : OUT STD_LOGIC;
emio_enet2_tx_sof : OUT STD_LOGIC;
emio_enet2_sync_frame_tx : OUT STD_LOGIC;
emio_enet2_delay_req_tx : OUT STD_LOGIC;
emio_enet2_pdelay_req_tx : OUT STD_LOGIC;
emio_enet2_pdelay_resp_tx : OUT STD_LOGIC;
emio_enet2_rx_sof : OUT STD_LOGIC;
emio_enet2_sync_frame_rx : OUT STD_LOGIC;
emio_enet2_delay_req_rx : OUT STD_LOGIC;
emio_enet2_pdelay_req_rx : OUT STD_LOGIC;
emio_enet2_pdelay_resp_rx : OUT STD_LOGIC;
emio_enet2_tsu_inc_ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_enet2_tsu_timer_cmp_val : OUT STD_LOGIC;
emio_enet3_tx_sof : OUT STD_LOGIC;
emio_enet3_sync_frame_tx : OUT STD_LOGIC;
emio_enet3_delay_req_tx : OUT STD_LOGIC;
emio_enet3_pdelay_req_tx : OUT STD_LOGIC;
emio_enet3_pdelay_resp_tx : OUT STD_LOGIC;
emio_enet3_rx_sof : OUT STD_LOGIC;
emio_enet3_sync_frame_rx : OUT STD_LOGIC;
emio_enet3_delay_req_rx : OUT STD_LOGIC;
emio_enet3_pdelay_req_rx : OUT STD_LOGIC;
emio_enet3_pdelay_resp_rx : OUT STD_LOGIC;
emio_enet3_tsu_inc_ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_enet3_tsu_timer_cmp_val : OUT STD_LOGIC;
fmio_gem_tsu_clk_to_pl_bufg : OUT STD_LOGIC;
fmio_gem_tsu_clk_from_pl : IN STD_LOGIC;
emio_enet_tsu_clk : IN STD_LOGIC;
emio_enet0_enet_tsu_timer_cnt : OUT STD_LOGIC_VECTOR(93 DOWNTO 0);
emio_enet0_ext_int_in : IN STD_LOGIC;
emio_enet1_ext_int_in : IN STD_LOGIC;
emio_enet2_ext_int_in : IN STD_LOGIC;
emio_enet3_ext_int_in : IN STD_LOGIC;
emio_enet0_dma_bus_width : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_enet1_dma_bus_width : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_enet2_dma_bus_width : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_enet3_dma_bus_width : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
emio_gpio_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
emio_gpio_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
emio_gpio_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
emio_i2c0_scl_i : IN STD_LOGIC;
emio_i2c0_scl_o : OUT STD_LOGIC;
emio_i2c0_scl_t : OUT STD_LOGIC;
emio_i2c0_sda_i : IN STD_LOGIC;
emio_i2c0_sda_o : OUT STD_LOGIC;
emio_i2c0_sda_t : OUT STD_LOGIC;
emio_i2c1_scl_i : IN STD_LOGIC;
emio_i2c1_scl_o : OUT STD_LOGIC;
emio_i2c1_scl_t : OUT STD_LOGIC;
emio_i2c1_sda_i : IN STD_LOGIC;
emio_i2c1_sda_o : OUT STD_LOGIC;
emio_i2c1_sda_t : OUT STD_LOGIC;
emio_uart0_txd : OUT STD_LOGIC;
emio_uart0_rxd : IN STD_LOGIC;
emio_uart0_ctsn : IN STD_LOGIC;
emio_uart0_rtsn : OUT STD_LOGIC;
emio_uart0_dsrn : IN STD_LOGIC;
emio_uart0_dcdn : IN STD_LOGIC;
emio_uart0_rin : IN STD_LOGIC;
emio_uart0_dtrn : OUT STD_LOGIC;
emio_uart1_txd : OUT STD_LOGIC;
emio_uart1_rxd : IN STD_LOGIC;
emio_uart1_ctsn : IN STD_LOGIC;
emio_uart1_rtsn : OUT STD_LOGIC;
emio_uart1_dsrn : IN STD_LOGIC;
emio_uart1_dcdn : IN STD_LOGIC;
emio_uart1_rin : IN STD_LOGIC;
emio_uart1_dtrn : OUT STD_LOGIC;
emio_sdio0_clkout : OUT STD_LOGIC;
emio_sdio0_fb_clk_in : IN STD_LOGIC;
emio_sdio0_cmdout : OUT STD_LOGIC;
emio_sdio0_cmdin : IN STD_LOGIC;
emio_sdio0_cmdena : OUT STD_LOGIC;
emio_sdio0_datain : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
emio_sdio0_dataout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
emio_sdio0_dataena : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
emio_sdio0_cd_n : IN STD_LOGIC;
emio_sdio0_wp : IN STD_LOGIC;
emio_sdio0_ledcontrol : OUT STD_LOGIC;
emio_sdio0_buspower : OUT STD_LOGIC;
emio_sdio0_bus_volt : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_sdio1_clkout : OUT STD_LOGIC;
emio_sdio1_fb_clk_in : IN STD_LOGIC;
emio_sdio1_cmdout : OUT STD_LOGIC;
emio_sdio1_cmdin : IN STD_LOGIC;
emio_sdio1_cmdena : OUT STD_LOGIC;
emio_sdio1_datain : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
emio_sdio1_dataout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
emio_sdio1_dataena : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
emio_sdio1_cd_n : IN STD_LOGIC;
emio_sdio1_wp : IN STD_LOGIC;
emio_sdio1_ledcontrol : OUT STD_LOGIC;
emio_sdio1_buspower : OUT STD_LOGIC;
emio_sdio1_bus_volt : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_spi0_sclk_i : IN STD_LOGIC;
emio_spi0_sclk_o : OUT STD_LOGIC;
emio_spi0_sclk_t : OUT STD_LOGIC;
emio_spi0_m_i : IN STD_LOGIC;
emio_spi0_m_o : OUT STD_LOGIC;
emio_spi0_mo_t : OUT STD_LOGIC;
emio_spi0_s_i : IN STD_LOGIC;
emio_spi0_s_o : OUT STD_LOGIC;
emio_spi0_so_t : OUT STD_LOGIC;
emio_spi0_ss_i_n : IN STD_LOGIC;
emio_spi0_ss_o_n : OUT STD_LOGIC;
emio_spi0_ss1_o_n : OUT STD_LOGIC;
emio_spi0_ss2_o_n : OUT STD_LOGIC;
emio_spi0_ss_n_t : OUT STD_LOGIC;
emio_spi1_sclk_i : IN STD_LOGIC;
emio_spi1_sclk_o : OUT STD_LOGIC;
emio_spi1_sclk_t : OUT STD_LOGIC;
emio_spi1_m_i : IN STD_LOGIC;
emio_spi1_m_o : OUT STD_LOGIC;
emio_spi1_mo_t : OUT STD_LOGIC;
emio_spi1_s_i : IN STD_LOGIC;
emio_spi1_s_o : OUT STD_LOGIC;
emio_spi1_so_t : OUT STD_LOGIC;
emio_spi1_ss_i_n : IN STD_LOGIC;
emio_spi1_ss_o_n : OUT STD_LOGIC;
emio_spi1_ss1_o_n : OUT STD_LOGIC;
emio_spi1_ss2_o_n : OUT STD_LOGIC;
emio_spi1_ss_n_t : OUT STD_LOGIC;
pl_ps_trace_clk : IN STD_LOGIC;
ps_pl_tracectl : OUT STD_LOGIC;
ps_pl_tracedata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
trace_clk_out : OUT STD_LOGIC;
emio_ttc0_wave_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_ttc0_clk_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_ttc1_wave_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_ttc1_clk_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_ttc2_wave_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_ttc2_clk_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_ttc3_wave_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_ttc3_clk_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
emio_wdt0_clk_i : IN STD_LOGIC;
emio_wdt0_rst_o : OUT STD_LOGIC;
emio_wdt1_clk_i : IN STD_LOGIC;
emio_wdt1_rst_o : OUT STD_LOGIC;
emio_hub_port_overcrnt_usb3_0 : IN STD_LOGIC;
emio_hub_port_overcrnt_usb3_1 : IN STD_LOGIC;
emio_hub_port_overcrnt_usb2_0 : IN STD_LOGIC;
emio_hub_port_overcrnt_usb2_1 : IN STD_LOGIC;
emio_u2dsport_vbus_ctrl_usb3_0 : OUT STD_LOGIC;
emio_u2dsport_vbus_ctrl_usb3_1 : OUT STD_LOGIC;
emio_u3dsport_vbus_ctrl_usb3_0 : OUT STD_LOGIC;
emio_u3dsport_vbus_ctrl_usb3_1 : OUT STD_LOGIC;
adma_fci_clk : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pl2adma_cvld : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pl2adma_tack : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
adma2pl_cack : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
adma2pl_tvld : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
perif_gdma_clk : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
perif_gdma_cvld : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
perif_gdma_tack : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gdma_perif_cack : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gdma_perif_tvld : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pl_clock_stop : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pll_aux_refclk_lpd : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
pll_aux_refclk_fpd : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dp_audio_ref_clk : OUT STD_LOGIC;
dp_video_ref_clk : OUT STD_LOGIC;
dp_s_axis_audio_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dp_s_axis_audio_tid : IN STD_LOGIC;
dp_s_axis_audio_tvalid : IN STD_LOGIC;
dp_s_axis_audio_tready : OUT STD_LOGIC;
dp_m_axis_mixed_audio_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
dp_m_axis_mixed_audio_tid : OUT STD_LOGIC;
dp_m_axis_mixed_audio_tvalid : OUT STD_LOGIC;
dp_m_axis_mixed_audio_tready : IN STD_LOGIC;
dp_s_axis_audio_clk : IN STD_LOGIC;
dp_live_video_in_vsync : IN STD_LOGIC;
dp_live_video_in_hsync : IN STD_LOGIC;
dp_live_video_in_de : IN STD_LOGIC;
dp_live_video_in_pixel1 : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
dp_video_in_clk : IN STD_LOGIC;
dp_video_out_hsync : OUT STD_LOGIC;
dp_video_out_vsync : OUT STD_LOGIC;
dp_video_out_pixel1 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
dp_aux_data_in : IN STD_LOGIC;
dp_aux_data_out : OUT STD_LOGIC;
dp_aux_data_oe_n : OUT STD_LOGIC;
dp_live_gfx_alpha_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dp_live_gfx_pixel1_in : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
dp_hot_plug_detect : IN STD_LOGIC;
dp_external_custom_event1 : IN STD_LOGIC;
dp_external_custom_event2 : IN STD_LOGIC;
dp_external_vsync_event : IN STD_LOGIC;
dp_live_video_de_out : OUT STD_LOGIC;
pl_ps_eventi : IN STD_LOGIC;
ps_pl_evento : OUT STD_LOGIC;
ps_pl_standbywfe : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ps_pl_standbywfi : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pl_ps_apugic_irq : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pl_ps_apugic_fiq : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rpu_eventi0 : IN STD_LOGIC;
rpu_eventi1 : IN STD_LOGIC;
rpu_evento0 : OUT STD_LOGIC;
rpu_evento1 : OUT STD_LOGIC;
nfiq0_lpd_rpu : IN STD_LOGIC;
nfiq1_lpd_rpu : IN STD_LOGIC;
nirq0_lpd_rpu : IN STD_LOGIC;
nirq1_lpd_rpu : IN STD_LOGIC;
irq_ipi_pl_0 : OUT STD_LOGIC;
irq_ipi_pl_1 : OUT STD_LOGIC;
irq_ipi_pl_2 : OUT STD_LOGIC;
irq_ipi_pl_3 : OUT STD_LOGIC;
stm_event : IN STD_LOGIC_VECTOR(59 DOWNTO 0);
pl_ps_trigger_0 : IN STD_LOGIC;
pl_ps_trigger_1 : IN STD_LOGIC;
pl_ps_trigger_2 : IN STD_LOGIC;
pl_ps_trigger_3 : IN STD_LOGIC;
ps_pl_trigack_0 : OUT STD_LOGIC;
ps_pl_trigack_1 : OUT STD_LOGIC;
ps_pl_trigack_2 : OUT STD_LOGIC;
ps_pl_trigack_3 : OUT STD_LOGIC;
ps_pl_trigger_0 : OUT STD_LOGIC;
ps_pl_trigger_1 : OUT STD_LOGIC;
ps_pl_trigger_2 : OUT STD_LOGIC;
ps_pl_trigger_3 : OUT STD_LOGIC;
pl_ps_trigack_0 : IN STD_LOGIC;
pl_ps_trigack_1 : IN STD_LOGIC;
pl_ps_trigack_2 : IN STD_LOGIC;
pl_ps_trigack_3 : IN STD_LOGIC;
ftm_gpo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ftm_gpi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
pl_ps_irq0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
pl_ps_irq1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
pl_resetn0 : OUT STD_LOGIC;
pl_resetn1 : OUT STD_LOGIC;
pl_resetn2 : OUT STD_LOGIC;
pl_resetn3 : OUT STD_LOGIC;
osc_rtc_clk : OUT STD_LOGIC;
pl_pmu_gpi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
pmu_pl_gpo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aib_pmu_afifm_fpd_ack : IN STD_LOGIC;
aib_pmu_afifm_lpd_ack : IN STD_LOGIC;
pmu_aib_afifm_fpd_req : OUT STD_LOGIC;
pmu_aib_afifm_lpd_req : OUT STD_LOGIC;
pmu_error_from_pl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pmu_error_to_pl : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
pl_acpinact : IN STD_LOGIC;
pl_clk0 : OUT STD_LOGIC;
pl_clk1 : OUT STD_LOGIC;
pl_clk2 : OUT STD_LOGIC;
pl_clk3 : OUT STD_LOGIC;
ps_pl_irq_can0 : OUT STD_LOGIC;
ps_pl_irq_can1 : OUT STD_LOGIC;
ps_pl_irq_enet0 : OUT STD_LOGIC;
ps_pl_irq_enet1 : OUT STD_LOGIC;
ps_pl_irq_enet2 : OUT STD_LOGIC;
ps_pl_irq_enet3 : OUT STD_LOGIC;
ps_pl_irq_enet0_wake : OUT STD_LOGIC;
ps_pl_irq_enet1_wake : OUT STD_LOGIC;
ps_pl_irq_enet2_wake : OUT STD_LOGIC;
ps_pl_irq_enet3_wake : OUT STD_LOGIC;
ps_pl_irq_gpio : OUT STD_LOGIC;
ps_pl_irq_i2c0 : OUT STD_LOGIC;
ps_pl_irq_i2c1 : OUT STD_LOGIC;
ps_pl_irq_uart0 : OUT STD_LOGIC;
ps_pl_irq_uart1 : OUT STD_LOGIC;
ps_pl_irq_sdio0 : OUT STD_LOGIC;
ps_pl_irq_sdio1 : OUT STD_LOGIC;
ps_pl_irq_sdio0_wake : OUT STD_LOGIC;
ps_pl_irq_sdio1_wake : OUT STD_LOGIC;
ps_pl_irq_spi0 : OUT STD_LOGIC;
ps_pl_irq_spi1 : OUT STD_LOGIC;
ps_pl_irq_qspi : OUT STD_LOGIC;
ps_pl_irq_ttc0_0 : OUT STD_LOGIC;
ps_pl_irq_ttc0_1 : OUT STD_LOGIC;
ps_pl_irq_ttc0_2 : OUT STD_LOGIC;
ps_pl_irq_ttc1_0 : OUT STD_LOGIC;
ps_pl_irq_ttc1_1 : OUT STD_LOGIC;
ps_pl_irq_ttc1_2 : OUT STD_LOGIC;
ps_pl_irq_ttc2_0 : OUT STD_LOGIC;
ps_pl_irq_ttc2_1 : OUT STD_LOGIC;
ps_pl_irq_ttc2_2 : OUT STD_LOGIC;
ps_pl_irq_ttc3_0 : OUT STD_LOGIC;
ps_pl_irq_ttc3_1 : OUT STD_LOGIC;
ps_pl_irq_ttc3_2 : OUT STD_LOGIC;
ps_pl_irq_csu_pmu_wdt : OUT STD_LOGIC;
ps_pl_irq_lp_wdt : OUT STD_LOGIC;
ps_pl_irq_usb3_0_endpoint : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ps_pl_irq_usb3_0_otg : OUT STD_LOGIC;
ps_pl_irq_usb3_1_endpoint : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ps_pl_irq_usb3_1_otg : OUT STD_LOGIC;
ps_pl_irq_adma_chan : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ps_pl_irq_usb3_0_pmu_wakeup : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ps_pl_irq_gdma_chan : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ps_pl_irq_csu : OUT STD_LOGIC;
ps_pl_irq_csu_dma : OUT STD_LOGIC;
ps_pl_irq_efuse : OUT STD_LOGIC;
ps_pl_irq_xmpu_lpd : OUT STD_LOGIC;
ps_pl_irq_ddr_ss : OUT STD_LOGIC;
ps_pl_irq_nand : OUT STD_LOGIC;
ps_pl_irq_fp_wdt : OUT STD_LOGIC;
ps_pl_irq_pcie_msi : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ps_pl_irq_pcie_legacy : OUT STD_LOGIC;
ps_pl_irq_pcie_dma : OUT STD_LOGIC;
ps_pl_irq_pcie_msc : OUT STD_LOGIC;
ps_pl_irq_dport : OUT STD_LOGIC;
ps_pl_irq_fpd_apb_int : OUT STD_LOGIC;
ps_pl_irq_fpd_atb_error : OUT STD_LOGIC;
ps_pl_irq_dpdma : OUT STD_LOGIC;
ps_pl_irq_apm_fpd : OUT STD_LOGIC;
ps_pl_irq_gpu : OUT STD_LOGIC;
ps_pl_irq_sata : OUT STD_LOGIC;
ps_pl_irq_xmpu_fpd : OUT STD_LOGIC;
ps_pl_irq_apu_cpumnt : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ps_pl_irq_apu_cti : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ps_pl_irq_apu_pmu : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ps_pl_irq_apu_comm : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ps_pl_irq_apu_l2err : OUT STD_LOGIC;
ps_pl_irq_apu_exterr : OUT STD_LOGIC;
ps_pl_irq_apu_regs : OUT STD_LOGIC;
ps_pl_irq_intf_ppd_cci : OUT STD_LOGIC;
ps_pl_irq_intf_fpd_smmu : OUT STD_LOGIC;
ps_pl_irq_atb_err_lpd : OUT STD_LOGIC;
ps_pl_irq_aib_axi : OUT STD_LOGIC;
ps_pl_irq_ams : OUT STD_LOGIC;
ps_pl_irq_lpd_apm : OUT STD_LOGIC;
ps_pl_irq_rtc_alaram : OUT STD_LOGIC;
ps_pl_irq_rtc_seconds : OUT STD_LOGIC;
ps_pl_irq_clkmon : OUT STD_LOGIC;
ps_pl_irq_ipi_channel0 : OUT STD_LOGIC;
ps_pl_irq_ipi_channel1 : OUT STD_LOGIC;
ps_pl_irq_ipi_channel2 : OUT STD_LOGIC;
ps_pl_irq_ipi_channel7 : OUT STD_LOGIC;
ps_pl_irq_ipi_channel8 : OUT STD_LOGIC;
ps_pl_irq_ipi_channel9 : OUT STD_LOGIC;
ps_pl_irq_ipi_channel10 : OUT STD_LOGIC;
ps_pl_irq_rpu_pm : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ps_pl_irq_ocm_error : OUT STD_LOGIC;
ps_pl_irq_lpd_apb_intr : OUT STD_LOGIC;
ps_pl_irq_r5_core0_ecc_error : OUT STD_LOGIC;
ps_pl_irq_r5_core1_ecc_error : OUT STD_LOGIC;
test_adc_clk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
test_adc_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
test_adc2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
test_db : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
test_adc_out : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
test_ams_osc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
test_mon_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
test_dclk : IN STD_LOGIC;
test_den : IN STD_LOGIC;
test_dwe : IN STD_LOGIC;
test_daddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
test_di : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
test_drdy : OUT STD_LOGIC;
test_do : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
test_convst : IN STD_LOGIC;
pstp_pl_clk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pstp_pl_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
pstp_pl_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
pstp_pl_ts : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fmio_test_gem_scanmux_1 : IN STD_LOGIC;
fmio_test_gem_scanmux_2 : IN STD_LOGIC;
test_char_mode_fpd_n : IN STD_LOGIC;
test_char_mode_lpd_n : IN STD_LOGIC;
fmio_test_io_char_scan_clock : IN STD_LOGIC;
fmio_test_io_char_scanenable : IN STD_LOGIC;
fmio_test_io_char_scan_in : IN STD_LOGIC;
fmio_test_io_char_scan_out : OUT STD_LOGIC;
fmio_test_io_char_scan_reset_n : IN STD_LOGIC;
fmio_char_afifslpd_test_select_n : IN STD_LOGIC;
fmio_char_afifslpd_test_input : IN STD_LOGIC;
fmio_char_afifslpd_test_output : OUT STD_LOGIC;
fmio_char_afifsfpd_test_select_n : IN STD_LOGIC;
fmio_char_afifsfpd_test_input : IN STD_LOGIC;
fmio_char_afifsfpd_test_output : OUT STD_LOGIC;
io_char_audio_in_test_data : IN STD_LOGIC;
io_char_audio_mux_sel_n : IN STD_LOGIC;
io_char_video_in_test_data : IN STD_LOGIC;
io_char_video_mux_sel_n : IN STD_LOGIC;
io_char_video_out_test_data : OUT STD_LOGIC;
io_char_audio_out_test_data : OUT STD_LOGIC;
fmio_test_qspi_scanmux_1_n : IN STD_LOGIC;
fmio_test_sdio_scanmux_1 : IN STD_LOGIC;
fmio_test_sdio_scanmux_2 : IN STD_LOGIC;
fmio_sd0_dll_test_in_n : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
fmio_sd0_dll_test_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
fmio_sd1_dll_test_in_n : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
fmio_sd1_dll_test_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
test_pl_scan_chopper_si : IN STD_LOGIC;
test_pl_scan_chopper_so : OUT STD_LOGIC;
test_pl_scan_chopper_trig : IN STD_LOGIC;
test_pl_scan_clk0 : IN STD_LOGIC;
test_pl_scan_clk1 : IN STD_LOGIC;
test_pl_scan_edt_clk : IN STD_LOGIC;
test_pl_scan_edt_in_apu : IN STD_LOGIC;
test_pl_scan_edt_in_cpu : IN STD_LOGIC;
test_pl_scan_edt_in_ddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
test_pl_scan_edt_in_fp : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
test_pl_scan_edt_in_gpu : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
test_pl_scan_edt_in_lp : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
test_pl_scan_edt_in_usb3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
test_pl_scan_edt_out_apu : OUT STD_LOGIC;
test_pl_scan_edt_out_cpu0 : OUT STD_LOGIC;
test_pl_scan_edt_out_cpu1 : OUT STD_LOGIC;
test_pl_scan_edt_out_cpu2 : OUT STD_LOGIC;
test_pl_scan_edt_out_cpu3 : OUT STD_LOGIC;
test_pl_scan_edt_out_ddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
test_pl_scan_edt_out_fp : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
test_pl_scan_edt_out_gpu : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
test_pl_scan_edt_out_lp : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
test_pl_scan_edt_out_usb3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
test_pl_scan_edt_update : IN STD_LOGIC;
test_pl_scan_reset_n : IN STD_LOGIC;
test_pl_scanenable : IN STD_LOGIC;
test_pl_scan_pll_reset : IN STD_LOGIC;
test_pl_scan_spare_in0 : IN STD_LOGIC;
test_pl_scan_spare_in1 : IN STD_LOGIC;
test_pl_scan_spare_out0 : OUT STD_LOGIC;
test_pl_scan_spare_out1 : OUT STD_LOGIC;
test_pl_scan_wrap_clk : IN STD_LOGIC;
test_pl_scan_wrap_ishift : IN STD_LOGIC;
test_pl_scan_wrap_oshift : IN STD_LOGIC;
test_pl_scan_slcr_config_clk : IN STD_LOGIC;
test_pl_scan_slcr_config_rstn : IN STD_LOGIC;
test_pl_scan_slcr_config_si : IN STD_LOGIC;
test_pl_scan_spare_in2 : IN STD_LOGIC;
test_pl_scanenable_slcr_en : IN STD_LOGIC;
test_pl_pll_lock_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
test_pl_scan_slcr_config_so : OUT STD_LOGIC;
tst_rtc_calibreg_in : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
tst_rtc_calibreg_out : OUT STD_LOGIC_VECTOR(20 DOWNTO 0);
tst_rtc_calibreg_we : IN STD_LOGIC;
tst_rtc_clk : IN STD_LOGIC;
tst_rtc_osc_clk_out : OUT STD_LOGIC;
tst_rtc_sec_counter_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
tst_rtc_seconds_raw_int : OUT STD_LOGIC;
tst_rtc_testclock_select_n : IN STD_LOGIC;
tst_rtc_tick_counter_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
tst_rtc_timesetreg_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
tst_rtc_timesetreg_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
tst_rtc_disable_bat_op : IN STD_LOGIC;
tst_rtc_osc_cntrl_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tst_rtc_osc_cntrl_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tst_rtc_osc_cntrl_we : IN STD_LOGIC;
tst_rtc_sec_reload : IN STD_LOGIC;
tst_rtc_timesetreg_we : IN STD_LOGIC;
tst_rtc_testmode_n : IN STD_LOGIC;
test_usb0_funcmux_0_n : IN STD_LOGIC;
test_usb1_funcmux_0_n : IN STD_LOGIC;
test_usb0_scanmux_0_n : IN STD_LOGIC;
test_usb1_scanmux_0_n : IN STD_LOGIC;
lpd_pll_test_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
pl_lpd_pll_test_ck_sel_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
pl_lpd_pll_test_fract_clk_sel_n : IN STD_LOGIC;
pl_lpd_pll_test_fract_en_n : IN STD_LOGIC;
pl_lpd_pll_test_mux_sel : IN STD_LOGIC;
pl_lpd_pll_test_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
fpd_pll_test_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
pl_fpd_pll_test_ck_sel_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
pl_fpd_pll_test_fract_clk_sel_n : IN STD_LOGIC;
pl_fpd_pll_test_fract_en_n : IN STD_LOGIC;
pl_fpd_pll_test_mux_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
pl_fpd_pll_test_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
fmio_char_gem_selection : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
fmio_char_gem_test_select_n : IN STD_LOGIC;
fmio_char_gem_test_input : IN STD_LOGIC;
fmio_char_gem_test_output : OUT STD_LOGIC;
test_ddr2pl_dcd_skewout : OUT STD_LOGIC;
test_pl2ddr_dcd_sample_pulse : IN STD_LOGIC;
test_bscan_en_n : IN STD_LOGIC;
test_bscan_tdi : IN STD_LOGIC;
test_bscan_updatedr : IN STD_LOGIC;
test_bscan_shiftdr : IN STD_LOGIC;
test_bscan_reset_tap_b : IN STD_LOGIC;
test_bscan_misr_jtag_load : IN STD_LOGIC;
test_bscan_intest : IN STD_LOGIC;
test_bscan_extest : IN STD_LOGIC;
test_bscan_clockdr : IN STD_LOGIC;
test_bscan_ac_mode : IN STD_LOGIC;
test_bscan_ac_test : IN STD_LOGIC;
test_bscan_init_memory : IN STD_LOGIC;
test_bscan_mode_c : IN STD_LOGIC;
test_bscan_tdo : OUT STD_LOGIC;
i_dbg_l0_txclk : IN STD_LOGIC;
i_dbg_l0_rxclk : IN STD_LOGIC;
i_dbg_l1_txclk : IN STD_LOGIC;
i_dbg_l1_rxclk : IN STD_LOGIC;
i_dbg_l2_txclk : IN STD_LOGIC;
i_dbg_l2_rxclk : IN STD_LOGIC;
i_dbg_l3_txclk : IN STD_LOGIC;
i_dbg_l3_rxclk : IN STD_LOGIC;
i_afe_rx_symbol_clk_by_2_pl : IN STD_LOGIC;
pl_fpd_spare_0_in : IN STD_LOGIC;
pl_fpd_spare_1_in : IN STD_LOGIC;
pl_fpd_spare_2_in : IN STD_LOGIC;
pl_fpd_spare_3_in : IN STD_LOGIC;
pl_fpd_spare_4_in : IN STD_LOGIC;
fpd_pl_spare_0_out : OUT STD_LOGIC;
fpd_pl_spare_1_out : OUT STD_LOGIC;
fpd_pl_spare_2_out : OUT STD_LOGIC;
fpd_pl_spare_3_out : OUT STD_LOGIC;
fpd_pl_spare_4_out : OUT STD_LOGIC;
pl_lpd_spare_0_in : IN STD_LOGIC;
pl_lpd_spare_1_in : IN STD_LOGIC;
pl_lpd_spare_2_in : IN STD_LOGIC;
pl_lpd_spare_3_in : IN STD_LOGIC;
pl_lpd_spare_4_in : IN STD_LOGIC;
lpd_pl_spare_0_out : OUT STD_LOGIC;
lpd_pl_spare_1_out : OUT STD_LOGIC;
lpd_pl_spare_2_out : OUT STD_LOGIC;
lpd_pl_spare_3_out : OUT STD_LOGIC;
lpd_pl_spare_4_out : OUT STD_LOGIC;
o_dbg_l0_phystatus : OUT STD_LOGIC;
o_dbg_l0_rxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l0_rxdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l0_rxvalid : OUT STD_LOGIC;
o_dbg_l0_rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
o_dbg_l0_rxelecidle : OUT STD_LOGIC;
o_dbg_l0_rstb : OUT STD_LOGIC;
o_dbg_l0_txdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l0_txdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l0_rate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l0_powerdown : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l0_txelecidle : OUT STD_LOGIC;
o_dbg_l0_txdetrx_lpback : OUT STD_LOGIC;
o_dbg_l0_rxpolarity : OUT STD_LOGIC;
o_dbg_l0_tx_sgmii_ewrap : OUT STD_LOGIC;
o_dbg_l0_rx_sgmii_en_cdet : OUT STD_LOGIC;
o_dbg_l0_sata_corerxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l0_sata_corerxdatavalid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l0_sata_coreready : OUT STD_LOGIC;
o_dbg_l0_sata_coreclockready : OUT STD_LOGIC;
o_dbg_l0_sata_corerxsignaldet : OUT STD_LOGIC;
o_dbg_l0_sata_phyctrltxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l0_sata_phyctrltxidle : OUT STD_LOGIC;
o_dbg_l0_sata_phyctrltxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l0_sata_phyctrlrxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l0_sata_phyctrltxrst : OUT STD_LOGIC;
o_dbg_l0_sata_phyctrlrxrst : OUT STD_LOGIC;
o_dbg_l0_sata_phyctrlreset : OUT STD_LOGIC;
o_dbg_l0_sata_phyctrlpartial : OUT STD_LOGIC;
o_dbg_l0_sata_phyctrlslumber : OUT STD_LOGIC;
o_dbg_l1_phystatus : OUT STD_LOGIC;
o_dbg_l1_rxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l1_rxdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l1_rxvalid : OUT STD_LOGIC;
o_dbg_l1_rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
o_dbg_l1_rxelecidle : OUT STD_LOGIC;
o_dbg_l1_rstb : OUT STD_LOGIC;
o_dbg_l1_txdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l1_txdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l1_rate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l1_powerdown : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l1_txelecidle : OUT STD_LOGIC;
o_dbg_l1_txdetrx_lpback : OUT STD_LOGIC;
o_dbg_l1_rxpolarity : OUT STD_LOGIC;
o_dbg_l1_tx_sgmii_ewrap : OUT STD_LOGIC;
o_dbg_l1_rx_sgmii_en_cdet : OUT STD_LOGIC;
o_dbg_l1_sata_corerxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l1_sata_corerxdatavalid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l1_sata_coreready : OUT STD_LOGIC;
o_dbg_l1_sata_coreclockready : OUT STD_LOGIC;
o_dbg_l1_sata_corerxsignaldet : OUT STD_LOGIC;
o_dbg_l1_sata_phyctrltxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l1_sata_phyctrltxidle : OUT STD_LOGIC;
o_dbg_l1_sata_phyctrltxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l1_sata_phyctrlrxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l1_sata_phyctrltxrst : OUT STD_LOGIC;
o_dbg_l1_sata_phyctrlrxrst : OUT STD_LOGIC;
o_dbg_l1_sata_phyctrlreset : OUT STD_LOGIC;
o_dbg_l1_sata_phyctrlpartial : OUT STD_LOGIC;
o_dbg_l1_sata_phyctrlslumber : OUT STD_LOGIC;
o_dbg_l2_phystatus : OUT STD_LOGIC;
o_dbg_l2_rxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l2_rxdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l2_rxvalid : OUT STD_LOGIC;
o_dbg_l2_rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
o_dbg_l2_rxelecidle : OUT STD_LOGIC;
o_dbg_l2_rstb : OUT STD_LOGIC;
o_dbg_l2_txdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l2_txdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l2_rate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l2_powerdown : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l2_txelecidle : OUT STD_LOGIC;
o_dbg_l2_txdetrx_lpback : OUT STD_LOGIC;
o_dbg_l2_rxpolarity : OUT STD_LOGIC;
o_dbg_l2_tx_sgmii_ewrap : OUT STD_LOGIC;
o_dbg_l2_rx_sgmii_en_cdet : OUT STD_LOGIC;
o_dbg_l2_sata_corerxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l2_sata_corerxdatavalid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l2_sata_coreready : OUT STD_LOGIC;
o_dbg_l2_sata_coreclockready : OUT STD_LOGIC;
o_dbg_l2_sata_corerxsignaldet : OUT STD_LOGIC;
o_dbg_l2_sata_phyctrltxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l2_sata_phyctrltxidle : OUT STD_LOGIC;
o_dbg_l2_sata_phyctrltxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l2_sata_phyctrlrxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l2_sata_phyctrltxrst : OUT STD_LOGIC;
o_dbg_l2_sata_phyctrlrxrst : OUT STD_LOGIC;
o_dbg_l2_sata_phyctrlreset : OUT STD_LOGIC;
o_dbg_l2_sata_phyctrlpartial : OUT STD_LOGIC;
o_dbg_l2_sata_phyctrlslumber : OUT STD_LOGIC;
o_dbg_l3_phystatus : OUT STD_LOGIC;
o_dbg_l3_rxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l3_rxdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l3_rxvalid : OUT STD_LOGIC;
o_dbg_l3_rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
o_dbg_l3_rxelecidle : OUT STD_LOGIC;
o_dbg_l3_rstb : OUT STD_LOGIC;
o_dbg_l3_txdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l3_txdatak : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l3_rate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l3_powerdown : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l3_txelecidle : OUT STD_LOGIC;
o_dbg_l3_txdetrx_lpback : OUT STD_LOGIC;
o_dbg_l3_rxpolarity : OUT STD_LOGIC;
o_dbg_l3_tx_sgmii_ewrap : OUT STD_LOGIC;
o_dbg_l3_rx_sgmii_en_cdet : OUT STD_LOGIC;
o_dbg_l3_sata_corerxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l3_sata_corerxdatavalid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l3_sata_coreready : OUT STD_LOGIC;
o_dbg_l3_sata_coreclockready : OUT STD_LOGIC;
o_dbg_l3_sata_corerxsignaldet : OUT STD_LOGIC;
o_dbg_l3_sata_phyctrltxdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_dbg_l3_sata_phyctrltxidle : OUT STD_LOGIC;
o_dbg_l3_sata_phyctrltxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l3_sata_phyctrlrxrate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_dbg_l3_sata_phyctrltxrst : OUT STD_LOGIC;
o_dbg_l3_sata_phyctrlrxrst : OUT STD_LOGIC;
o_dbg_l3_sata_phyctrlreset : OUT STD_LOGIC;
o_dbg_l3_sata_phyctrlpartial : OUT STD_LOGIC;
o_dbg_l3_sata_phyctrlslumber : OUT STD_LOGIC;
dbg_path_fifo_bypass : OUT STD_LOGIC;
i_afe_pll_pd_hs_clock_r : IN STD_LOGIC;
i_afe_mode : IN STD_LOGIC;
i_bgcal_afe_mode : IN STD_LOGIC;
o_afe_cmn_calib_comp_out : OUT STD_LOGIC;
i_afe_cmn_bg_enable_low_leakage : IN STD_LOGIC;
i_afe_cmn_bg_iso_ctrl_bar : IN STD_LOGIC;
i_afe_cmn_bg_pd : IN STD_LOGIC;
i_afe_cmn_bg_pd_bg_ok : IN STD_LOGIC;
i_afe_cmn_bg_pd_ptat : IN STD_LOGIC;
i_afe_cmn_calib_en_iconst : IN STD_LOGIC;
i_afe_cmn_calib_enable_low_leakage : IN STD_LOGIC;
i_afe_cmn_calib_iso_ctrl_bar : IN STD_LOGIC;
o_afe_pll_dco_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
o_afe_pll_clk_sym_hs : OUT STD_LOGIC;
o_afe_pll_fbclk_frac : OUT STD_LOGIC;
o_afe_rx_pipe_lfpsbcn_rxelecidle : OUT STD_LOGIC;
o_afe_rx_pipe_sigdet : OUT STD_LOGIC;
o_afe_rx_symbol : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_afe_rx_symbol_clk_by_2 : OUT STD_LOGIC;
o_afe_rx_uphy_save_calcode : OUT STD_LOGIC;
o_afe_rx_uphy_startloop_buf : OUT STD_LOGIC;
o_afe_rx_uphy_rx_calib_done : OUT STD_LOGIC;
i_afe_rx_rxpma_rstb : IN STD_LOGIC;
i_afe_rx_uphy_restore_calcode_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
i_afe_rx_pipe_rxeqtraining : IN STD_LOGIC;
i_afe_rx_iso_hsrx_ctrl_bar : IN STD_LOGIC;
i_afe_rx_iso_lfps_ctrl_bar : IN STD_LOGIC;
i_afe_rx_iso_sigdet_ctrl_bar : IN STD_LOGIC;
i_afe_rx_hsrx_clock_stop_req : IN STD_LOGIC;
o_afe_rx_uphy_save_calcode_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_afe_rx_hsrx_clock_stop_ack : OUT STD_LOGIC;
o_afe_pg_avddcr : OUT STD_LOGIC;
o_afe_pg_avddio : OUT STD_LOGIC;
o_afe_pg_dvddcr : OUT STD_LOGIC;
o_afe_pg_static_avddcr : OUT STD_LOGIC;
o_afe_pg_static_avddio : OUT STD_LOGIC;
i_pll_afe_mode : IN STD_LOGIC;
i_afe_pll_coarse_code : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
i_afe_pll_en_clock_hs_div2 : IN STD_LOGIC;
i_afe_pll_fbdiv : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
i_afe_pll_load_fbdiv : IN STD_LOGIC;
i_afe_pll_pd : IN STD_LOGIC;
i_afe_pll_pd_pfd : IN STD_LOGIC;
i_afe_pll_rst_fdbk_div : IN STD_LOGIC;
i_afe_pll_startloop : IN STD_LOGIC;
i_afe_pll_v2i_code : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
i_afe_pll_v2i_prog : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
i_afe_pll_vco_cnt_window : IN STD_LOGIC;
i_afe_rx_mphy_gate_symbol_clk : IN STD_LOGIC;
i_afe_rx_mphy_mux_hsb_ls : IN STD_LOGIC;
i_afe_rx_pipe_rx_term_enable : IN STD_LOGIC;
i_afe_rx_uphy_biasgen_iconst_core_mirror_enable : IN STD_LOGIC;
i_afe_rx_uphy_biasgen_iconst_io_mirror_enable : IN STD_LOGIC;
i_afe_rx_uphy_biasgen_irconst_core_mirror_enable : IN STD_LOGIC;
i_afe_rx_uphy_enable_cdr : IN STD_LOGIC;
i_afe_rx_uphy_enable_low_leakage : IN STD_LOGIC;
i_afe_rx_rxpma_refclk_dig : IN STD_LOGIC;
i_afe_rx_uphy_hsrx_rstb : IN STD_LOGIC;
i_afe_rx_uphy_pdn_hs_des : IN STD_LOGIC;
i_afe_rx_uphy_pd_samp_c2c : IN STD_LOGIC;
i_afe_rx_uphy_pd_samp_c2c_eclk : IN STD_LOGIC;
i_afe_rx_uphy_pso_clk_lane : IN STD_LOGIC;
i_afe_rx_uphy_pso_eq : IN STD_LOGIC;
i_afe_rx_uphy_pso_hsrxdig : IN STD_LOGIC;
i_afe_rx_uphy_pso_iqpi : IN STD_LOGIC;
i_afe_rx_uphy_pso_lfpsbcn : IN STD_LOGIC;
i_afe_rx_uphy_pso_samp_flops : IN STD_LOGIC;
i_afe_rx_uphy_pso_sigdet : IN STD_LOGIC;
i_afe_rx_uphy_restore_calcode : IN STD_LOGIC;
i_afe_rx_uphy_run_calib : IN STD_LOGIC;
i_afe_rx_uphy_rx_lane_polarity_swap : IN STD_LOGIC;
i_afe_rx_uphy_startloop_pll : IN STD_LOGIC;
i_afe_rx_uphy_hsclk_division_factor : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i_afe_rx_uphy_rx_pma_opmode : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
i_afe_tx_enable_hsclk_division : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i_afe_tx_enable_ldo : IN STD_LOGIC;
i_afe_tx_enable_ref : IN STD_LOGIC;
i_afe_tx_enable_supply_hsclk : IN STD_LOGIC;
i_afe_tx_enable_supply_pipe : IN STD_LOGIC;
i_afe_tx_enable_supply_serializer : IN STD_LOGIC;
i_afe_tx_enable_supply_uphy : IN STD_LOGIC;
i_afe_tx_hs_ser_rstb : IN STD_LOGIC;
i_afe_tx_hs_symbol : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
i_afe_tx_mphy_tx_ls_data : IN STD_LOGIC;
i_afe_tx_pipe_tx_enable_idle_mode : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i_afe_tx_pipe_tx_enable_lfps : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i_afe_tx_pipe_tx_enable_rxdet : IN STD_LOGIC;
i_afe_TX_uphy_txpma_opmode : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
i_afe_TX_pmadig_digital_reset_n : IN STD_LOGIC;
i_afe_TX_serializer_rst_rel : IN STD_LOGIC;
i_afe_TX_pll_symb_clk_2 : IN STD_LOGIC;
i_afe_TX_ana_if_rate : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i_afe_TX_en_dig_sublp_mode : IN STD_LOGIC;
i_afe_TX_LPBK_SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
i_afe_TX_iso_ctrl_bar : IN STD_LOGIC;
i_afe_TX_ser_iso_ctrl_bar : IN STD_LOGIC;
i_afe_TX_lfps_clk : IN STD_LOGIC;
i_afe_TX_serializer_rstb : IN STD_LOGIC;
o_afe_TX_dig_reset_rel_ack : OUT STD_LOGIC;
o_afe_TX_pipe_TX_dn_rxdet : OUT STD_LOGIC;
o_afe_TX_pipe_TX_dp_rxdet : OUT STD_LOGIC;
i_afe_tx_pipe_tx_fast_est_common_mode : IN STD_LOGIC;
o_dbg_l0_txclk : OUT STD_LOGIC;
o_dbg_l0_rxclk : OUT STD_LOGIC;
o_dbg_l1_txclk : OUT STD_LOGIC;
o_dbg_l1_rxclk : OUT STD_LOGIC;
o_dbg_l2_txclk : OUT STD_LOGIC;
o_dbg_l2_rxclk : OUT STD_LOGIC;
o_dbg_l3_txclk : OUT STD_LOGIC;
o_dbg_l3_rxclk : OUT STD_LOGIC;
emio_i2c0_scl_t_n : OUT STD_LOGIC;
emio_i2c0_sda_t_n : OUT STD_LOGIC;
emio_enet0_mdio_t_n : OUT STD_LOGIC;
emio_enet1_mdio_t_n : OUT STD_LOGIC;
emio_enet2_mdio_t_n : OUT STD_LOGIC;
emio_enet3_mdio_t_n : OUT STD_LOGIC;
emio_gpio_t_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
emio_i2c1_scl_t_n : OUT STD_LOGIC;
emio_i2c1_sda_t_n : OUT STD_LOGIC;
emio_spi0_sclk_t_n : OUT STD_LOGIC;
emio_spi0_mo_t_n : OUT STD_LOGIC;
emio_spi0_so_t_n : OUT STD_LOGIC;
emio_spi0_ss_n_t_n : OUT STD_LOGIC;
emio_spi1_sclk_t_n : OUT STD_LOGIC;
emio_spi1_mo_t_n : OUT STD_LOGIC;
emio_spi1_so_t_n : OUT STD_LOGIC;
emio_spi1_ss_n_t_n : OUT STD_LOGIC
);
END COMPONENT zynq_ultra_ps_e_v3_5_0_zynq_ultra_ps_e;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design2023_1_zynq_ultra_ps_e_0_0_arch: ARCHITECTURE IS "zynq_ultra_ps_e_v3_5_0_zynq_ultra_ps_e,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design2023_1_zynq_ultra_ps_e_0_0_arch : ARCHITECTURE IS "design2023_1_zynq_ultra_ps_e_0_0,zynq_ultra_ps_e_v3_5_0_zynq_ultra_ps_e,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design2023_1_zynq_ultra_ps_e_0_0_arch: ARCHITECTURE IS "design2023_1_zynq_ultra_ps_e_0_0,zynq_ultra_ps_e_v3_5_0_zynq_ultra_ps_e,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=zynq_ultra_ps_e,x_ipVersion=3.5,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_DP_USE_AUDIO=0,C_DP_USE_VIDEO=0,C_MAXIGP0_DATA_WIDTH=128,C_MAXIGP1_DATA_WIDTH=128,C_MAXIGP2_DATA_WIDTH=32,C_SAXIGP0_DATA_WIDTH=128,C_SAXIGP1_DATA_WIDTH=128,C_SAXIGP2_DATA_WIDTH=128,C_SAXIGP3_DATA_WIDTH=128,C_SAXIGP4_DATA_WIDTH=128,C_SAXIGP5_DATA_WIDTH=128,C_SAXIG" &
"P6_DATA_WIDTH=128,C_USE_DIFF_RW_CLK_GP0=0,C_USE_DIFF_RW_CLK_GP1=0,C_USE_DIFF_RW_CLK_GP2=0,C_USE_DIFF_RW_CLK_GP3=0,C_USE_DIFF_RW_CLK_GP4=0,C_USE_DIFF_RW_CLK_GP5=0,C_USE_DIFF_RW_CLK_GP6=0,C_EN_FIFO_ENET0=0,C_EN_FIFO_ENET1=0,C_EN_FIFO_ENET2=0,C_EN_FIFO_ENET3=0,C_PL_CLK0_BUF=TRUE,C_PL_CLK1_BUF=FALSE,C_PL_CLK2_BUF=FALSE,C_PL_CLK3_BUF=FALSE,C_TRACE_PIPELINE_WIDTH=8,C_EN_EMIO_TRACE=0,C_TRACE_DATA_WIDTH=32,C_USE_DEBUG_TEST=0,C_SD0_INTERNAL_BUS_WIDTH=5,C_SD1_INTERNAL_BUS_WIDTH=5,C_NUM_F2P_0_INTR_INPUTS=1" &
",C_NUM_F2P_1_INTR_INPUTS=1,C_EMIO_GPIO_WIDTH=1,C_NUM_FABRIC_RESETS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF pl_clk0: SIGNAL IS "XIL_INTERFACENAME PL_CLK0, FREQ_HZ 99999001, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design2023_1_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF pl_clk0: SIGNAL IS "xilinx.com:signal:clock:1.0 PL_CLK0 CLK";
BEGIN
U0 : zynq_ultra_ps_e_v3_5_0_zynq_ultra_ps_e
GENERIC MAP (
C_DP_USE_AUDIO => 0,
C_DP_USE_VIDEO => 0,
C_MAXIGP0_DATA_WIDTH => 128,
C_MAXIGP1_DATA_WIDTH => 128,
C_MAXIGP2_DATA_WIDTH => 32,
C_SAXIGP0_DATA_WIDTH => 128,
C_SAXIGP1_DATA_WIDTH => 128,
C_SAXIGP2_DATA_WIDTH => 128,
C_SAXIGP3_DATA_WIDTH => 128,
C_SAXIGP4_DATA_WIDTH => 128,
C_SAXIGP5_DATA_WIDTH => 128,
C_SAXIGP6_DATA_WIDTH => 128,
C_USE_DIFF_RW_CLK_GP0 => 0,
C_USE_DIFF_RW_CLK_GP1 => 0,
C_USE_DIFF_RW_CLK_GP2 => 0,
C_USE_DIFF_RW_CLK_GP3 => 0,
C_USE_DIFF_RW_CLK_GP4 => 0,
C_USE_DIFF_RW_CLK_GP5 => 0,
C_USE_DIFF_RW_CLK_GP6 => 0,
C_EN_FIFO_ENET0 => "0",
C_EN_FIFO_ENET1 => "0",
C_EN_FIFO_ENET2 => "0",
C_EN_FIFO_ENET3 => "0",
C_PL_CLK0_BUF => "TRUE",
C_PL_CLK1_BUF => "FALSE",
C_PL_CLK2_BUF => "FALSE",
C_PL_CLK3_BUF => "FALSE",
C_TRACE_PIPELINE_WIDTH => 8,
C_EN_EMIO_TRACE => 0,
C_TRACE_DATA_WIDTH => 32,
C_USE_DEBUG_TEST => 0,
C_SD0_INTERNAL_BUS_WIDTH => 5,
C_SD1_INTERNAL_BUS_WIDTH => 5,
C_NUM_F2P_0_INTR_INPUTS => 1,
C_NUM_F2P_1_INTR_INPUTS => 1,
C_EMIO_GPIO_WIDTH => 1,
C_NUM_FABRIC_RESETS => 0
)
PORT MAP (
maxihpm0_fpd_aclk => '0',
maxigp0_awready => '0',
maxigp0_wready => '0',
maxigp0_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
maxigp0_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
maxigp0_bvalid => '0',
maxigp0_arready => '0',
maxigp0_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
maxigp0_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
maxigp0_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
maxigp0_rlast => '0',
maxigp0_rvalid => '0',
maxihpm1_fpd_aclk => '0',
maxigp1_awready => '0',
maxigp1_wready => '0',
maxigp1_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
maxigp1_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
maxigp1_bvalid => '0',
maxigp1_arready => '0',
maxigp1_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
maxigp1_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
maxigp1_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
maxigp1_rlast => '0',
maxigp1_rvalid => '0',
maxihpm0_lpd_aclk => '0',
maxigp2_awready => '0',
maxigp2_wready => '0',
maxigp2_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
maxigp2_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
maxigp2_bvalid => '0',
maxigp2_arready => '0',
maxigp2_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
maxigp2_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
maxigp2_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
maxigp2_rlast => '0',
maxigp2_rvalid => '0',
saxihpc0_fpd_rclk => '0',
saxihpc0_fpd_wclk => '0',
saxihpc0_fpd_aclk => '0',
saxigp0_aruser => '0',
saxigp0_awuser => '0',
saxigp0_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp0_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp0_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp0_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp0_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp0_awlock => '0',
saxigp0_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp0_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp0_awvalid => '0',
saxigp0_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxigp0_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxigp0_wlast => '0',
saxigp0_wvalid => '0',
ddrc_ext_refresh_rank0_req => '0',
ddrc_ext_refresh_rank1_req => '0',
ddrc_refresh_pl_clk => '0',
saxigp0_bready => '0',
saxigp0_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp0_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp0_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp0_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp0_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp0_arlock => '0',
saxigp0_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp0_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp0_arvalid => '0',
saxigp0_rready => '0',
saxigp0_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp0_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxihpc1_fpd_rclk => '0',
saxihpc1_fpd_wclk => '0',
saxihpc1_fpd_aclk => '0',
saxigp1_aruser => '0',
saxigp1_awuser => '0',
saxigp1_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp1_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp1_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp1_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp1_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp1_awlock => '0',
saxigp1_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp1_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp1_awvalid => '0',
saxigp1_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxigp1_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxigp1_wlast => '0',
saxigp1_wvalid => '0',
saxigp1_bready => '0',
saxigp1_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp1_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp1_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp1_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp1_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp1_arlock => '0',
saxigp1_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp1_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp1_arvalid => '0',
saxigp1_rready => '0',
saxigp1_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp1_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxihp0_fpd_rclk => '0',
saxihp0_fpd_wclk => '0',
saxihp0_fpd_aclk => '0',
saxigp2_aruser => '0',
saxigp2_awuser => '0',
saxigp2_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp2_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp2_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp2_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp2_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp2_awlock => '0',
saxigp2_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp2_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp2_awvalid => '0',
saxigp2_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxigp2_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxigp2_wlast => '0',
saxigp2_wvalid => '0',
saxigp2_bready => '0',
saxigp2_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp2_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp2_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp2_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp2_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp2_arlock => '0',
saxigp2_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp2_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp2_arvalid => '0',
saxigp2_rready => '0',
saxigp2_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp2_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxihp1_fpd_rclk => '0',
saxihp1_fpd_wclk => '0',
saxihp1_fpd_aclk => '0',
saxigp3_aruser => '0',
saxigp3_awuser => '0',
saxigp3_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp3_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp3_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp3_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp3_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp3_awlock => '0',
saxigp3_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp3_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp3_awvalid => '0',
saxigp3_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxigp3_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxigp3_wlast => '0',
saxigp3_wvalid => '0',
saxigp3_bready => '0',
saxigp3_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp3_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp3_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp3_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp3_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp3_arlock => '0',
saxigp3_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp3_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp3_arvalid => '0',
saxigp3_rready => '0',
saxigp3_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp3_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxihp2_fpd_rclk => '0',
saxihp2_fpd_wclk => '0',
saxihp2_fpd_aclk => '0',
saxigp4_aruser => '0',
saxigp4_awuser => '0',
saxigp4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp4_awlock => '0',
saxigp4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp4_awvalid => '0',
saxigp4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxigp4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxigp4_wlast => '0',
saxigp4_wvalid => '0',
saxigp4_bready => '0',
saxigp4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp4_arlock => '0',
saxigp4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp4_arvalid => '0',
saxigp4_rready => '0',
saxigp4_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp4_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxihp3_fpd_rclk => '0',
saxihp3_fpd_wclk => '0',
saxihp3_fpd_aclk => '0',
saxigp5_aruser => '0',
saxigp5_awuser => '0',
saxigp5_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp5_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp5_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp5_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp5_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp5_awlock => '0',
saxigp5_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp5_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp5_awvalid => '0',
saxigp5_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxigp5_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxigp5_wlast => '0',
saxigp5_wvalid => '0',
saxigp5_bready => '0',
saxigp5_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp5_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp5_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp5_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp5_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp5_arlock => '0',
saxigp5_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp5_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp5_arvalid => '0',
saxigp5_rready => '0',
saxigp5_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp5_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxi_lpd_rclk => '0',
saxi_lpd_wclk => '0',
saxi_lpd_aclk => '0',
saxigp6_aruser => '0',
saxigp6_awuser => '0',
saxigp6_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp6_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp6_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp6_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp6_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp6_awlock => '0',
saxigp6_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp6_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp6_awvalid => '0',
saxigp6_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxigp6_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxigp6_wlast => '0',
saxigp6_wvalid => '0',
saxigp6_bready => '0',
saxigp6_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
saxigp6_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 49)),
saxigp6_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxigp6_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp6_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxigp6_arlock => '0',
saxigp6_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp6_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxigp6_arvalid => '0',
saxigp6_rready => '0',
saxigp6_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxigp6_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxiacp_fpd_aclk => '0',
saxiacp_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxiacp_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxiacp_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
saxiacp_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 40)),
saxiacp_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxiacp_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxiacp_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxiacp_awlock => '0',
saxiacp_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxiacp_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxiacp_awvalid => '0',
saxiacp_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
saxiacp_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
saxiacp_wlast => '0',
saxiacp_wvalid => '0',
saxiacp_bready => '0',
saxiacp_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
saxiacp_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 40)),
saxiacp_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
saxiacp_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxiacp_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
saxiacp_arlock => '0',
saxiacp_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxiacp_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
saxiacp_arvalid => '0',
saxiacp_rready => '0',
saxiacp_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
saxiacp_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_aclk => '0',
sacefpd_wuser => '0',
sacefpd_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
sacefpd_awsnoop => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
sacefpd_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
sacefpd_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
sacefpd_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
sacefpd_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
sacefpd_awdomain => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
sacefpd_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
sacefpd_awbar => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
sacefpd_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 44)),
sacefpd_awlock => '0',
sacefpd_awvalid => '0',
sacefpd_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
sacefpd_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
sacefpd_wlast => '0',
sacefpd_wvalid => '0',
sacefpd_bready => '0',
sacefpd_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
sacefpd_arsnoop => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
sacefpd_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
sacefpd_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
sacefpd_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
sacefpd_ardomain => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
sacefpd_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
sacefpd_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
sacefpd_arbar => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
sacefpd_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 44)),
sacefpd_arlock => '0',
sacefpd_arvalid => '0',
sacefpd_rready => '0',
sacefpd_acready => '0',
sacefpd_cddata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
sacefpd_cdlast => '0',
sacefpd_cdvalid => '0',
sacefpd_crresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
sacefpd_crvalid => '0',
sacefpd_wack => '0',
sacefpd_rack => '0',
emio_can0_phy_rx => '0',
emio_can1_phy_rx => '0',
emio_enet0_gmii_rx_clk => '0',
emio_enet0_gmii_crs => '0',
emio_enet0_gmii_col => '0',
emio_enet0_gmii_rxd => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet0_gmii_rx_er => '0',
emio_enet0_gmii_rx_dv => '0',
emio_enet0_gmii_tx_clk => '0',
emio_enet0_mdio_i => '0',
emio_enet1_gmii_rx_clk => '0',
emio_enet1_gmii_crs => '0',
emio_enet1_gmii_col => '0',
emio_enet1_gmii_rxd => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet1_gmii_rx_er => '0',
emio_enet1_gmii_rx_dv => '0',
emio_enet1_gmii_tx_clk => '0',
emio_enet1_mdio_i => '0',
emio_enet2_gmii_rx_clk => '0',
emio_enet2_gmii_crs => '0',
emio_enet2_gmii_col => '0',
emio_enet2_gmii_rxd => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet2_gmii_rx_er => '0',
emio_enet2_gmii_rx_dv => '0',
emio_enet2_gmii_tx_clk => '0',
emio_enet2_mdio_i => '0',
emio_enet3_gmii_rx_clk => '0',
emio_enet3_gmii_crs => '0',
emio_enet3_gmii_col => '0',
emio_enet3_gmii_rxd => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet3_gmii_rx_er => '0',
emio_enet3_gmii_rx_dv => '0',
emio_enet3_gmii_tx_clk => '0',
emio_enet3_mdio_i => '0',
emio_enet0_tx_r_data_rdy => '0',
emio_enet0_tx_r_valid => '0',
emio_enet0_tx_r_data => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet0_tx_r_sop => '1',
emio_enet0_tx_r_eop => '1',
emio_enet0_tx_r_err => '0',
emio_enet0_tx_r_underflow => '0',
emio_enet0_tx_r_flushed => '0',
emio_enet0_tx_r_control => '0',
emio_enet0_dma_tx_status_tog => '0',
emio_enet0_rx_w_overflow => '0',
emio_enet1_tx_r_data_rdy => '0',
emio_enet1_tx_r_valid => '0',
emio_enet1_tx_r_data => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet1_tx_r_sop => '1',
emio_enet1_tx_r_eop => '1',
emio_enet1_tx_r_err => '0',
emio_enet1_tx_r_underflow => '0',
emio_enet1_tx_r_flushed => '0',
emio_enet1_tx_r_control => '0',
emio_enet1_dma_tx_status_tog => '0',
emio_enet1_rx_w_overflow => '0',
emio_enet2_tx_r_data_rdy => '0',
emio_enet2_tx_r_valid => '0',
emio_enet2_tx_r_data => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet2_tx_r_sop => '1',
emio_enet2_tx_r_eop => '1',
emio_enet2_tx_r_err => '0',
emio_enet2_tx_r_underflow => '0',
emio_enet2_tx_r_flushed => '0',
emio_enet2_tx_r_control => '0',
emio_enet2_dma_tx_status_tog => '0',
emio_enet2_rx_w_overflow => '0',
emio_enet3_tx_r_data_rdy => '0',
emio_enet3_tx_r_valid => '0',
emio_enet3_tx_r_data => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
emio_enet3_tx_r_sop => '1',
emio_enet3_tx_r_eop => '1',
emio_enet3_tx_r_err => '0',
emio_enet3_tx_r_underflow => '0',
emio_enet3_tx_r_flushed => '0',
emio_enet3_tx_r_control => '0',
emio_enet3_dma_tx_status_tog => '0',
emio_enet3_rx_w_overflow => '0',
emio_enet0_tsu_inc_ctrl => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
emio_enet1_tsu_inc_ctrl => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
emio_enet2_tsu_inc_ctrl => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
emio_enet3_tsu_inc_ctrl => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
fmio_gem_tsu_clk_from_pl => '0',
emio_enet_tsu_clk => '0',
emio_enet0_ext_int_in => '0',
emio_enet1_ext_int_in => '0',
emio_enet2_ext_int_in => '0',
emio_enet3_ext_int_in => '0',
emio_gpio_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
emio_i2c0_scl_i => '0',
emio_i2c0_sda_i => '0',
emio_i2c1_scl_i => '0',
emio_i2c1_sda_i => '0',
emio_uart0_rxd => '0',
emio_uart0_ctsn => '0',
emio_uart0_dsrn => '0',
emio_uart0_dcdn => '0',
emio_uart0_rin => '0',
emio_uart1_rxd => '0',
emio_uart1_ctsn => '0',
emio_uart1_dsrn => '0',
emio_uart1_dcdn => '0',
emio_uart1_rin => '0',
emio_sdio0_fb_clk_in => '0',
emio_sdio0_cmdin => '0',
emio_sdio0_datain => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
emio_sdio0_cd_n => '0',
emio_sdio0_wp => '1',
emio_sdio1_fb_clk_in => '0',
emio_sdio1_cmdin => '0',
emio_sdio1_datain => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
emio_sdio1_cd_n => '0',
emio_sdio1_wp => '1',
emio_spi0_sclk_i => '0',
emio_spi0_m_i => '0',
emio_spi0_s_i => '0',
emio_spi0_ss_i_n => '1',
emio_spi1_sclk_i => '0',
emio_spi1_m_i => '0',
emio_spi1_s_i => '0',
emio_spi1_ss_i_n => '1',
pl_ps_trace_clk => '0',
emio_ttc0_clk_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
emio_ttc1_clk_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
emio_ttc2_clk_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
emio_ttc3_clk_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
emio_wdt0_clk_i => '0',
emio_wdt1_clk_i => '0',
emio_hub_port_overcrnt_usb3_0 => '0',
emio_hub_port_overcrnt_usb3_1 => '0',
emio_hub_port_overcrnt_usb2_0 => '0',
emio_hub_port_overcrnt_usb2_1 => '0',
adma_fci_clk => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
pl2adma_cvld => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
pl2adma_tack => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
perif_gdma_clk => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
perif_gdma_cvld => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
perif_gdma_tack => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
pl_clock_stop => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
pll_aux_refclk_lpd => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
pll_aux_refclk_fpd => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
dp_s_axis_audio_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
dp_s_axis_audio_tid => '0',
dp_s_axis_audio_tvalid => '0',
dp_m_axis_mixed_audio_tready => '0',
dp_s_axis_audio_clk => '0',
dp_live_video_in_vsync => '0',
dp_live_video_in_hsync => '0',
dp_live_video_in_de => '0',
dp_live_video_in_pixel1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
dp_video_in_clk => '0',
dp_aux_data_in => '0',
dp_live_gfx_alpha_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dp_live_gfx_pixel1_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
dp_hot_plug_detect => '0',
dp_external_custom_event1 => '0',
dp_external_custom_event2 => '0',
dp_external_vsync_event => '0',
pl_ps_eventi => '0',
pl_ps_apugic_irq => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
pl_ps_apugic_fiq => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
rpu_eventi0 => '0',
rpu_eventi1 => '0',
nfiq0_lpd_rpu => '1',
nfiq1_lpd_rpu => '1',
nirq0_lpd_rpu => '1',
nirq1_lpd_rpu => '1',
stm_event => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 60)),
pl_ps_trigger_0 => '0',
pl_ps_trigger_1 => '0',
pl_ps_trigger_2 => '0',
pl_ps_trigger_3 => '0',
pl_ps_trigack_0 => '0',
pl_ps_trigack_1 => '0',
pl_ps_trigack_2 => '0',
pl_ps_trigack_3 => '0',
ftm_gpi => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
pl_ps_irq0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
pl_ps_irq1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
pl_pmu_gpi => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
aib_pmu_afifm_fpd_ack => '0',
aib_pmu_afifm_lpd_ack => '0',
pmu_error_from_pl => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
pl_acpinact => '0',
pl_clk0 => pl_clk0,
test_adc_clk => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
test_adc_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
test_adc2_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
test_dclk => '0',
test_den => '0',
test_dwe => '0',
test_daddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
test_di => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
test_convst => '0',
pstp_pl_clk => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
pstp_pl_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
pstp_pl_ts => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
fmio_test_gem_scanmux_1 => '0',
fmio_test_gem_scanmux_2 => '0',
test_char_mode_fpd_n => '0',
test_char_mode_lpd_n => '0',
fmio_test_io_char_scan_clock => '0',
fmio_test_io_char_scanenable => '0',
fmio_test_io_char_scan_in => '0',
fmio_test_io_char_scan_reset_n => '0',
fmio_char_afifslpd_test_select_n => '0',
fmio_char_afifslpd_test_input => '0',
fmio_char_afifsfpd_test_select_n => '0',
fmio_char_afifsfpd_test_input => '0',
io_char_audio_in_test_data => '0',
io_char_audio_mux_sel_n => '0',
io_char_video_in_test_data => '0',
io_char_video_mux_sel_n => '0',
fmio_test_qspi_scanmux_1_n => '0',
fmio_test_sdio_scanmux_1 => '0',
fmio_test_sdio_scanmux_2 => '0',
fmio_sd0_dll_test_in_n => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
fmio_sd1_dll_test_in_n => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
test_pl_scan_chopper_si => '0',
test_pl_scan_chopper_trig => '0',
test_pl_scan_clk0 => '0',
test_pl_scan_clk1 => '0',
test_pl_scan_edt_clk => '0',
test_pl_scan_edt_in_apu => '0',
test_pl_scan_edt_in_cpu => '0',
test_pl_scan_edt_in_ddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
test_pl_scan_edt_in_fp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
test_pl_scan_edt_in_gpu => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
test_pl_scan_edt_in_lp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
test_pl_scan_edt_in_usb3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
test_pl_scan_edt_update => '0',
test_pl_scan_reset_n => '0',
test_pl_scanenable => '0',
test_pl_scan_pll_reset => '0',
test_pl_scan_spare_in0 => '0',
test_pl_scan_spare_in1 => '0',
test_pl_scan_wrap_clk => '0',
test_pl_scan_wrap_ishift => '0',
test_pl_scan_wrap_oshift => '0',
test_pl_scan_slcr_config_clk => '0',
test_pl_scan_slcr_config_rstn => '0',
test_pl_scan_slcr_config_si => '0',
test_pl_scan_spare_in2 => '0',
test_pl_scanenable_slcr_en => '0',
tst_rtc_calibreg_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 21)),
tst_rtc_calibreg_we => '0',
tst_rtc_clk => '0',
tst_rtc_testclock_select_n => '0',
tst_rtc_timesetreg_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
tst_rtc_disable_bat_op => '0',
tst_rtc_osc_cntrl_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
tst_rtc_osc_cntrl_we => '0',
tst_rtc_sec_reload => '0',
tst_rtc_timesetreg_we => '0',
tst_rtc_testmode_n => '0',
test_usb0_funcmux_0_n => '0',
test_usb1_funcmux_0_n => '0',
test_usb0_scanmux_0_n => '0',
test_usb1_scanmux_0_n => '0',
pl_lpd_pll_test_ck_sel_n => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
pl_lpd_pll_test_fract_clk_sel_n => '0',
pl_lpd_pll_test_fract_en_n => '0',
pl_lpd_pll_test_mux_sel => '0',
pl_lpd_pll_test_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
pl_fpd_pll_test_ck_sel_n => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
pl_fpd_pll_test_fract_clk_sel_n => '0',
pl_fpd_pll_test_fract_en_n => '0',
pl_fpd_pll_test_mux_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
pl_fpd_pll_test_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
fmio_char_gem_selection => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
fmio_char_gem_test_select_n => '0',
fmio_char_gem_test_input => '0',
test_pl2ddr_dcd_sample_pulse => '0',
test_bscan_en_n => '0',
test_bscan_tdi => '0',
test_bscan_updatedr => '0',
test_bscan_shiftdr => '0',
test_bscan_reset_tap_b => '0',
test_bscan_misr_jtag_load => '0',
test_bscan_intest => '0',
test_bscan_extest => '0',
test_bscan_clockdr => '0',
test_bscan_ac_mode => '0',
test_bscan_ac_test => '0',
test_bscan_init_memory => '0',
test_bscan_mode_c => '0',
i_dbg_l0_txclk => '0',
i_dbg_l0_rxclk => '0',
i_dbg_l1_txclk => '0',
i_dbg_l1_rxclk => '0',
i_dbg_l2_txclk => '0',
i_dbg_l2_rxclk => '0',
i_dbg_l3_txclk => '0',
i_dbg_l3_rxclk => '0',
i_afe_rx_symbol_clk_by_2_pl => '0',
pl_fpd_spare_0_in => '0',
pl_fpd_spare_1_in => '0',
pl_fpd_spare_2_in => '0',
pl_fpd_spare_3_in => '0',
pl_fpd_spare_4_in => '0',
pl_lpd_spare_0_in => '0',
pl_lpd_spare_1_in => '0',
pl_lpd_spare_2_in => '0',
pl_lpd_spare_3_in => '0',
pl_lpd_spare_4_in => '0',
i_afe_pll_pd_hs_clock_r => '0',
i_afe_mode => '0',
i_bgcal_afe_mode => '0',
i_afe_cmn_bg_enable_low_leakage => '0',
i_afe_cmn_bg_iso_ctrl_bar => '0',
i_afe_cmn_bg_pd => '0',
i_afe_cmn_bg_pd_bg_ok => '0',
i_afe_cmn_bg_pd_ptat => '0',
i_afe_cmn_calib_en_iconst => '0',
i_afe_cmn_calib_enable_low_leakage => '0',
i_afe_cmn_calib_iso_ctrl_bar => '0',
i_afe_rx_rxpma_rstb => '0',
i_afe_rx_uphy_restore_calcode_data => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
i_afe_rx_pipe_rxeqtraining => '0',
i_afe_rx_iso_hsrx_ctrl_bar => '0',
i_afe_rx_iso_lfps_ctrl_bar => '0',
i_afe_rx_iso_sigdet_ctrl_bar => '0',
i_afe_rx_hsrx_clock_stop_req => '0',
i_pll_afe_mode => '0',
i_afe_pll_coarse_code => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
i_afe_pll_en_clock_hs_div2 => '0',
i_afe_pll_fbdiv => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
i_afe_pll_load_fbdiv => '0',
i_afe_pll_pd => '0',
i_afe_pll_pd_pfd => '0',
i_afe_pll_rst_fdbk_div => '0',
i_afe_pll_startloop => '0',
i_afe_pll_v2i_code => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
i_afe_pll_v2i_prog => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
i_afe_pll_vco_cnt_window => '0',
i_afe_rx_mphy_gate_symbol_clk => '0',
i_afe_rx_mphy_mux_hsb_ls => '0',
i_afe_rx_pipe_rx_term_enable => '0',
i_afe_rx_uphy_biasgen_iconst_core_mirror_enable => '0',
i_afe_rx_uphy_biasgen_iconst_io_mirror_enable => '0',
i_afe_rx_uphy_biasgen_irconst_core_mirror_enable => '0',
i_afe_rx_uphy_enable_cdr => '0',
i_afe_rx_uphy_enable_low_leakage => '0',
i_afe_rx_rxpma_refclk_dig => '0',
i_afe_rx_uphy_hsrx_rstb => '0',
i_afe_rx_uphy_pdn_hs_des => '0',
i_afe_rx_uphy_pd_samp_c2c => '0',
i_afe_rx_uphy_pd_samp_c2c_eclk => '0',
i_afe_rx_uphy_pso_clk_lane => '0',
i_afe_rx_uphy_pso_eq => '0',
i_afe_rx_uphy_pso_hsrxdig => '0',
i_afe_rx_uphy_pso_iqpi => '0',
i_afe_rx_uphy_pso_lfpsbcn => '0',
i_afe_rx_uphy_pso_samp_flops => '0',
i_afe_rx_uphy_pso_sigdet => '0',
i_afe_rx_uphy_restore_calcode => '0',
i_afe_rx_uphy_run_calib => '0',
i_afe_rx_uphy_rx_lane_polarity_swap => '0',
i_afe_rx_uphy_startloop_pll => '0',
i_afe_rx_uphy_hsclk_division_factor => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
i_afe_rx_uphy_rx_pma_opmode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
i_afe_tx_enable_hsclk_division => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
i_afe_tx_enable_ldo => '0',
i_afe_tx_enable_ref => '0',
i_afe_tx_enable_supply_hsclk => '0',
i_afe_tx_enable_supply_pipe => '0',
i_afe_tx_enable_supply_serializer => '0',
i_afe_tx_enable_supply_uphy => '0',
i_afe_tx_hs_ser_rstb => '0',
i_afe_tx_hs_symbol => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
i_afe_tx_mphy_tx_ls_data => '0',
i_afe_tx_pipe_tx_enable_idle_mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
i_afe_tx_pipe_tx_enable_lfps => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
i_afe_tx_pipe_tx_enable_rxdet => '0',
i_afe_TX_uphy_txpma_opmode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
i_afe_TX_pmadig_digital_reset_n => '0',
i_afe_TX_serializer_rst_rel => '0',
i_afe_TX_pll_symb_clk_2 => '0',
i_afe_TX_ana_if_rate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
i_afe_TX_en_dig_sublp_mode => '0',
i_afe_TX_LPBK_SEL => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
i_afe_TX_iso_ctrl_bar => '0',
i_afe_TX_ser_iso_ctrl_bar => '0',
i_afe_TX_lfps_clk => '0',
i_afe_TX_serializer_rstb => '0',
i_afe_tx_pipe_tx_fast_est_common_mode => '0'
);
END design2023_1_zynq_ultra_ps_e_0_0_arch;
8) Generated wrapper file for PS8, zynq_ultra_ps_e_v3_5_0
//-----------------------------------------------------------------------------
// zynq_ultra_ps_e_v3_5_0
//
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: zynq_ultra_ps_e_si_v3_5_zynq_ultra_ps_e_si
// Version: v1.00.a
// Description: This is the wrapper file for PS8.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// psu_wrapper.
//
// --zynq_ultra_ps_e_si_v3_5_zynq_ultra_ps_e_si.v
// --PS8.v - Unisim component
//-----------------------------------------------------------------------------
// Author: mishra
//
// History:
//
//mishra 11/03/14 -- First version
// ~~~~~~
// Created the first version v1.00.a
// ^^^^^^
//------------------------------------------------------------------------------
(*PSS_POWER= "<BLOCKTYPE name={PS8}> <PS8><FPD><PROCESSSORS><PROCESSOR name={Cortex A-53} numCores={4} L2Cache={Enable} clockFreq={1199.988037} load={0.5}/><PROCESSOR name={GPU Mali-400 MP} numCores={2} clockFreq={599.994019} load={0.5} /></PROCESSSORS>\
<PLLS><PLL domain={APU} vco={2399.976} /><PLL domain={DDR} vco={2399.976} /><PLL domain={Video} vco={2133.312} /></PLLS>\
<MEMORY memType={LPDDR4} dataWidth={4} clockFreq={479.995} readRate={0.5} writeRate={0.5} cmdAddressActivity={0.5} />\
<SERDES><GT name={PCIe} standard={} lanes={} usageRate={0.5} /><GT name={SATA} standard={} lanes={} usageRate={0.5} /><GT name={Display Port} standard={} lanes={} usageRate={0.5} />clockFreq={} /><GT name={USB3} standard={USB3.0} lanes={0}usageRate={0.5} /><GT name={SGMII} standard={SGMII} lanes={0} usageRate={0.5} /></SERDES>\
<AFI master={0} slave={0} clockFreq={333.333} usageRate={0.5} />\
<FPINTERCONNECT clockFreq={533.328003} Bandwidth={Low} />\
</FPD>\
<LPD><PROCESSSORS><PROCESSOR name={Cortex R-5} usage={Enable} TCM={Enable} OCM={Enable} clockFreq={499.994995} load={0.5}/></PROCESSSORS>\
<PLLS><PLL domain={IO} vco={1999.980} /><PLL domain={RPLL} vco={1599.984} /></PLLS>\
<CSUPMU><Unit name={CSU} usageRate={0.5} clockFreq={180} /><Unit name={PMU} usageRate={0.5} clockFreq={180} /></CSUPMU>\
<GPIO><Bank ioBank={VCC_PSIO0} number={0} io_standard={LVCMOS 1.8V} /><Bank ioBank={VCC_PSIO1} number={0} io_standard={LVCMOS 1.8V} /><Bank ioBank={VCC_PSIO2} number={0} io_standard={LVCMOS 1.8V} /><Bank ioBank={VCC_PSIO3} number={16} io_standard={LVCMOS 1.8V} /></GPIO>\
<IOINTERFACES> <IO name={QSPI} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={NAND 3.1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={USB0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={USB1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth2} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth3} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GPIO 0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GPIO 1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GPIO 2} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GPIO 3} io_standard={} ioBank={VCC_PSIO3} clockFreq={1} inputs={} outputs={} inouts={16} usageRate={0.5}/><IO name={UART0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={UART1} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={1} outputs={1} inouts={0} usageRate={0.5}/><IO name={I2C0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={I2C1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SPI0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SPI1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={CAN0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={CAN1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SD0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SD1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={Trace} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={TTC0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={TTC1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={TTC2} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={TTC3} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={PJTAG} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={DPAUX} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={WDT0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={WDT1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/></IOINTERFACES>\
<AFI master={0} slave={0} clockFreq={333.333} usageRate={0.5} />\
<LPINTERCONNECT clockFreq={499.994995} Bandwidth={High} />\
</LPD>\
</PS8>\
</BLOCKTYPE>/>" *)
(*PSS_IO= "Signal Name, DiffPair Type, DiffPair Signal,Direction, Site Type, IO Standard, Drive (mA), Slew Rate, Pull Type, IBIS Model, ODT, OUTPUT_IMPEDANCE \n\
UART1_TXD, , , OUT, PS_MIO0_500, LVCMOS18, 12, FAST, PULLUP, PS_MIO_LVCMOS18_F_12,, \n\
UART1_RXD, , , IN, PS_MIO1_500, LVCMOS18, 12, FAST, PULLUP, PS_MIO_LVCMOS18_F_12,, \n\
PS_REF_CLK, , , IN, PS_REF_CLK_503, LVCMOS18, 2, SLOW, , PS_MIO_LVCMOS18_S_2,, \n\
PS_JTAG_TCK, , , IN, PS_JTAG_TCK_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_JTAG_TDI, , , IN, PS_JTAG_TDI_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_JTAG_TDO, , , OUT, PS_JTAG_TDO_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_JTAG_TMS, , , IN, PS_JTAG_TMS_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_DONE, , , OUT, PS_DONE_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_ERROR_OUT, , , OUT, PS_ERROR_OUT_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_ERROR_STATUS, , , OUT, PS_ERROR_STATUS_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_INIT_B, , , INOUT, PS_INIT_B_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_MODE0, , , IN, PS_MODE0_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_MODE1, , , IN, PS_MODE1_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_MODE2, , , IN, PS_MODE2_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_MODE3, , , IN, PS_MODE3_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_PADI, , , IN, PS_PADI_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_PADO, , , OUT, PS_PADO_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_POR_B, , , IN, PS_POR_B_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_PROG_B, , , IN, PS_PROG_B_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
PS_SRST_B, , , IN, PS_SRST_B_503, LVCMOS18, 12, FAST, , PS_MIO_LVCMOS18_F_12,, \n\
LPDDR4_RAM_RST_N, , , OUT, PS_DDR_RAM_RST_N_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_CK0, P, LPDDR4_CK_N0, OUT, PS_DDR_CK0_504, LPDDR4, , , ,PS_LPDDR4_CK_OUT40_P, RTT_NONE, 40\n\
LPDDR4_CK_N0, N, LPDDR4_CK0, OUT, PS_DDR_CK_N0_504, LPDDR4, , , ,PS_LPDDR4_CK_OUT40_N, RTT_NONE, 40\n\
LPDDR4_CKE0, , , OUT, PS_DDR_CKE0_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_CS_N0, , , OUT, PS_DDR_CS_N0_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_CK1, P, LPDDR4_CK_N1, OUT, PS_DDR_CK1_504, LPDDR4, , , ,PS_LPDDR4_CK_OUT40_P, RTT_NONE, 40\n\
LPDDR4_CK_N1, N, LPDDR4_CK1, OUT, PS_DDR_CK_N1_504, LPDDR4, , , ,PS_LPDDR4_CK_OUT40_N, RTT_NONE, 40\n\
LPDDR4_ZQ, , , INOUT, PS_DDR_ZQ_504, LPDDR4, , , ,, , \n\
LPDDR4_A0, , , OUT, PS_DDR_A0_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A1, , , OUT, PS_DDR_A1_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A2, , , OUT, PS_DDR_A2_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A3, , , OUT, PS_DDR_A3_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A4, , , OUT, PS_DDR_A4_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A5, , , OUT, PS_DDR_A5_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A10, , , OUT, PS_DDR_A10_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A11, , , OUT, PS_DDR_A11_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A12, , , OUT, PS_DDR_A12_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A13, , , OUT, PS_DDR_A13_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A14, , , OUT, PS_DDR_A14_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_A15, , , OUT, PS_DDR_A15_504, LPDDR4, , , ,PS_LPDDR4_CKE_OUT40, RTT_NONE, 40\n\
LPDDR4_DQS_P0, P, LPDDR4_DQS_N0, INOUT, PS_DDR_DQS_P0_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_P|PS_LPDDR4_DQS_IN40_P, RTT_40, 40\n\
LPDDR4_DQS_P1, P, LPDDR4_DQS_N1, INOUT, PS_DDR_DQS_P1_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_P|PS_LPDDR4_DQS_IN40_P, RTT_40, 40\n\
LPDDR4_DQS_P2, P, LPDDR4_DQS_N2, INOUT, PS_DDR_DQS_P2_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_P|PS_LPDDR4_DQS_IN40_P, RTT_40, 40\n\
LPDDR4_DQS_P3, P, LPDDR4_DQS_N3, INOUT, PS_DDR_DQS_P3_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_P|PS_LPDDR4_DQS_IN40_P, RTT_40, 40\n\
LPDDR4_DQS_N0, N, LPDDR4_DQS_P0, INOUT, PS_DDR_DQS_N0_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_N|PS_LPDDR4_DQS_IN40_N, RTT_40, 40\n\
LPDDR4_DQS_N1, N, LPDDR4_DQS_P1, INOUT, PS_DDR_DQS_N1_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_N|PS_LPDDR4_DQS_IN40_N, RTT_40, 40\n\
LPDDR4_DQS_N2, N, LPDDR4_DQS_P2, INOUT, PS_DDR_DQS_N2_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_N|PS_LPDDR4_DQS_IN40_N, RTT_40, 40\n\
LPDDR4_DQS_N3, N, LPDDR4_DQS_P3, INOUT, PS_DDR_DQS_N3_504, LPDDR4, , , ,PS_LPDDR4_DQS_OUT40_N|PS_LPDDR4_DQS_IN40_N, RTT_40, 40\n\
LPDDR4_DM0, , , OUT, PS_DDR_DM0_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40, RTT_40, 40\n\
LPDDR4_DM1, , , OUT, PS_DDR_DM1_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40, RTT_40, 40\n\
LPDDR4_DM2, , , OUT, PS_DDR_DM2_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40, RTT_40, 40\n\
LPDDR4_DM3, , , OUT, PS_DDR_DM3_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40, RTT_40, 40\n\
LPDDR4_DQ0, , , INOUT, PS_DDR_DQ0_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ1, , , INOUT, PS_DDR_DQ1_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ2, , , INOUT, PS_DDR_DQ2_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ3, , , INOUT, PS_DDR_DQ3_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ4, , , INOUT, PS_DDR_DQ4_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ5, , , INOUT, PS_DDR_DQ5_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ6, , , INOUT, PS_DDR_DQ6_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ7, , , INOUT, PS_DDR_DQ7_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ8, , , INOUT, PS_DDR_DQ8_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ9, , , INOUT, PS_DDR_DQ9_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ10, , , INOUT, PS_DDR_DQ10_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ11, , , INOUT, PS_DDR_DQ11_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ12, , , INOUT, PS_DDR_DQ12_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ13, , , INOUT, PS_DDR_DQ13_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ14, , , INOUT, PS_DDR_DQ14_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ15, , , INOUT, PS_DDR_DQ15_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ16, , , INOUT, PS_DDR_DQ16_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ17, , , INOUT, PS_DDR_DQ17_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ18, , , INOUT, PS_DDR_DQ18_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ19, , , INOUT, PS_DDR_DQ19_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ20, , , INOUT, PS_DDR_DQ20_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ21, , , INOUT, PS_DDR_DQ21_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ22, , , INOUT, PS_DDR_DQ22_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ23, , , INOUT, PS_DDR_DQ23_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ24, , , INOUT, PS_DDR_DQ24_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ25, , , INOUT, PS_DDR_DQ25_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ26, , , INOUT, PS_DDR_DQ26_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ27, , , INOUT, PS_DDR_DQ27_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ28, , , INOUT, PS_DDR_DQ28_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ29, , , INOUT, PS_DDR_DQ29_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ30, , , INOUT, PS_DDR_DQ30_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40\n\
LPDDR4_DQ31, , , INOUT, PS_DDR_DQ31_504, LPDDR4, , , ,PS_LPDDR4_DQ_OUT40|PS_LPDDR4_DQ_IN40, RTT_40, 40" *)
(*PSS_JITTER= "<PSS_EXTERNAL_CLOCKS>\
<EXTERNAL_CLOCK name={PLCLK[0]} clock_external_divide={8} vco_name={RPLL} vco_freq={1599.984} vco_internal_divide={2}/>\
</PSS_EXTERNAL_CLOCKS>" *)
(* CORE_GENERATION_INFO = "zynq_ultra_ps_e_v3_5 ,zynq_ultra_ps_e_v3_5_user_configuration,{ PSU__CAN0__PERIPHERAL__ENABLE=0, PSU__CAN0__GRP_CLK__ENABLE=0, PSU__CAN1__PERIPHERAL__ENABLE=0, PSU__CAN1__GRP_CLK__ENABLE=0, PSU__CAN0_LOOP_CAN1__ENABLE=0, PSU__DPAUX__PERIPHERAL__ENABLE=0, PSU__ENET0__GRP_MDIO__ENABLE=0, PSU__GEM__TSU__ENABLE=0, PSU__ENET0__PERIPHERAL__ENABLE=0, PSU__ENET1__PERIPHERAL__ENABLE=0, PSU__ENET1__GRP_MDIO__ENABLE=0, PSU__FPGA_PL0_ENABLE=1, PSU__FPGA_PL1_ENABLE=0, PSU__FPGA_PL2_ENABLE=0, PSU__FPGA_PL3_ENABLE=0, PSU__ENET2__PERIPHERAL__ENABLE=0, PSU__ENET2__GRP_MDIO__ENABLE=0, PSU__ENET3__PERIPHERAL__ENABLE=0, PSU__ENET3__GRP_MDIO__ENABLE=0, PSU__GPIO_EMIO__PERIPHERAL__ENABLE=0, PSU__GPIO0_MIO__PERIPHERAL__ENABLE=0, PSU__GPIO1_MIO__PERIPHERAL__ENABLE=0, PSU__GPIO2_MIO__PERIPHERAL__ENABLE=0, PSU__I2C0__PERIPHERAL__ENABLE=0, PSU__I2C0__GRP_INT__ENABLE=0, PSU__I2C1__PERIPHERAL__ENABLE=0, PSU__I2C1__GRP_INT__ENABLE=0, PSU__I2C0_LOOP_I2C1__ENABLE=0, PSU__TESTSCAN__PERIPHERAL__ENABLE=0, PSU__PCIE__PERIPHERAL__ENABLE=0, PSU_IMPORT_BOARD_PRESET=, PSU__EP__IP=0, PSU__ACTUAL__IP=1, PSU__NAND__PERIPHERAL__ENABLE=0, PSU__NAND__READY_BUSY__ENABLE=0, PSU__NAND__CHIP_ENABLE__ENABLE=0, PSU__NAND__DATA_STROBE__ENABLE=0, PSU__PJTAG__PERIPHERAL__ENABLE=0, PSU__PMU__PERIPHERAL__ENABLE=0, PSU__PMU__EMIO_GPI__ENABLE=0, PSU__PMU__EMIO_GPO__ENABLE=0, PSU__PMU__GPI0__ENABLE=0, PSU__PMU__GPI1__ENABLE=0, PSU__PMU__GPI2__ENABLE=0, PSU__PMU__GPI3__ENABLE=0, PSU__PMU__GPI4__ENABLE=0, PSU__PMU__GPI5__ENABLE=0, PSU__PMU__GPO0__ENABLE=0, PSU__PMU__GPO1__ENABLE=0, PSU__PMU__GPO2__ENABLE=0\
, PSU__PMU__GPO3__ENABLE=0, PSU__PMU__GPO4__ENABLE=0, PSU__PMU__GPO5__ENABLE=0, PSU__CSU__PERIPHERAL__ENABLE=0, PSU__QSPI__PERIPHERAL__ENABLE=0, PSU__QSPI__GRP_FBCLK__ENABLE=0, PSU__SD0__PERIPHERAL__ENABLE=0, PSU__SD0__GRP_CD__ENABLE=0, PSU__SD0__GRP_POW__ENABLE=0, PSU__SD0__GRP_WP__ENABLE=0, PSU__SD1__PERIPHERAL__ENABLE=0, PSU__SD1__GRP_CD__ENABLE=0, PSU__SD1__GRP_POW__ENABLE=0, PSU__SD1__GRP_WP__ENABLE=0, PSU__SPI0__PERIPHERAL__ENABLE=0, PSU__SPI0__GRP_SS0__ENABLE=0, PSU__SPI0__GRP_SS1__ENABLE=0, PSU__SPI0__GRP_SS2__ENABLE=0, PSU__SPI1__PERIPHERAL__ENABLE=0, PSU__SPI1__GRP_SS0__ENABLE=0, PSU__SPI1__GRP_SS1__ENABLE=0, PSU__SPI1__GRP_SS2__ENABLE=0, PSU__SPI0_LOOP_SPI1__ENABLE=0, PSU__SWDT0__PERIPHERAL__ENABLE=0, PSU__SWDT1__PERIPHERAL__ENABLE=0, PSU__TRACE__PERIPHERAL__ENABLE=0, PSU__TTC0__PERIPHERAL__ENABLE=0, PSU__TTC1__PERIPHERAL__ENABLE=0, PSU__UART1__BAUD_RATE=115200, PSU__TTC2__PERIPHERAL__ENABLE=0, PSU__TTC3__PERIPHERAL__ENABLE=0, PSU__DDRC__AL=0, PSU__DDRC__BANK_ADDR_COUNT=3, PSU__DDRC__BUS_WIDTH=32 Bit, PSU__DDRC__CLOCK_STOP_EN=0, PSU__DDRC__COL_ADDR_COUNT=10, PSU__DDRC__DEVICE_CAPACITY=2048 MBits, PSU__DDRC__DRAM_WIDTH=32 Bits, PSU__DDRC__ECC=Disabled, PSU__DDRC__ENABLE=1, PSU__DDRC__FREQ_MHZ=1, PSU__DDRC__MEMORY_TYPE=LPDDR 4, PSU__DDRC__ROW_ADDR_COUNT=13, PSU__DDRC__SPEED_BIN=LPDDR4_1066, PSU__DDRC__T_FAW=40.0, PSU__DDRC__T_RAS_MIN=42, PSU__DDRC__T_RC=63, PSU__DDRC__T_RCD=10, PSU__DDRC__T_RP=12, PSU__DDRC__TRAIN_DATA_EYE=1\
, PSU__DDRC__TRAIN_READ_GATE=1, PSU__DDRC__TRAIN_WRITE_LEVEL=1, PSU__FP__POWER__ON=1, PSU__PL__POWER__ON=1, PSU__OCM_BANK0__POWER__ON=1, PSU__OCM_BANK1__POWER__ON=1, PSU__OCM_BANK2__POWER__ON=1, PSU__OCM_BANK3__POWER__ON=1, PSU__TCM0A__POWER__ON=1, PSU__TCM0B__POWER__ON=1, PSU__TCM1A__POWER__ON=1, PSU__TCM1B__POWER__ON=1, PSU__RPU__POWER__ON=1, PSU__L2_BANK0__POWER__ON=1, PSU__GPU_PP0__POWER__ON=1, PSU__GPU_PP1__POWER__ON=1, PSU__ACPU0__POWER__ON=1, PSU__ACPU1__POWER__ON=1, PSU__ACPU2__POWER__ON=1, PSU__ACPU3__POWER__ON=1, PSU__UART0__PERIPHERAL__ENABLE=0, PSU__UART1__PERIPHERAL__ENABLE=1, PSU__UART1__PERIPHERAL__IO=MIO 0 .. 1, PSU__UART0_LOOP_UART1__ENABLE=0, PSU__UART0__MODEM__ENABLE=0, PSU__UART1__MODEM__ENABLE=0, PSU__USB0__PERIPHERAL__ENABLE=0, PSU__USB1__PERIPHERAL__ENABLE=0, PSU__CRF_APB__DPLL_CTRL__DIV2=1, PSU__CRF_APB__APLL_CTRL__DIV2=1, PSU__CRL_APB__IOPLL_CTRL__DIV2=1, PSU__CRL_APB__RPLL_CTRL__DIV2=1, PSU__CRF_APB__VPLL_CTRL__DIV2=1, PSU__CRF_APB__APLL_CTRL__FBDIV=72, PSU__CRF_APB__DPLL_CTRL__FBDIV=72, PSU__CRF_APB__VPLL_CTRL__FBDIV=64, PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0=3, PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0=3, PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0=2, PSU__CRF_APB__ACPU_CTRL__DIVISOR0=1, PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0=5, PSU__DISPLAYPORT__PERIPHERAL__ENABLE=0, PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0=2, PSU__CRF_APB__APM_CTRL__DIVISOR0=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0=5, PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0=63, PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0=6, PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1=10\
, PSU__CRF_APB__DDR_CTRL__DIVISOR0=5, PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI0_REF__ENABLE=0, PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI1_REF__ENABLE=0, PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI2_REF__ENABLE=0, PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI3_REF__ENABLE=0, PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI4_REF__ENABLE=0, PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI5_REF__ENABLE=0, PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0=5, PSU__SATA__PERIPHERAL__ENABLE=0, PSU__SATA__LANE0__ENABLE=0, PSU__SATA__LANE1__ENABLE=0, PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0=8, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0=20, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0=1, PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0=3, PSU__CRL_APB__AFI6__ENABLE=0, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0=5, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1=15, PSU__CRL_APB__USB3__ENABLE=0, PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0=5, PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0=2, PSU__CRL_APB__IOPLL_CTRL__FBDIV=60, PSU__CRL_APB__RPLL_CTRL__FBDIV=48, PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0=2, PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0=2, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1=1\
, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0=5, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0=10, PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0=6, PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0=2, PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0=3, PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0=3, PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0=3, PSU__CRL_APB__PCAP_CTRL__DIVISOR0=5, PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0=10, PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0=2, PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0=4, PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__APLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__DPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__VPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__ACPU_CTRL__SRCSEL=APLL, PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL=VPLL\
, PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL=VPLL, PSU__CRF_APB__DDR_CTRL__SRCSEL=DPLL, PSU__CRF_APB__GPU_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__SATA_REF_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__PL0_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__PL1_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__PL2_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__PL3_REF_CTRL__SRCSEL=RPLL, PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL=VPLL, PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__IOPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRL_APB__RPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__UART0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__UART1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL=RPLL, PSU__CRL_APB__CPU_R5_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL=RPLL, PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL=SysOsc, PSU__CRL_APB__PCAP_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__NAND_REF_CTRL__SRCSEL=IOPLL\
, PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DLL_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__AMS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL=IOPLL, PSU__IOU_SLCR__WDT_CLK_SEL__SELECT=APB, PSU__FPD_SLCR__WDT_CLK_SEL__SELECT=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL=APB, PSU__CRF_APB__APLL_FRAC_CFG__ENABLED=0, PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED=0, PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED=0, PSU__OVERRIDE__BASIC_CLOCK=0, PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ=1199.988037, PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ=320, PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ=25, PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ=27, PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ=239.997604, PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ=250, PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ=250, PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ=250, PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ=250\
, PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ=300, PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ=200, PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ=266.664001, PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ=180, PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ=199.998001, PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ=999.989990, PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ=49.999500, PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ=33.333000, PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ=20, PSU__CRF_APB__ACPU_CTRL__FREQMHZ=1200, PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ=250, PSU__CRF_APB__APM_CTRL__FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ=300, PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ=25, PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ=27, PSU__CRF_APB__DDR_CTRL__FREQMHZ=533, PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ=250, PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ=600\
, PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ=533.333, PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ=100, PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ=250, PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ=300, PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ=500, PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ=267, PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ=180, PSU__CRL_APB__PCAP_CTRL__FREQMHZ=200, PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ=100, PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ=500, PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ=250, PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ=1500, PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ=50, PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ=20, PSU__CSU__CSU_TAMPER_0__ENABLE=0, PSU__CSU__CSU_TAMPER_1__ENABLE=0, PSU__CSU__CSU_TAMPER_2__ENABLE=0, PSU__CSU__CSU_TAMPER_3__ENABLE=0, PSU__CSU__CSU_TAMPER_4__ENABLE=0, PSU__CSU__CSU_TAMPER_5__ENABLE=0, PSU__CSU__CSU_TAMPER_6__ENABLE=0, PSU__CSU__CSU_TAMPER_7__ENABLE=0, PSU__CSU__CSU_TAMPER_8__ENABLE=0, PSU__CSU__CSU_TAMPER_9__ENABLE=0, PSU__CSU__CSU_TAMPER_10__ENABLE=0, PSU__CSU__CSU_TAMPER_11__ENABLE=0\
, PSU__CSU__CSU_TAMPER_12__ENABLE=0, PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM=0, PSU__GEN_IPI_0__MASTER=APU, PSU__GEN_IPI_1__MASTER=RPU0, PSU__GEN_IPI_2__MASTER=RPU1, PSU__GEN_IPI_3__MASTER=PMU, PSU__GEN_IPI_4__MASTER=PMU, PSU__GEN_IPI_5__MASTER=PMU, PSU__GEN_IPI_6__MASTER=PMU, PSU__GEN_IPI_7__MASTER=NONE, PSU__GEN_IPI_8__MASTER=NONE, PSU__GEN_IPI_9__MASTER=NONE, PSU__GEN_IPI_10__MASTER=NONE, PSU__PROTECTION__SUBSYSTEMS=PMU Firmware:PMU|Secure Subsystem:, PSU__PROTECTION__DDR_SEGMENTS=NONE, PSU__PROTECTION__OCM_SEGMENTS=NONE, PSU__PROTECTION__LPD_SEGMENTS=SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem, PSU__PROTECTION__FPD_SEGMENTS=SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem, PSU__PROTECTION__DEBUG=0, PSU__PROTECTION__PRESUBSYSTEMS=NONE, PSU__DDR_QOS_ENABLE=0, PSU__DDR_QOS_RD_LPR_THRSHLD=, PSU__DDR_QOS_RD_HPR_THRSHLD=, PSU__DDR_QOS_WR_THRSHLD=, PSU__DDR_QOS_HP0_RDQOS=, PSU__DDR_QOS_HP0_WRQOS=, PSU__DDR_QOS_HP1_RDQOS=, PSU__DDR_QOS_HP1_WRQOS=, PSU__DDR_QOS_HP2_RDQOS=, PSU__DDR_QOS_HP2_WRQOS=, PSU__DDR_QOS_HP3_RDQOS=, PSU__DDR_QOS_HP3_WRQOS= }" *)
(* HW_HANDOFF = "design2023_1_zynq_ultra_ps_e_0_0.hwdef" *)
module zynq_ultra_ps_e_v3_5_0_zynq_ultra_ps_e
#(
parameter C_MAXIGP0_DATA_WIDTH = 128,
parameter C_MAXIGP1_DATA_WIDTH = 128,
parameter C_MAXIGP2_DATA_WIDTH = 128,
parameter C_SAXIGP0_DATA_WIDTH = 128,
parameter C_SAXIGP1_DATA_WIDTH = 128,
parameter C_SAXIGP2_DATA_WIDTH = 128,
parameter C_SAXIGP3_DATA_WIDTH = 128,
parameter C_SAXIGP4_DATA_WIDTH = 128,
parameter C_SAXIGP5_DATA_WIDTH = 128,
parameter C_SAXIGP6_DATA_WIDTH = 128,
parameter C_SD0_INTERNAL_BUS_WIDTH = 8,
parameter C_SD1_INTERNAL_BUS_WIDTH = 8,
parameter C_PL_CLK0_BUF = "true",
parameter C_PL_CLK1_BUF = "true",
parameter C_PL_CLK2_BUF = "true",
parameter C_PL_CLK3_BUF = "true",
parameter integer C_NUM_F2P_0_INTR_INPUTS = 0,
parameter integer C_NUM_F2P_1_INTR_INPUTS = 0,
parameter C_NUM_FABRIC_RESETS = 1,
parameter C_EMIO_GPIO_WIDTH = 96,
//parameter C_TRISTATE_INVERTED = 1,
parameter C_USE_DIFF_RW_CLK_GP0 = 0,
parameter C_USE_DIFF_RW_CLK_GP1 = 0,
parameter C_USE_DIFF_RW_CLK_GP2 = 0,
parameter C_USE_DIFF_RW_CLK_GP3 = 0,
parameter C_USE_DIFF_RW_CLK_GP4 = 0,
parameter C_USE_DIFF_RW_CLK_GP5 = 0,
parameter C_USE_DIFF_RW_CLK_GP6 = 0,
parameter C_TRACE_PIPELINE_WIDTH = 8,
parameter C_EN_EMIO_TRACE = 0,
parameter C_EN_FIFO_ENET0 = "0",
parameter C_EN_FIFO_ENET1 = "0",
parameter C_EN_FIFO_ENET2 = "0",
parameter C_EN_FIFO_ENET3 = "0",
parameter C_TRACE_DATA_WIDTH = 32,
parameter C_USE_DEBUG_TEST = 0,
parameter C_DP_USE_AUDIO = 0,
parameter C_DP_USE_VIDEO = 0
)
(
// maxigp0
input wire maxihpm0_fpd_aclk,
output wire dp_video_ref_clk,
output wire dp_audio_ref_clk,
output wire [15:0] maxigp0_awid,
output wire [39:0] maxigp0_awaddr,
output wire [7:0] maxigp0_awlen,
output wire [2:0] maxigp0_awsize,
output wire [1:0] maxigp0_awburst,
output wire maxigp0_awlock,
output wire [3:0] maxigp0_awcache,
output wire [2:0] maxigp0_awprot,
output wire maxigp0_awvalid,
output wire [15:0] maxigp0_awuser,
input wire maxigp0_awready,
output wire [C_MAXIGP0_DATA_WIDTH-1 :0] maxigp0_wdata,
output wire [(C_MAXIGP0_DATA_WIDTH/8)-1 :0] maxigp0_wstrb,
output wire maxigp0_wlast,
output wire maxigp0_wvalid,
input wire maxigp0_wready,
input wire [15:0] maxigp0_bid,
input wire [1:0] maxigp0_bresp,
input wire maxigp0_bvalid,
output wire maxigp0_bready,
output wire [15:0] maxigp0_arid,
output wire [39:0] maxigp0_araddr,
output wire [7:0] maxigp0_arlen,
output wire [2:0] maxigp0_arsize,
output wire [1:0] maxigp0_arburst,
output wire maxigp0_arlock,
output wire [3:0] maxigp0_arcache,
output wire [2:0] maxigp0_arprot,
output wire maxigp0_arvalid,
output wire [15:0] maxigp0_aruser,
input wire maxigp0_arready,
input wire [15:0] maxigp0_rid,
input wire [C_MAXIGP0_DATA_WIDTH-1 :0] maxigp0_rdata,
input wire [1:0] maxigp0_rresp,
input wire maxigp0_rlast,
input wire maxigp0_rvalid,
output wire maxigp0_rready,
output wire [3:0] maxigp0_awqos,
output wire [3:0] maxigp0_arqos,
// maxigp1
input wire maxihpm1_fpd_aclk,
output wire [15:0] maxigp1_awid,
output wire [39:0] maxigp1_awaddr,
output wire [7:0] maxigp1_awlen,
output wire [2:0] maxigp1_awsize,
output wire [1:0] maxigp1_awburst,
output wire maxigp1_awlock,
output wire [3:0] maxigp1_awcache,
output wire [2:0] maxigp1_awprot,
output wire maxigp1_awvalid,
output wire [15:0] maxigp1_awuser,
input wire maxigp1_awready,
output wire [C_MAXIGP1_DATA_WIDTH-1 :0] maxigp1_wdata,
output wire [(C_MAXIGP1_DATA_WIDTH/8)-1 :0] maxigp1_wstrb,
output wire maxigp1_wlast,
output wire maxigp1_wvalid,
input wire maxigp1_wready,
input wire [15:0] maxigp1_bid,
input wire [1:0] maxigp1_bresp,
input wire maxigp1_bvalid,
output wire maxigp1_bready,
output wire [15:0] maxigp1_arid,
output wire [39:0] maxigp1_araddr,
output wire [7:0] maxigp1_arlen,
output wire [2:0] maxigp1_arsize,
output wire [1:0] maxigp1_arburst,
output wire maxigp1_arlock,
output wire [3:0] maxigp1_arcache,
output wire [2:0] maxigp1_arprot,
output wire maxigp1_arvalid,
output wire [15:0] maxigp1_aruser,
input wire maxigp1_arready,
input wire [15:0] maxigp1_rid,
input wire [C_MAXIGP1_DATA_WIDTH-1 :0] maxigp1_rdata,
input wire [1:0] maxigp1_rresp,
input wire maxigp1_rlast,
input wire maxigp1_rvalid,
output wire maxigp1_rready,
output wire [3:0] maxigp1_awqos,
output wire [3:0] maxigp1_arqos,
// maxigp2
input wire maxihpm0_lpd_aclk,
output wire [15:0] maxigp2_awid,
output wire [39:0] maxigp2_awaddr,
output wire [7:0] maxigp2_awlen,
output wire [2:0] maxigp2_awsize,
output wire [1:0] maxigp2_awburst,
output wire maxigp2_awlock,
output wire [3:0] maxigp2_awcache,
output wire [2:0] maxigp2_awprot,
output wire maxigp2_awvalid,
output wire [15:0] maxigp2_awuser,
input wire maxigp2_awready,
output wire [C_MAXIGP2_DATA_WIDTH-1 :0] maxigp2_wdata,
output wire [(C_MAXIGP2_DATA_WIDTH/8)-1 :0] maxigp2_wstrb,
output wire maxigp2_wlast,
output wire maxigp2_wvalid,
input wire maxigp2_wready,
input wire [15:0] maxigp2_bid,
input wire [1:0] maxigp2_bresp,
input wire maxigp2_bvalid,
output wire maxigp2_bready,
output wire [15:0] maxigp2_arid,
output wire [39:0] maxigp2_araddr,
output wire [7:0] maxigp2_arlen,
output wire [2:0] maxigp2_arsize,
output wire [1:0] maxigp2_arburst,
output wire maxigp2_arlock,
output wire [3:0] maxigp2_arcache,
output wire [2:0] maxigp2_arprot,
output wire maxigp2_arvalid,
output wire [15:0] maxigp2_aruser,
input wire maxigp2_arready,
input wire [15:0] maxigp2_rid,
input wire [C_MAXIGP2_DATA_WIDTH-1 :0] maxigp2_rdata,
input wire [1:0] maxigp2_rresp,
input wire maxigp2_rlast,
input wire maxigp2_rvalid,
output wire maxigp2_rready,
output wire [3:0] maxigp2_awqos,
output wire [3:0] maxigp2_arqos,
// saxigp0
input wire saxihpc0_fpd_aclk,
input wire saxihpc0_fpd_rclk,
input wire saxihpc0_fpd_wclk,
input wire saxigp0_aruser,
input wire saxigp0_awuser,
input wire [5:0] saxigp0_awid,
input wire [48:0] saxigp0_awaddr,
input wire [7:0] saxigp0_awlen ,
input wire [2:0] saxigp0_awsize,
input wire [1:0] saxigp0_awburst,
input wire saxigp0_awlock,
input wire [3:0] saxigp0_awcache,
input wire [2:0] saxigp0_awprot,
input wire saxigp0_awvalid,
output wire saxigp0_awready,
input wire [C_SAXIGP0_DATA_WIDTH-1:0] saxigp0_wdata,
input wire [(C_SAXIGP0_DATA_WIDTH/8) -1 :0] saxigp0_wstrb,
input wire saxigp0_wlast,
input wire saxigp0_wvalid,
output wire saxigp0_wready,
output wire [5:0] saxigp0_bid,
output wire [1:0] saxigp0_bresp,
output wire saxigp0_bvalid,
input wire saxigp0_bready,
input wire [5:0] saxigp0_arid,
input wire [48:0] saxigp0_araddr,
input wire [7:0] saxigp0_arlen,
input wire [2:0] saxigp0_arsize,
input wire [1:0] saxigp0_arburst,
input wire saxigp0_arlock,
input wire [3:0] saxigp0_arcache,
input wire [2:0] saxigp0_arprot,
input wire saxigp0_arvalid,
output wire saxigp0_arready,
output wire [5:0] saxigp0_rid,
output wire [C_SAXIGP0_DATA_WIDTH-1:0] saxigp0_rdata,
output wire [1:0] saxigp0_rresp,
output wire saxigp0_rlast,
output wire saxigp0_rvalid,
input wire saxigp0_rready,
input wire [3:0] saxigp0_awqos,
input wire [3:0] saxigp0_arqos,
output wire [7:0] saxigp0_rcount,
output wire [7:0] saxigp0_wcount,
output wire [3:0] saxigp0_racount,
output wire [3:0] saxigp0_wacount,
// saxigp1
input wire saxihpc1_fpd_aclk,
input wire saxihpc1_fpd_rclk,
input wire saxihpc1_fpd_wclk,
input wire saxigp1_aruser,
input wire saxigp1_awuser,
input wire [5:0] saxigp1_awid,
input wire [48:0] saxigp1_awaddr,
input wire [7:0] saxigp1_awlen ,
input wire [2:0] saxigp1_awsize,
input wire [1:0] saxigp1_awburst,
input wire saxigp1_awlock,
input wire [3:0] saxigp1_awcache,
input wire [2:0] saxigp1_awprot,
input wire saxigp1_awvalid,
output wire saxigp1_awready,
input wire [C_SAXIGP1_DATA_WIDTH-1:0] saxigp1_wdata,
input wire [(C_SAXIGP1_DATA_WIDTH/8) -1 :0] saxigp1_wstrb,
input wire saxigp1_wlast,
input wire saxigp1_wvalid,
output wire saxigp1_wready,
output wire [5:0] saxigp1_bid,
output wire [1:0] saxigp1_bresp,
output wire saxigp1_bvalid,
input wire saxigp1_bready,
input wire [5:0] saxigp1_arid,
input wire [48:0] saxigp1_araddr,
input wire [7:0] saxigp1_arlen,
input wire [2:0] saxigp1_arsize,
input wire [1:0] saxigp1_arburst,
input wire saxigp1_arlock,
input wire [3:0] saxigp1_arcache,
input wire [2:0] saxigp1_arprot,
input wire saxigp1_arvalid,
output wire saxigp1_arready,
output wire [5:0] saxigp1_rid,
output wire [C_SAXIGP1_DATA_WIDTH-1:0] saxigp1_rdata,
output wire [1:0] saxigp1_rresp,
output wire saxigp1_rlast,
output wire saxigp1_rvalid,
input wire saxigp1_rready,
input wire [3:0] saxigp1_awqos,
input wire [3:0] saxigp1_arqos,
output wire [7:0] saxigp1_rcount,
output wire [7:0] saxigp1_wcount,
output wire [3:0] saxigp1_racount,
output wire [3:0] saxigp1_wacount,
// saxigp2
input wire saxihp0_fpd_aclk,
input wire saxihp0_fpd_rclk,
input wire saxihp0_fpd_wclk,
input wire saxigp2_aruser,
input wire saxigp2_awuser,
input wire [5:0] saxigp2_awid,
input wire [48:0] saxigp2_awaddr,
input wire [7:0] saxigp2_awlen ,
input wire [2:0] saxigp2_awsize,
input wire [1:0] saxigp2_awburst,
input wire saxigp2_awlock,
input wire [3:0] saxigp2_awcache,
input wire [2:0] saxigp2_awprot,
input wire saxigp2_awvalid,
output wire saxigp2_awready,
input wire [C_SAXIGP2_DATA_WIDTH-1:0] saxigp2_wdata,
input wire [(C_SAXIGP2_DATA_WIDTH/8) -1 :0] saxigp2_wstrb,
input wire saxigp2_wlast,
input wire saxigp2_wvalid,
output wire saxigp2_wready,
output wire [5:0] saxigp2_bid,
output wire [1:0] saxigp2_bresp,
output wire saxigp2_bvalid,
input wire saxigp2_bready,
input wire [5:0] saxigp2_arid,
input wire [48:0] saxigp2_araddr,
input wire [7:0] saxigp2_arlen,
input wire [2:0] saxigp2_arsize,
input wire [1:0] saxigp2_arburst,
input wire saxigp2_arlock,
input wire [3:0] saxigp2_arcache,
input wire [2:0] saxigp2_arprot,
input wire saxigp2_arvalid,
output wire saxigp2_arready,
output wire [5:0] saxigp2_rid,
output wire [C_SAXIGP2_DATA_WIDTH-1:0] saxigp2_rdata,
output wire [1:0] saxigp2_rresp,
output wire saxigp2_rlast,
output wire saxigp2_rvalid,
input wire saxigp2_rready,
input wire [3:0] saxigp2_awqos,
input wire [3:0] saxigp2_arqos,
output wire [7:0] saxigp2_rcount,
output wire [7:0] saxigp2_wcount,
output wire [3:0] saxigp2_racount,
output wire [3:0] saxigp2_wacount,
// saxigp3
input wire saxihp1_fpd_aclk,
input wire saxihp1_fpd_rclk,
input wire saxihp1_fpd_wclk,
input wire saxigp3_aruser,
input wire saxigp3_awuser,
input wire [5:0] saxigp3_awid,
input wire [48:0] saxigp3_awaddr,
input wire [7:0] saxigp3_awlen ,
input wire [2:0] saxigp3_awsize,
input wire [1:0] saxigp3_awburst,
input wire saxigp3_awlock,
input wire [3:0] saxigp3_awcache,
input wire [2:0] saxigp3_awprot,
input wire saxigp3_awvalid,
output wire saxigp3_awready,
input wire [C_SAXIGP3_DATA_WIDTH-1:0] saxigp3_wdata,
input wire [(C_SAXIGP3_DATA_WIDTH/8) -1 :0] saxigp3_wstrb,
input wire saxigp3_wlast,
input wire saxigp3_wvalid,
output wire saxigp3_wready,
output wire [5:0] saxigp3_bid,
output wire [1:0] saxigp3_bresp,
output wire saxigp3_bvalid,
input wire saxigp3_bready,
input wire [5:0] saxigp3_arid,
input wire [48:0] saxigp3_araddr,
input wire [7:0] saxigp3_arlen,
input wire [2:0] saxigp3_arsize,
input wire [1:0] saxigp3_arburst,
input wire saxigp3_arlock,
input wire [3:0] saxigp3_arcache,
input wire [2:0] saxigp3_arprot,
input wire saxigp3_arvalid,
output wire saxigp3_arready,
output wire [5:0] saxigp3_rid,
output wire [C_SAXIGP3_DATA_WIDTH-1:0] saxigp3_rdata,
output wire [1:0] saxigp3_rresp,
output wire saxigp3_rlast,
output wire saxigp3_rvalid,
input wire saxigp3_rready,
input wire [3:0] saxigp3_awqos,
input wire [3:0] saxigp3_arqos,
output wire [7:0] saxigp3_rcount,
output wire [7:0] saxigp3_wcount,
output wire [3:0] saxigp3_racount,
output wire [3:0] saxigp3_wacount,
// saxigp4
input wire saxihp2_fpd_aclk,
input wire saxihp2_fpd_rclk,
input wire saxihp2_fpd_wclk,
input wire saxigp4_aruser,
input wire saxigp4_awuser,
input wire [5:0] saxigp4_awid,
input wire [48:0] saxigp4_awaddr,
input wire [7:0] saxigp4_awlen ,
input wire [2:0] saxigp4_awsize,
input wire [1:0] saxigp4_awburst,
input wire saxigp4_awlock,
input wire [3:0] saxigp4_awcache,
input wire [2:0] saxigp4_awprot,
input wire saxigp4_awvalid,
output wire saxigp4_awready,
input wire [C_SAXIGP4_DATA_WIDTH-1:0] saxigp4_wdata,
input wire [(C_SAXIGP4_DATA_WIDTH/8) -1 :0] saxigp4_wstrb,
input wire saxigp4_wlast,
input wire saxigp4_wvalid,
output wire saxigp4_wready,
output wire [5:0] saxigp4_bid,
output wire [1:0] saxigp4_bresp,
output wire saxigp4_bvalid,
input wire saxigp4_bready,
input wire [5:0] saxigp4_arid,
input wire [48:0] saxigp4_araddr,
input wire [7:0] saxigp4_arlen,
input wire [2:0] saxigp4_arsize,
input wire [1:0] saxigp4_arburst,
input wire saxigp4_arlock,
input wire [3:0] saxigp4_arcache,
input wire [2:0] saxigp4_arprot,
input wire saxigp4_arvalid,
output wire saxigp4_arready,
output wire [5:0] saxigp4_rid,
output wire [C_SAXIGP4_DATA_WIDTH-1:0] saxigp4_rdata,
output wire [1:0] saxigp4_rresp,
output wire saxigp4_rlast,
output wire saxigp4_rvalid,
input wire saxigp4_rready,
input wire [3:0] saxigp4_awqos,
input wire [3:0] saxigp4_arqos,
output wire [7:0] saxigp4_rcount,
output wire [7:0] saxigp4_wcount,
output wire [3:0] saxigp4_racount,
output wire [3:0] saxigp4_wacount,
// saxigp5
input wire saxihp3_fpd_aclk,
input wire saxihp3_fpd_rclk,
input wire saxihp3_fpd_wclk,
input wire saxigp5_aruser,
input wire saxigp5_awuser,
input wire [5:0] saxigp5_awid,
input wire [48:0] saxigp5_awaddr,
input wire [7:0] saxigp5_awlen ,
input wire [2:0] saxigp5_awsize,
input wire [1:0] saxigp5_awburst,
input wire saxigp5_awlock,
input wire [3:0] saxigp5_awcache,
input wire [2:0] saxigp5_awprot,
input wire saxigp5_awvalid,
output wire saxigp5_awready,
input wire [C_SAXIGP5_DATA_WIDTH-1:0] saxigp5_wdata,
input wire [(C_SAXIGP5_DATA_WIDTH/8) -1 :0] saxigp5_wstrb,
input wire saxigp5_wlast,
input wire saxigp5_wvalid,
output wire saxigp5_wready,
output wire [5:0] saxigp5_bid,
output wire [1:0] saxigp5_bresp,
output wire saxigp5_bvalid,
input wire saxigp5_bready,
input wire [5:0] saxigp5_arid,
input wire [48:0] saxigp5_araddr,
input wire [7:0] saxigp5_arlen,
input wire [2:0] saxigp5_arsize,
input wire [1:0] saxigp5_arburst,
input wire saxigp5_arlock,
input wire [3:0] saxigp5_arcache,
input wire [2:0] saxigp5_arprot,
input wire saxigp5_arvalid,
output wire saxigp5_arready,
output wire [5:0] saxigp5_rid,
output wire [C_SAXIGP5_DATA_WIDTH-1:0] saxigp5_rdata,
output wire [1:0] saxigp5_rresp,
output wire saxigp5_rlast,
output wire saxigp5_rvalid,
input wire saxigp5_rready,
input wire [3:0] saxigp5_awqos,
input wire [3:0] saxigp5_arqos,
output wire [7:0] saxigp5_rcount,
output wire [7:0] saxigp5_wcount,
output wire [3:0] saxigp5_racount,
output wire [3:0] saxigp5_wacount,
// saxigp6
input wire saxi_lpd_aclk,
input wire saxi_lpd_rclk,
input wire saxi_lpd_wclk,
input wire saxigp6_aruser,
input wire saxigp6_awuser,
input wire [5:0] saxigp6_awid,
input wire [48:0] saxigp6_awaddr,
input wire [7:0] saxigp6_awlen ,
input wire [2:0] saxigp6_awsize,
input wire [1:0] saxigp6_awburst,
input wire saxigp6_awlock,
input wire [3:0] saxigp6_awcache,
input wire [2:0] saxigp6_awprot,
input wire saxigp6_awvalid,
output wire saxigp6_awready,
input wire [C_SAXIGP6_DATA_WIDTH-1:0] saxigp6_wdata,
input wire [(C_SAXIGP6_DATA_WIDTH/8) -1 :0] saxigp6_wstrb,
input wire saxigp6_wlast,
input wire saxigp6_wvalid,
output wire saxigp6_wready,
output wire [5:0] saxigp6_bid,
output wire [1:0] saxigp6_bresp,
output wire saxigp6_bvalid,
input wire saxigp6_bready,
input wire [5:0] saxigp6_arid,
input wire [48:0] saxigp6_araddr,
input wire [7:0] saxigp6_arlen,
input wire [2:0] saxigp6_arsize,
input wire [1:0] saxigp6_arburst,
input wire saxigp6_arlock,
input wire [3:0] saxigp6_arcache,
input wire [2:0] saxigp6_arprot,
input wire saxigp6_arvalid,
output wire saxigp6_arready,
output wire [5:0] saxigp6_rid,
output wire [C_SAXIGP6_DATA_WIDTH-1:0] saxigp6_rdata,
output wire [1:0] saxigp6_rresp,
output wire saxigp6_rlast,
output wire saxigp6_rvalid,
input wire saxigp6_rready,
input wire [3:0] saxigp6_awqos,
input wire [3:0] saxigp6_arqos,
output wire [7:0] saxigp6_rcount,
output wire [7:0] saxigp6_wcount,
output wire [3:0] saxigp6_racount,
output wire [3:0] saxigp6_wacount,
// saxiacp
input wire saxiacp_fpd_aclk,
input wire [39:0] saxiacp_awaddr,
input wire [4:0] saxiacp_awid,
input wire [7:0] saxiacp_awlen,
input wire [2:0] saxiacp_awsize,
input wire [1:0] saxiacp_awburst,
input wire saxiacp_awlock,
input wire [3:0] saxiacp_awcache,
input wire [2:0] saxiacp_awprot,
input wire saxiacp_awvalid,
output wire saxiacp_awready,
input wire [1:0] saxiacp_awuser,
input wire [3:0] saxiacp_awqos,
input wire saxiacp_wlast,
input wire [127:0] saxiacp_wdata,
input wire [15:0] saxiacp_wstrb,
input wire saxiacp_wvalid,
output wire saxiacp_wready,
output wire [1:0] saxiacp_bresp,
output wire [4:0] saxiacp_bid,
output wire saxiacp_bvalid,
input wire saxiacp_bready,
input wire [39:0] saxiacp_araddr,
input wire [4:0] saxiacp_arid,
input wire [7:0] saxiacp_arlen,
input wire [2:0] saxiacp_arsize,
input wire [1:0] saxiacp_arburst,
input wire saxiacp_arlock,
input wire [3:0] saxiacp_arcache,
input wire [2:0] saxiacp_arprot,
input wire saxiacp_arvalid,
output wire saxiacp_arready,
input wire [1:0] saxiacp_aruser,
input wire [3:0] saxiacp_arqos,
output wire [4:0] saxiacp_rid,
output wire saxiacp_rlast,
output wire [127:0] saxiacp_rdata,
output wire [1:0] saxiacp_rresp,
output wire saxiacp_rvalid,
input wire saxiacp_rready,
// sacefpd
input wire sacefpd_aclk,
input wire sacefpd_awvalid,
output wire sacefpd_awready,
input wire [5:0] sacefpd_awid,
input wire [43:0] sacefpd_awaddr,
input wire [3:0] sacefpd_awregion,
input wire [7:0] sacefpd_awlen,
input wire [2:0] sacefpd_awsize,
input wire [1:0] sacefpd_awburst,
input wire sacefpd_awlock,
input wire [3:0] sacefpd_awcache,
input wire [2:0] sacefpd_awprot,
input wire [1:0] sacefpd_awdomain,
input wire [2:0] sacefpd_awsnoop,
input wire [1:0] sacefpd_awbar,
input wire [3:0] sacefpd_awqos,
input wire sacefpd_wvalid,
output wire sacefpd_wready,
input wire [127:0] sacefpd_wdata,
input wire [15:0] sacefpd_wstrb,
input wire sacefpd_wlast,
input wire sacefpd_wuser,
output wire sacefpd_bvalid,
input wire sacefpd_bready,
output wire [5:0] sacefpd_bid,
output wire [1:0] sacefpd_bresp,
output wire sacefpd_buser,
input wire sacefpd_arvalid,
output wire sacefpd_arready,
input wire [5:0] sacefpd_arid,
input wire [43:0] sacefpd_araddr,
input wire [3:0] sacefpd_arregion,
input wire [7:0] sacefpd_arlen,
input wire [2:0] sacefpd_arsize,
input wire [1:0] sacefpd_arburst,
input wire sacefpd_arlock,
input wire [3:0] sacefpd_arcache,
input wire [2:0] sacefpd_arprot,
input wire [1:0] sacefpd_ardomain,
input wire [3:0] sacefpd_arsnoop,
input wire [1:0] sacefpd_arbar,
input wire [3:0] sacefpd_arqos,
output wire sacefpd_rvalid,
input wire sacefpd_rready,
output wire [5:0] sacefpd_rid,
output wire [127:0] sacefpd_rdata,
output wire [3:0] sacefpd_rresp,
output wire sacefpd_rlast,
output wire sacefpd_ruser,
output wire sacefpd_acvalid,
input wire sacefpd_acready,
output wire [43:0] sacefpd_acaddr,
output wire [3:0] sacefpd_acsnoop,
output wire [2:0] sacefpd_acprot,
input wire sacefpd_crvalid,
output wire sacefpd_crready,
input wire [4:0] sacefpd_crresp,
input wire sacefpd_cdvalid,
output wire sacefpd_cdready,
input wire [127:0] sacefpd_cddata,
input wire sacefpd_cdlast,
input wire sacefpd_wack,
input wire sacefpd_rack,
///////////////////////////////////////////////
// not using anything below this line yet... //
///////////////////////////////////////////////
// can0
output wire emio_can0_phy_tx,
input wire emio_can0_phy_rx,
// can1
output wire emio_can1_phy_tx,
input wire emio_can1_phy_rx,
// enet0
input wire emio_enet0_gmii_rx_clk,
output wire [2:0] emio_enet0_speed_mode,
input wire emio_enet0_gmii_crs,
input wire emio_enet0_gmii_col,
input wire [7:0] emio_enet0_gmii_rxd,
input wire emio_enet0_gmii_rx_er,
input wire emio_enet0_gmii_rx_dv,
input wire emio_enet0_gmii_tx_clk,
output wire [7:0] emio_enet0_gmii_txd,
output wire emio_enet0_gmii_tx_en,
output wire emio_enet0_gmii_tx_er,
output wire emio_enet0_mdio_mdc,
input wire emio_enet0_mdio_i,
output wire emio_enet0_mdio_o,
output wire emio_enet0_mdio_t,
output wire emio_enet0_mdio_t_n,
// enet1
input wire emio_enet1_gmii_rx_clk,
output wire [2:0] emio_enet1_speed_mode,
input wire emio_enet1_gmii_crs,
input wire emio_enet1_gmii_col,
input wire [7:0] emio_enet1_gmii_rxd,
input wire emio_enet1_gmii_rx_er,
input wire emio_enet1_gmii_rx_dv,
input wire emio_enet1_gmii_tx_clk,
output wire [7:0] emio_enet1_gmii_txd,
output wire emio_enet1_gmii_tx_en,
output wire emio_enet1_gmii_tx_er,
output wire emio_enet1_mdio_mdc,
input wire emio_enet1_mdio_i,
output wire emio_enet1_mdio_o,
output wire emio_enet1_mdio_t,
output wire emio_enet1_mdio_t_n,
// enet2
input wire emio_enet2_gmii_rx_clk,
output wire [2:0] emio_enet2_speed_mode,
input wire emio_enet2_gmii_crs,
input wire emio_enet2_gmii_col,
input wire [7:0] emio_enet2_gmii_rxd,
input wire emio_enet2_gmii_rx_er,
input wire emio_enet2_gmii_rx_dv,
input wire emio_enet2_gmii_tx_clk,
output wire [7:0] emio_enet2_gmii_txd,
output wire emio_enet2_gmii_tx_en,
output wire emio_enet2_gmii_tx_er,
output wire emio_enet2_mdio_mdc,
input wire emio_enet2_mdio_i,
output wire emio_enet2_mdio_o,
output wire emio_enet2_mdio_t,
output wire emio_enet2_mdio_t_n,
// enet3
input wire emio_enet3_gmii_rx_clk,
output wire [2:0] emio_enet3_speed_mode,
input wire emio_enet3_gmii_crs,
input wire emio_enet3_gmii_col,
input wire [7:0] emio_enet3_gmii_rxd,
input wire emio_enet3_gmii_rx_er,
input wire emio_enet3_gmii_rx_dv,
input wire emio_enet3_gmii_tx_clk,
output wire [7:0] emio_enet3_gmii_txd,
output wire emio_enet3_gmii_tx_en,
output wire emio_enet3_gmii_tx_er,
output wire emio_enet3_mdio_mdc,
input wire emio_enet3_mdio_i,
output wire emio_enet3_mdio_o,
output wire emio_enet3_mdio_t,
output wire emio_enet3_mdio_t_n,
// fifoif0
input wire emio_enet0_tx_r_data_rdy,
output wire emio_enet0_tx_r_rd,
input wire emio_enet0_tx_r_valid,
input wire [7:0] emio_enet0_tx_r_data,
input wire emio_enet0_tx_r_sop,
input wire emio_enet0_tx_r_eop,
input wire emio_enet0_tx_r_err,
input wire emio_enet0_tx_r_underflow,
input wire emio_enet0_tx_r_flushed,
input wire emio_enet0_tx_r_control,
output wire emio_enet0_dma_tx_end_tog,
input wire emio_enet0_dma_tx_status_tog,
output wire [3:0] emio_enet0_tx_r_status,
output wire emio_enet0_rx_w_wr,
output wire [7:0] emio_enet0_rx_w_data,
output wire emio_enet0_rx_w_sop,
output wire emio_enet0_rx_w_eop,
output wire [44:0] emio_enet0_rx_w_status,
output wire emio_enet0_rx_w_err,
input wire emio_enet0_rx_w_overflow,
input wire emio_enet0_signal_detect,
output wire emio_enet0_rx_w_flush,
output wire emio_enet0_tx_r_fixed_lat,
// fifoif1
input wire emio_enet1_tx_r_data_rdy,
output wire emio_enet1_tx_r_rd,
input wire emio_enet1_tx_r_valid,
input wire [7:0] emio_enet1_tx_r_data,
input wire emio_enet1_tx_r_sop,
input wire emio_enet1_tx_r_eop,
input wire emio_enet1_tx_r_err,
input wire emio_enet1_tx_r_underflow,
input wire emio_enet1_tx_r_flushed,
input wire emio_enet1_tx_r_control,
output wire emio_enet1_dma_tx_end_tog,
input wire emio_enet1_dma_tx_status_tog,
output wire [3:0] emio_enet1_tx_r_status,
output wire emio_enet1_rx_w_wr,
output wire [7:0] emio_enet1_rx_w_data,
output wire emio_enet1_rx_w_sop,
output wire emio_enet1_rx_w_eop,
output wire [44:0] emio_enet1_rx_w_status,
output wire emio_enet1_rx_w_err,
input wire emio_enet1_rx_w_overflow,
input wire emio_enet1_signal_detect,
output wire emio_enet1_rx_w_flush,
output wire emio_enet1_tx_r_fixed_lat,
// fifoif2
input wire emio_enet2_tx_r_data_rdy,
output wire emio_enet2_tx_r_rd,
input wire emio_enet2_tx_r_valid,
input wire [7:0] emio_enet2_tx_r_data,
input wire emio_enet2_tx_r_sop,
input wire emio_enet2_tx_r_eop,
input wire emio_enet2_tx_r_err,
input wire emio_enet2_tx_r_underflow,
input wire emio_enet2_tx_r_flushed,
input wire emio_enet2_tx_r_control,
output wire emio_enet2_dma_tx_end_tog,
input wire emio_enet2_dma_tx_status_tog,
output wire [3:0] emio_enet2_tx_r_status,
output wire emio_enet2_rx_w_wr,
output wire [7:0] emio_enet2_rx_w_data,
output wire emio_enet2_rx_w_sop,
output wire emio_enet2_rx_w_eop,
output wire [44:0] emio_enet2_rx_w_status,
output wire emio_enet2_rx_w_err,
input wire emio_enet2_rx_w_overflow,
input wire emio_enet2_signal_detect,
output wire emio_enet2_rx_w_flush,
output wire emio_enet2_tx_r_fixed_lat,
// fifoif3
input wire emio_enet3_tx_r_data_rdy,
output wire emio_enet3_tx_r_rd,
input wire emio_enet3_tx_r_valid,
input wire [7:0] emio_enet3_tx_r_data,
input wire emio_enet3_tx_r_sop,
input wire emio_enet3_tx_r_eop,
input wire emio_enet3_tx_r_err,
input wire emio_enet3_tx_r_underflow,
input wire emio_enet3_tx_r_flushed,
input wire emio_enet3_tx_r_control,
output wire emio_enet3_dma_tx_end_tog,
input wire emio_enet3_dma_tx_status_tog,
output wire [3:0] emio_enet3_tx_r_status,
output wire emio_enet3_rx_w_wr,
output wire [7:0] emio_enet3_rx_w_data,
output wire emio_enet3_rx_w_sop,
output wire emio_enet3_rx_w_eop,
output wire [44:0] emio_enet3_rx_w_status,
output wire emio_enet3_rx_w_err,
input wire emio_enet3_rx_w_overflow,
input wire emio_enet3_signal_detect,
output wire emio_enet3_rx_w_flush,
output wire emio_enet3_tx_r_fixed_lat,
// gem0_fmio
//input wire fmio_gem0_fifo_tx_clk_from_pl,
//input wire fmio_gem0_fifo_rx_clk_from_pl,
output wire fmio_gem0_fifo_tx_clk_to_pl_bufg,
output wire fmio_gem0_fifo_rx_clk_to_pl_bufg,
// gem1_fmio
//input wire fmio_gem1_fifo_tx_clk_from_pl,
//input wire fmio_gem1_fifo_rx_clk_from_pl,
output wire fmio_gem1_fifo_tx_clk_to_pl_bufg,
output wire fmio_gem1_fifo_rx_clk_to_pl_bufg,
// gem2_fmio
//input wire fmio_gem2_fifo_tx_clk_from_pl,
//input wire fmio_gem2_fifo_rx_clk_from_pl,
output wire fmio_gem2_fifo_tx_clk_to_pl_bufg,
output wire fmio_gem2_fifo_rx_clk_to_pl_bufg,
// gem3_fmio
//input wire fmio_gem3_fifo_tx_clk_from_pl,
//input wire fmio_gem3_fifo_rx_clk_from_pl,
output wire fmio_gem3_fifo_tx_clk_to_pl_bufg,
output wire fmio_gem3_fifo_rx_clk_to_pl_bufg,
// gem0_1588
output wire emio_enet0_tx_sof,
output wire emio_enet0_sync_frame_tx,
output wire emio_enet0_delay_req_tx,
output wire emio_enet0_pdelay_req_tx,
output wire emio_enet0_pdelay_resp_tx,
output wire emio_enet0_rx_sof,
output wire emio_enet0_sync_frame_rx,
output wire emio_enet0_delay_req_rx,
output wire emio_enet0_pdelay_req_rx,
output wire emio_enet0_pdelay_resp_rx,
input wire [1:0] emio_enet0_tsu_inc_ctrl,
output wire emio_enet0_tsu_timer_cmp_val,
//gem1_1588
output wire emio_enet1_tx_sof,
output wire emio_enet1_sync_frame_tx,
output wire emio_enet1_delay_req_tx,
output wire emio_enet1_pdelay_req_tx,
output wire emio_enet1_pdelay_resp_tx,
output wire emio_enet1_rx_sof,
output wire emio_enet1_sync_frame_rx,
output wire emio_enet1_delay_req_rx,
output wire emio_enet1_pdelay_req_rx,
output wire emio_enet1_pdelay_resp_rx,
input wire [1:0] emio_enet1_tsu_inc_ctrl,
output wire emio_enet1_tsu_timer_cmp_val,
//gem2_1588
output wire emio_enet2_tx_sof,
output wire emio_enet2_sync_frame_tx,
output wire emio_enet2_delay_req_tx,
output wire emio_enet2_pdelay_req_tx,
output wire emio_enet2_pdelay_resp_tx,
output wire emio_enet2_rx_sof,
output wire emio_enet2_sync_frame_rx,
output wire emio_enet2_delay_req_rx,
output wire emio_enet2_pdelay_req_rx,
output wire emio_enet2_pdelay_resp_rx,
input wire [1:0] emio_enet2_tsu_inc_ctrl,
output wire emio_enet2_tsu_timer_cmp_val,
//gem3_1588
output wire emio_enet3_tx_sof,
output wire emio_enet3_sync_frame_tx,
output wire emio_enet3_delay_req_tx,
output wire emio_enet3_pdelay_req_tx,
output wire emio_enet3_pdelay_resp_tx,
output wire emio_enet3_rx_sof,
output wire emio_enet3_sync_frame_rx,
output wire emio_enet3_delay_req_rx,
output wire emio_enet3_pdelay_req_rx,
output wire emio_enet3_pdelay_resp_rx,
input wire [1:0] emio_enet3_tsu_inc_ctrl,
output wire emio_enet3_tsu_timer_cmp_val,
// gem_tsu
input wire fmio_gem_tsu_clk_from_pl,
output wire fmio_gem_tsu_clk_to_pl_bufg,
input wire emio_enet_tsu_clk,
output wire [93:0] emio_enet0_enet_tsu_timer_cnt,
// gem_misc
input wire emio_enet0_ext_int_in,
input wire emio_enet1_ext_int_in,
input wire emio_enet2_ext_int_in,
input wire emio_enet3_ext_int_in,
output wire [1:0] emio_enet0_dma_bus_width,
output wire [1:0] emio_enet1_dma_bus_width,
output wire [1:0] emio_enet2_dma_bus_width,
output wire [1:0] emio_enet3_dma_bus_width,
// gpio
input wire [(C_EMIO_GPIO_WIDTH -1):0] emio_gpio_i,
output wire [(C_EMIO_GPIO_WIDTH -1):0] emio_gpio_o,
output wire [(C_EMIO_GPIO_WIDTH -1):0] emio_gpio_t,
output wire [(C_EMIO_GPIO_WIDTH -1):0] emio_gpio_t_n,
// i2c0
input wire emio_i2c0_scl_i,
output wire emio_i2c0_scl_o,
output wire emio_i2c0_scl_t_n,
output wire emio_i2c0_scl_t,
input wire emio_i2c0_sda_i,
output wire emio_i2c0_sda_o,
output wire emio_i2c0_sda_t_n,
output wire emio_i2c0_sda_t,
// i2c1
input wire emio_i2c1_scl_i,
output wire emio_i2c1_scl_o,
output wire emio_i2c1_scl_t,
output wire emio_i2c1_scl_t_n,
input wire emio_i2c1_sda_i,
output wire emio_i2c1_sda_o,
output wire emio_i2c1_sda_t,
output wire emio_i2c1_sda_t_n,
// uart0
output wire emio_uart0_txd,
input wire emio_uart0_rxd,
input wire emio_uart0_ctsn,
output wire emio_uart0_rtsn,
input wire emio_uart0_dsrn,
input wire emio_uart0_dcdn,
input wire emio_uart0_rin,
output wire emio_uart0_dtrn,
// uart1
output wire emio_uart1_txd,
input wire emio_uart1_rxd,
input wire emio_uart1_ctsn,
output wire emio_uart1_rtsn,
input wire emio_uart1_dsrn,
input wire emio_uart1_dcdn,
input wire emio_uart1_rin,
output wire emio_uart1_dtrn,
// sdio0
output wire emio_sdio0_clkout,
input wire emio_sdio0_fb_clk_in,
output wire emio_sdio0_cmdout,
input wire emio_sdio0_cmdin,
output wire emio_sdio0_cmdena,
input wire [C_SD0_INTERNAL_BUS_WIDTH-1:0] emio_sdio0_datain,
output wire [C_SD0_INTERNAL_BUS_WIDTH-1:0] emio_sdio0_dataout,
output wire [C_SD0_INTERNAL_BUS_WIDTH-1:0] emio_sdio0_dataena,
input wire emio_sdio0_cd_n,
input wire emio_sdio0_wp,
output wire emio_sdio0_ledcontrol,
output wire emio_sdio0_buspower,
output wire [2:0] emio_sdio0_bus_volt,
// sdio1
output wire emio_sdio1_clkout,
input wire emio_sdio1_fb_clk_in,
output wire emio_sdio1_cmdout,
input wire emio_sdio1_cmdin,
output wire emio_sdio1_cmdena,
input wire [C_SD1_INTERNAL_BUS_WIDTH-1:0] emio_sdio1_datain,
output wire [C_SD1_INTERNAL_BUS_WIDTH-1:0] emio_sdio1_dataout,
output wire [C_SD1_INTERNAL_BUS_WIDTH-1:0] emio_sdio1_dataena,
input wire emio_sdio1_cd_n,
input wire emio_sdio1_wp,
output wire emio_sdio1_ledcontrol,
output wire emio_sdio1_buspower,
output wire [2:0] emio_sdio1_bus_volt,
// spi0
input wire emio_spi0_sclk_i,
output wire emio_spi0_sclk_o,
output wire emio_spi0_sclk_t,
output wire emio_spi0_sclk_t_n,
input wire emio_spi0_m_i,
output wire emio_spi0_m_o,
output wire emio_spi0_mo_t,
output wire emio_spi0_mo_t_n,
input wire emio_spi0_s_i,
output wire emio_spi0_s_o,
output wire emio_spi0_so_t,
output wire emio_spi0_so_t_n,
input wire emio_spi0_ss_i_n,
output wire emio_spi0_ss_o_n,
output wire emio_spi0_ss1_o_n,
output wire emio_spi0_ss2_o_n,
output wire emio_spi0_ss_n_t,
output wire emio_spi0_ss_n_t_n,
// spi1
input wire emio_spi1_sclk_i,
output wire emio_spi1_sclk_o,
output wire emio_spi1_sclk_t,
output wire emio_spi1_sclk_t_n,
input wire emio_spi1_m_i,
output wire emio_spi1_m_o,
output wire emio_spi1_mo_t,
output wire emio_spi1_mo_t_n,
input wire emio_spi1_s_i,
output wire emio_spi1_s_o,
output wire emio_spi1_so_t,
output wire emio_spi1_so_t_n,
input wire emio_spi1_ss_i_n,
output wire emio_spi1_ss_o_n,
output wire emio_spi1_ss1_o_n,
output wire emio_spi1_ss2_o_n,
output wire emio_spi1_ss_n_t,
output wire emio_spi1_ss_n_t_n,
// trace
input wire pl_ps_trace_clk,
output wire ps_pl_tracectl,
output wire [C_TRACE_DATA_WIDTH-1:0] ps_pl_tracedata,
output reg trace_clk_out,
// ttc0
output wire [2:0] emio_ttc0_wave_o,
input wire [2:0] emio_ttc0_clk_i,
// ttc1
output wire [2:0] emio_ttc1_wave_o,
input wire [2:0] emio_ttc1_clk_i,
// ttc2
output wire [2:0] emio_ttc2_wave_o,
input wire [2:0] emio_ttc2_clk_i,
// ttc3
output wire [2:0] emio_ttc3_wave_o,
input wire [2:0] emio_ttc3_clk_i,
// wdt0
input wire emio_wdt0_clk_i,
output wire emio_wdt0_rst_o,
// wdt1
input wire emio_wdt1_clk_i,
output wire emio_wdt1_rst_o,
// usb3
input wire emio_hub_port_overcrnt_usb3_0,
input wire emio_hub_port_overcrnt_usb3_1,
input wire emio_hub_port_overcrnt_usb2_0,
input wire emio_hub_port_overcrnt_usb2_1,
output wire emio_u2dsport_vbus_ctrl_usb3_0,
output wire emio_u2dsport_vbus_ctrl_usb3_1,
output wire emio_u3dsport_vbus_ctrl_usb3_0,
output wire emio_u3dsport_vbus_ctrl_usb3_1,
//adma
input wire [7:0] adma_fci_clk,
input wire [7:0] pl2adma_cvld,
input wire [7:0] pl2adma_tack,
output wire [7:0] adma2pl_cack,
output wire [7:0] adma2pl_tvld,
//gdma
input wire [7:0] perif_gdma_clk,
input wire [7:0] perif_gdma_cvld,
input wire [7:0] perif_gdma_tack,
output wire [7:0] gdma_perif_cack,
output wire [7:0] gdma_perif_tvld,
// clk
input wire [3:0] pl_clock_stop,
input wire [1:0] pll_aux_refclk_lpd,
input wire [2:0] pll_aux_refclk_fpd,
// audio
input wire [31:0] dp_s_axis_audio_tdata,
input wire dp_s_axis_audio_tid,
input wire dp_s_axis_audio_tvalid,
output wire dp_s_axis_audio_tready,
output wire [31:0] dp_m_axis_mixed_audio_tdata,
output wire dp_m_axis_mixed_audio_tid,
output wire dp_m_axis_mixed_audio_tvalid,
input wire dp_m_axis_mixed_audio_tready,
input wire dp_s_axis_audio_clk,
// video
input wire dp_live_video_in_vsync,
input wire dp_live_video_in_hsync,
input wire dp_live_video_in_de,
input wire [35:0] dp_live_video_in_pixel1,
input wire dp_video_in_clk,
output wire dp_video_out_hsync,
output wire dp_video_out_vsync,
output wire [35:0] dp_video_out_pixel1,
input wire dp_aux_data_in,
output wire dp_aux_data_out,
output wire dp_aux_data_oe_n,
input wire [7:0] dp_live_gfx_alpha_in,
input wire [35:0] dp_live_gfx_pixel1_in,
input wire dp_hot_plug_detect,
input wire dp_external_custom_event1,
input wire dp_external_custom_event2,
input wire dp_external_vsync_event,
output wire dp_live_video_de_out,
// event_apu
input wire pl_ps_eventi,
output wire ps_pl_evento,
output wire [3:0] ps_pl_standbywfe,
output wire [3:0] ps_pl_standbywfi,
input wire [3:0] pl_ps_apugic_irq,
input wire [3:0] pl_ps_apugic_fiq,
// event_rpu
input wire rpu_eventi0,
input wire rpu_eventi1,
output wire rpu_evento0,
output wire rpu_evento1,
input wire nfiq0_lpd_rpu,
input wire nfiq1_lpd_rpu,
input wire nirq0_lpd_rpu,
input wire nirq1_lpd_rpu,
// ipi
output wire irq_ipi_pl_0,
output wire irq_ipi_pl_1,
output wire irq_ipi_pl_2,
output wire irq_ipi_pl_3,
// stm
input wire [59:0] stm_event,
// ftm
input wire pl_ps_trigack_0,
input wire pl_ps_trigack_1,
input wire pl_ps_trigack_2,
input wire pl_ps_trigack_3,
input wire pl_ps_trigger_0,
input wire pl_ps_trigger_1,
input wire pl_ps_trigger_2,
input wire pl_ps_trigger_3,
output wire ps_pl_trigack_0,
output wire ps_pl_trigack_1,
output wire ps_pl_trigack_2,
output wire ps_pl_trigack_3,
output wire ps_pl_trigger_0,
output wire ps_pl_trigger_1,
output wire ps_pl_trigger_2,
output wire ps_pl_trigger_3,
output wire [31:0] ftm_gpo,
input wire [31:0] ftm_gpi,
// irq
input wire [(C_NUM_F2P_0_INTR_INPUTS-1):0] pl_ps_irq0,
input wire [(C_NUM_F2P_1_INTR_INPUTS-1):0] pl_ps_irq1,
//output wire [99:0] ps_pl_irq_lpd,
//output wire [63:0] ps_pl_irq_fpd,
//resets using gpio
output wire pl_resetn0,
output wire pl_resetn1,
output wire pl_resetn2,
output wire pl_resetn3,
output wire ps_pl_irq_can0,
output wire ps_pl_irq_can1,
output wire ps_pl_irq_enet0,
output wire ps_pl_irq_enet1,
output wire ps_pl_irq_enet2,
output wire ps_pl_irq_enet3,
output wire ps_pl_irq_enet0_wake,
output wire ps_pl_irq_enet1_wake,
output wire ps_pl_irq_enet2_wake,
output wire ps_pl_irq_enet3_wake,
output wire ps_pl_irq_gpio,
output wire ps_pl_irq_i2c0,
output wire ps_pl_irq_i2c1,
output wire ps_pl_irq_uart0,
output wire ps_pl_irq_uart1,
output wire ps_pl_irq_sdio0,
output wire ps_pl_irq_sdio1,
output wire ps_pl_irq_sdio0_wake,
output wire ps_pl_irq_sdio1_wake,
output wire ps_pl_irq_spi0,
output wire ps_pl_irq_spi1,
output wire ps_pl_irq_qspi,
output wire ps_pl_irq_ttc0_0,
output wire ps_pl_irq_ttc0_1,
output wire ps_pl_irq_ttc0_2,
output wire ps_pl_irq_ttc1_0,
output wire ps_pl_irq_ttc1_1,
output wire ps_pl_irq_ttc1_2,
output wire ps_pl_irq_ttc2_0,
output wire ps_pl_irq_ttc2_1,
output wire ps_pl_irq_ttc2_2,
output wire ps_pl_irq_ttc3_0,
output wire ps_pl_irq_ttc3_1,
output wire ps_pl_irq_ttc3_2,
output wire ps_pl_irq_csu_pmu_wdt,
output wire ps_pl_irq_lp_wdt,
output wire [3:0] ps_pl_irq_usb3_0_endpoint,
output wire ps_pl_irq_usb3_0_otg,
output wire [3:0] ps_pl_irq_usb3_1_endpoint,
output wire ps_pl_irq_usb3_1_otg,
output wire [7:0] ps_pl_irq_adma_chan,
output wire [1:0] ps_pl_irq_usb3_0_pmu_wakeup,
output wire [7:0] ps_pl_irq_gdma_chan,
output wire ps_pl_irq_csu,
output wire ps_pl_irq_csu_dma,
output wire ps_pl_irq_efuse,
output wire ps_pl_irq_xmpu_lpd,
output wire ps_pl_irq_ddr_ss,
output wire ps_pl_irq_nand,
output wire ps_pl_irq_fp_wdt,
output wire [1:0] ps_pl_irq_pcie_msi,
output wire ps_pl_irq_pcie_legacy,
output wire ps_pl_irq_pcie_dma,
output wire ps_pl_irq_pcie_msc,
output wire ps_pl_irq_dport,
output wire ps_pl_irq_fpd_apb_int,
output wire ps_pl_irq_fpd_atb_error,
output wire ps_pl_irq_dpdma,
output wire ps_pl_irq_apm_fpd,
output wire ps_pl_irq_gpu,
output wire ps_pl_irq_sata,
output wire ps_pl_irq_xmpu_fpd,
output wire [3:0] ps_pl_irq_apu_cpumnt,
output wire [3:0] ps_pl_irq_apu_cti,
output wire [3:0] ps_pl_irq_apu_pmu,
output wire [3:0] ps_pl_irq_apu_comm,
output wire ps_pl_irq_apu_l2err,
output wire ps_pl_irq_apu_exterr,
output wire ps_pl_irq_apu_regs,
output wire ps_pl_irq_intf_ppd_cci,
output wire ps_pl_irq_intf_fpd_smmu,
output wire ps_pl_irq_atb_err_lpd,
output wire ps_pl_irq_aib_axi,
output wire ps_pl_irq_ams,
output wire ps_pl_irq_lpd_apm,
output wire ps_pl_irq_rtc_alaram,
output wire ps_pl_irq_rtc_seconds,
output wire ps_pl_irq_clkmon,
output wire ps_pl_irq_ipi_channel0,
output wire ps_pl_irq_ipi_channel1,
output wire ps_pl_irq_ipi_channel2,
output wire ps_pl_irq_ipi_channel7,
output wire ps_pl_irq_ipi_channel8,
output wire ps_pl_irq_ipi_channel9,
output wire ps_pl_irq_ipi_channel10,
output wire [1:0] ps_pl_irq_rpu_pm,
output wire ps_pl_irq_ocm_error,
output wire ps_pl_irq_lpd_apb_intr,
output wire ps_pl_irq_r5_core0_ecc_error,
output wire ps_pl_irq_r5_core1_ecc_error,
// rtc
output wire osc_rtc_clk,
// pmu
input wire [31:0] pl_pmu_gpi,
output wire [31:0] pmu_pl_gpo,
input wire aib_pmu_afifm_fpd_ack,
input wire aib_pmu_afifm_lpd_ack,
output wire pmu_aib_afifm_fpd_req,
output wire pmu_aib_afifm_lpd_req,
output wire [46:0] pmu_error_to_pl,
input wire [3:0] pmu_error_from_pl,
// misc
input wire ddrc_ext_refresh_rank0_req,
input wire ddrc_ext_refresh_rank1_req,
input wire ddrc_refresh_pl_clk,
input wire pl_acpinact,
//For Clock buffering
//FCLK
output wire pl_clk3,
output wire pl_clk2,
output wire pl_clk1,
output wire pl_clk0,
///////////////////////////
// ACE interface allotment
//////////////////////////
input wire [15:0] sacefpd_awuser,
input wire [15:0] sacefpd_aruser,
//Debug and Test signals
input [3:0] test_adc_clk,
input [31:0] test_adc_in,
input [31:0] test_adc2_in,
output [15:0] test_db,
output [19:0] test_adc_out,
output [7:0] test_ams_osc,
output [15:0] test_mon_data,
input test_dclk,
input test_den,
input test_dwe,
input [7:0] test_daddr,
input [15:0] test_di,
output test_drdy,
output [15:0] test_do,
input test_convst,
input [3:0] pstp_pl_clk,
input [31:0] pstp_pl_in,
output [31:0] pstp_pl_out,
input [31:0] pstp_pl_ts,
input fmio_test_gem_scanmux_1,
input fmio_test_gem_scanmux_2,
input test_char_mode_fpd_n,
input test_char_mode_lpd_n,
input fmio_test_io_char_scan_clock,
input fmio_test_io_char_scanenable,
input fmio_test_io_char_scan_in,
output fmio_test_io_char_scan_out,
input fmio_test_io_char_scan_reset_n,
input fmio_char_afifslpd_test_select_n,
input fmio_char_afifslpd_test_input,
output fmio_char_afifslpd_test_output,
input fmio_char_afifsfpd_test_select_n,
input fmio_char_afifsfpd_test_input,
output fmio_char_afifsfpd_test_output,
input io_char_audio_in_test_data,
input io_char_audio_mux_sel_n,
input io_char_video_in_test_data,
input io_char_video_mux_sel_n,
output io_char_video_out_test_data,
output io_char_audio_out_test_data,
input fmio_test_qspi_scanmux_1_n,
input fmio_test_sdio_scanmux_1,
input fmio_test_sdio_scanmux_2,
input [3:0] fmio_sd0_dll_test_in_n,
output [7:0] fmio_sd0_dll_test_out,
input [3:0] fmio_sd1_dll_test_in_n,
output [7:0] fmio_sd1_dll_test_out,
input test_pl_scan_chopper_si,
output test_pl_scan_chopper_so,
input test_pl_scan_chopper_trig,
input test_pl_scan_clk0,
input test_pl_scan_clk1,
input test_pl_scan_edt_clk,
input test_pl_scan_edt_in_apu,
input test_pl_scan_edt_in_cpu,
input [3:0] test_pl_scan_edt_in_ddr,
input [9:0] test_pl_scan_edt_in_fp,
input [3:0] test_pl_scan_edt_in_gpu,
input [8:0] test_pl_scan_edt_in_lp,
input [1:0] test_pl_scan_edt_in_usb3,
output test_pl_scan_edt_out_apu,
output test_pl_scan_edt_out_cpu0,
output test_pl_scan_edt_out_cpu1,
output test_pl_scan_edt_out_cpu2,
output test_pl_scan_edt_out_cpu3,
output [3:0] test_pl_scan_edt_out_ddr,
output [9:0] test_pl_scan_edt_out_fp,
output [3:0] test_pl_scan_edt_out_gpu,
output [8:0] test_pl_scan_edt_out_lp,
output [1:0] test_pl_scan_edt_out_usb3,
input test_pl_scan_edt_update,
input test_pl_scan_reset_n,
input test_pl_scanenable,
input test_pl_scan_pll_reset,
input test_pl_scan_spare_in0,
input test_pl_scan_spare_in1,
output test_pl_scan_spare_out0,
output test_pl_scan_spare_out1,
input test_pl_scan_wrap_clk,
input test_pl_scan_wrap_ishift,
input test_pl_scan_wrap_oshift,
input test_pl_scan_slcr_config_clk,
input test_pl_scan_slcr_config_rstn,
input test_pl_scan_slcr_config_si,
input test_pl_scan_spare_in2,
input test_pl_scanenable_slcr_en,
output [4:0] test_pl_pll_lock_out,
output test_pl_scan_slcr_config_so,
input [20:0] tst_rtc_calibreg_in,
output [20:0] tst_rtc_calibreg_out,
input tst_rtc_calibreg_we,
input tst_rtc_clk,
output tst_rtc_osc_clk_out,
output [31:0] tst_rtc_sec_counter_out,
output tst_rtc_seconds_raw_int,
input tst_rtc_testclock_select_n,
output [15:0] tst_rtc_tick_counter_out,
input [31:0] tst_rtc_timesetreg_in,
output [31:0] tst_rtc_timesetreg_out,
input tst_rtc_disable_bat_op,
input [3:0] tst_rtc_osc_cntrl_in,
output [3:0] tst_rtc_osc_cntrl_out,
input tst_rtc_osc_cntrl_we,
input tst_rtc_sec_reload,
input tst_rtc_timesetreg_we,
input tst_rtc_testmode_n,
input test_usb0_funcmux_0_n,
input test_usb1_funcmux_0_n,
input test_usb0_scanmux_0_n,
input test_usb1_scanmux_0_n,
output [31:0] lpd_pll_test_out,
input [2:0] pl_lpd_pll_test_ck_sel_n,
input pl_lpd_pll_test_fract_clk_sel_n,
input pl_lpd_pll_test_fract_en_n,
input pl_lpd_pll_test_mux_sel,
input [3:0] pl_lpd_pll_test_sel,
output [31:0] fpd_pll_test_out,
input [2:0] pl_fpd_pll_test_ck_sel_n,
input pl_fpd_pll_test_fract_clk_sel_n,
input pl_fpd_pll_test_fract_en_n,
input [1:0] pl_fpd_pll_test_mux_sel,
input [3:0] pl_fpd_pll_test_sel,
input [1:0] fmio_char_gem_selection,
input fmio_char_gem_test_select_n,
input fmio_char_gem_test_input,
output fmio_char_gem_test_output,
output test_ddr2pl_dcd_skewout,
input test_pl2ddr_dcd_sample_pulse,
input test_bscan_en_n,
input test_bscan_tdi,
input test_bscan_updatedr,
input test_bscan_shiftdr,
input test_bscan_reset_tap_b,
input test_bscan_misr_jtag_load,
input test_bscan_intest,
input test_bscan_extest,
input test_bscan_clockdr,
input test_bscan_ac_mode,
input test_bscan_ac_test,
input test_bscan_init_memory,
input test_bscan_mode_c,
output test_bscan_tdo,
input i_dbg_l0_txclk,
input i_dbg_l0_rxclk,
input i_dbg_l1_txclk,
input i_dbg_l1_rxclk,
input i_dbg_l2_txclk,
input i_dbg_l2_rxclk,
input i_dbg_l3_txclk,
input i_dbg_l3_rxclk,
input i_afe_rx_symbol_clk_by_2_pl,
input pl_fpd_spare_0_in,
input pl_fpd_spare_1_in,
input pl_fpd_spare_2_in,
input pl_fpd_spare_3_in,
input pl_fpd_spare_4_in,
output fpd_pl_spare_0_out,
output fpd_pl_spare_1_out,
output fpd_pl_spare_2_out,
output fpd_pl_spare_3_out,
output fpd_pl_spare_4_out,
input pl_lpd_spare_0_in,
input pl_lpd_spare_1_in,
input pl_lpd_spare_2_in,
input pl_lpd_spare_3_in,
input pl_lpd_spare_4_in,
output lpd_pl_spare_0_out,
output lpd_pl_spare_1_out,
output lpd_pl_spare_2_out,
output lpd_pl_spare_3_out,
output lpd_pl_spare_4_out,
output o_dbg_l0_phystatus,
output [19:0] o_dbg_l0_rxdata,
output [1:0] o_dbg_l0_rxdatak,
output o_dbg_l0_rxvalid,
output [2:0] o_dbg_l0_rxstatus,
output o_dbg_l0_rxelecidle,
output o_dbg_l0_rstb,
output [19:0] o_dbg_l0_txdata,
output [1:0] o_dbg_l0_txdatak,
output [1:0] o_dbg_l0_rate,
output [1:0] o_dbg_l0_powerdown,
output o_dbg_l0_txelecidle,
output o_dbg_l0_txdetrx_lpback,
output o_dbg_l0_rxpolarity,
output o_dbg_l0_tx_sgmii_ewrap,
output o_dbg_l0_rx_sgmii_en_cdet,
output [19:0] o_dbg_l0_sata_corerxdata,
output [1:0] o_dbg_l0_sata_corerxdatavalid,
output o_dbg_l0_sata_coreready,
output o_dbg_l0_sata_coreclockready,
output o_dbg_l0_sata_corerxsignaldet,
output [19:0] o_dbg_l0_sata_phyctrltxdata,
output o_dbg_l0_sata_phyctrltxidle,
output [1:0] o_dbg_l0_sata_phyctrltxrate,
output [1:0] o_dbg_l0_sata_phyctrlrxrate,
output o_dbg_l0_sata_phyctrltxrst,
output o_dbg_l0_sata_phyctrlrxrst,
output o_dbg_l0_sata_phyctrlreset,
output o_dbg_l0_sata_phyctrlpartial,
output o_dbg_l0_sata_phyctrlslumber,
output o_dbg_l1_phystatus,
output [19:0] o_dbg_l1_rxdata,
output [1:0] o_dbg_l1_rxdatak,
output o_dbg_l1_rxvalid,
output [2:0] o_dbg_l1_rxstatus,
output o_dbg_l1_rxelecidle,
output o_dbg_l1_rstb,
output [19:0] o_dbg_l1_txdata,
output [1:0] o_dbg_l1_txdatak,
output [1:0] o_dbg_l1_rate,
output [1:0] o_dbg_l1_powerdown,
output o_dbg_l1_txelecidle,
output o_dbg_l1_txdetrx_lpback,
output o_dbg_l1_rxpolarity,
output o_dbg_l1_tx_sgmii_ewrap,
output o_dbg_l1_rx_sgmii_en_cdet,
output [19:0] o_dbg_l1_sata_corerxdata,
output [1:0] o_dbg_l1_sata_corerxdatavalid,
output o_dbg_l1_sata_coreready,
output o_dbg_l1_sata_coreclockready,
output o_dbg_l1_sata_corerxsignaldet,
output [19:0] o_dbg_l1_sata_phyctrltxdata,
output o_dbg_l1_sata_phyctrltxidle,
output [1:0] o_dbg_l1_sata_phyctrltxrate,
output [1:0] o_dbg_l1_sata_phyctrlrxrate,
output o_dbg_l1_sata_phyctrltxrst,
output o_dbg_l1_sata_phyctrlrxrst,
output o_dbg_l1_sata_phyctrlreset,
output o_dbg_l1_sata_phyctrlpartial,
output o_dbg_l1_sata_phyctrlslumber,
output o_dbg_l2_phystatus,
output [19:0] o_dbg_l2_rxdata,
output [1:0] o_dbg_l2_rxdatak,
output o_dbg_l2_rxvalid,
output [2:0] o_dbg_l2_rxstatus,
output o_dbg_l2_rxelecidle,
output o_dbg_l2_rstb,
output [19:0] o_dbg_l2_txdata,
output [1:0] o_dbg_l2_txdatak,
output [1:0] o_dbg_l2_rate,
output [1:0] o_dbg_l2_powerdown,
output o_dbg_l2_txelecidle,
output o_dbg_l2_txdetrx_lpback,
output o_dbg_l2_rxpolarity,
output o_dbg_l2_tx_sgmii_ewrap,
output o_dbg_l2_rx_sgmii_en_cdet,
output [19:0] o_dbg_l2_sata_corerxdata,
output [1:0] o_dbg_l2_sata_corerxdatavalid,
output o_dbg_l2_sata_coreready,
output o_dbg_l2_sata_coreclockready,
output o_dbg_l2_sata_corerxsignaldet,
output [19:0] o_dbg_l2_sata_phyctrltxdata,
output o_dbg_l2_sata_phyctrltxidle,
output [1:0] o_dbg_l2_sata_phyctrltxrate,
output [1:0] o_dbg_l2_sata_phyctrlrxrate,
output o_dbg_l2_sata_phyctrltxrst,
output o_dbg_l2_sata_phyctrlrxrst,
output o_dbg_l2_sata_phyctrlreset,
output o_dbg_l2_sata_phyctrlpartial,
output o_dbg_l2_sata_phyctrlslumber,
output o_dbg_l3_phystatus,
output [19:0] o_dbg_l3_rxdata,
output [1:0] o_dbg_l3_rxdatak,
output o_dbg_l3_rxvalid,
output [2:0] o_dbg_l3_rxstatus,
output o_dbg_l3_rxelecidle,
output o_dbg_l3_rstb,
output [19:0] o_dbg_l3_txdata,
output [1:0] o_dbg_l3_txdatak,
output [1:0] o_dbg_l3_rate,
output [1:0] o_dbg_l3_powerdown,
output o_dbg_l3_txelecidle,
output o_dbg_l3_txdetrx_lpback,
output o_dbg_l3_rxpolarity,
output o_dbg_l3_tx_sgmii_ewrap,
output o_dbg_l3_rx_sgmii_en_cdet,
output [19:0] o_dbg_l3_sata_corerxdata,
output [1:0] o_dbg_l3_sata_corerxdatavalid,
output o_dbg_l3_sata_coreready,
output o_dbg_l3_sata_coreclockready,
output o_dbg_l3_sata_corerxsignaldet,
output [19:0] o_dbg_l3_sata_phyctrltxdata,
output o_dbg_l3_sata_phyctrltxidle,
output [1:0] o_dbg_l3_sata_phyctrltxrate,
output [1:0] o_dbg_l3_sata_phyctrlrxrate,
output o_dbg_l3_sata_phyctrltxrst,
output o_dbg_l3_sata_phyctrlrxrst,
output o_dbg_l3_sata_phyctrlreset,
output o_dbg_l3_sata_phyctrlpartial,
output o_dbg_l3_sata_phyctrlslumber,
output dbg_path_fifo_bypass,
input i_afe_pll_pd_hs_clock_r,
input i_afe_mode,
input i_bgcal_afe_mode,
output o_afe_cmn_calib_comp_out,
input i_afe_cmn_bg_enable_low_leakage,
input i_afe_cmn_bg_iso_ctrl_bar,
input i_afe_cmn_bg_pd,
input i_afe_cmn_bg_pd_bg_ok,
input i_afe_cmn_bg_pd_ptat,
input i_afe_cmn_calib_en_iconst,
input i_afe_cmn_calib_enable_low_leakage,
input i_afe_cmn_calib_iso_ctrl_bar,
output [12:0] o_afe_pll_dco_count,
output o_afe_pll_clk_sym_hs,
output o_afe_pll_fbclk_frac,
output o_afe_rx_pipe_lfpsbcn_rxelecidle,
output o_afe_rx_pipe_sigdet,
output [19:0] o_afe_rx_symbol,
output o_afe_rx_symbol_clk_by_2,
output o_afe_rx_uphy_save_calcode,
output o_afe_rx_uphy_startloop_buf,
output o_afe_rx_uphy_rx_calib_done,
input i_afe_rx_rxpma_rstb,
input [7:0] i_afe_rx_uphy_restore_calcode_data,
input i_afe_rx_pipe_rxeqtraining,
input i_afe_rx_iso_hsrx_ctrl_bar,
input i_afe_rx_iso_lfps_ctrl_bar,
input i_afe_rx_iso_sigdet_ctrl_bar,
input i_afe_rx_hsrx_clock_stop_req,
output [7:0] o_afe_rx_uphy_save_calcode_data,
output o_afe_rx_hsrx_clock_stop_ack,
output o_afe_pg_avddcr,
output o_afe_pg_avddio,
output o_afe_pg_dvddcr,
output o_afe_pg_static_avddcr,
output o_afe_pg_static_avddio,
input i_pll_afe_mode,
input [10:0] i_afe_pll_coarse_code,
input i_afe_pll_en_clock_hs_div2,
input [15:0] i_afe_pll_fbdiv,
input i_afe_pll_load_fbdiv,
input i_afe_pll_pd,
input i_afe_pll_pd_pfd,
input i_afe_pll_rst_fdbk_div,
input i_afe_pll_startloop,
input [5:0] i_afe_pll_v2i_code,
input [4:0] i_afe_pll_v2i_prog,
input i_afe_pll_vco_cnt_window,
input i_afe_rx_mphy_gate_symbol_clk,
input i_afe_rx_mphy_mux_hsb_ls,
input i_afe_rx_pipe_rx_term_enable,
input i_afe_rx_uphy_biasgen_iconst_core_mirror_enable,
input i_afe_rx_uphy_biasgen_iconst_io_mirror_enable,
input i_afe_rx_uphy_biasgen_irconst_core_mirror_enable,
input i_afe_rx_uphy_enable_cdr,
input i_afe_rx_uphy_enable_low_leakage,
input i_afe_rx_rxpma_refclk_dig,
input i_afe_rx_uphy_hsrx_rstb,
input i_afe_rx_uphy_pdn_hs_des,
input i_afe_rx_uphy_pd_samp_c2c,
input i_afe_rx_uphy_pd_samp_c2c_eclk,
input i_afe_rx_uphy_pso_clk_lane,
input i_afe_rx_uphy_pso_eq,
input i_afe_rx_uphy_pso_hsrxdig,
input i_afe_rx_uphy_pso_iqpi,
input i_afe_rx_uphy_pso_lfpsbcn,
input i_afe_rx_uphy_pso_samp_flops,
input i_afe_rx_uphy_pso_sigdet,
input i_afe_rx_uphy_restore_calcode,
input i_afe_rx_uphy_run_calib,
input i_afe_rx_uphy_rx_lane_polarity_swap,
input i_afe_rx_uphy_startloop_pll,
input [1:0] i_afe_rx_uphy_hsclk_division_factor,
input [7:0] i_afe_rx_uphy_rx_pma_opmode,
input [1:0] i_afe_tx_enable_hsclk_division,
input i_afe_tx_enable_ldo,
input i_afe_tx_enable_ref,
input i_afe_tx_enable_supply_hsclk,
input i_afe_tx_enable_supply_pipe,
input i_afe_tx_enable_supply_serializer,
input i_afe_tx_enable_supply_uphy,
input i_afe_tx_hs_ser_rstb,
input [19:0] i_afe_tx_hs_symbol,
input i_afe_tx_mphy_tx_ls_data,
input [1:0] i_afe_tx_pipe_tx_enable_idle_mode,
input [1:0] i_afe_tx_pipe_tx_enable_lfps,
input i_afe_tx_pipe_tx_enable_rxdet,
input [7:0] i_afe_TX_uphy_txpma_opmode,
input i_afe_TX_pmadig_digital_reset_n,
input i_afe_TX_serializer_rst_rel,
input i_afe_TX_pll_symb_clk_2,
input [1:0] i_afe_TX_ana_if_rate,
input i_afe_TX_en_dig_sublp_mode,
input [2:0] i_afe_TX_LPBK_SEL,
input i_afe_TX_iso_ctrl_bar,
input i_afe_TX_ser_iso_ctrl_bar,
input i_afe_TX_lfps_clk,
input i_afe_TX_serializer_rstb,
output o_afe_TX_dig_reset_rel_ack,
output o_afe_TX_pipe_TX_dn_rxdet,
output o_afe_TX_pipe_TX_dp_rxdet,
input i_afe_tx_pipe_tx_fast_est_common_mode,
output o_dbg_l0_txclk,
output o_dbg_l0_rxclk,
output o_dbg_l1_txclk,
output o_dbg_l1_rxclk,
output o_dbg_l2_txclk,
output o_dbg_l2_rxclk,
output o_dbg_l3_txclk,
output o_dbg_l3_rxclk
);
// [5:0]AxUSER driven by PL-AXI_ID
// [9:6]AxUSER tied to 4'b1111
// [15:10]AxUSER tied to 6'b000000
//Write channel
// assign sacefpd_awuser[15:10] = 6'b000000;
// assign sacefpd_awuser[9:6] = 4'b1111;
//Read Channel
// assign sacefpd_aruser[15:10] = 6'b000000;
// assign sacefpd_aruser[9:6] = 4'b1111;
wire emio_sdio0_cmdena_i ;
wire [C_SD0_INTERNAL_BUS_WIDTH-1:0] emio_sdio0_dataena_i;
wire emio_sdio1_cmdena_i;
wire [C_SD1_INTERNAL_BUS_WIDTH-1:0] emio_sdio1_dataena_i;
wire [3:0] pl_clk_unbuffered ;
wire [3:0] pl_clk_buffered ;
wire [127:0] maxigp0_wdata_i;
wire [127:0] maxigp1_wdata_i;
wire [127:0] maxigp2_wdata_i;
wire [127:0] saxigp0_wdata_i;
wire [127:0] saxigp1_wdata_i;
wire [127:0] saxigp2_wdata_i;
wire [127:0] saxigp3_wdata_i;
wire [127:0] saxigp4_wdata_i;
wire [127:0] saxigp5_wdata_i;
wire [127:0] saxigp6_wdata_i;
wire [127:0] maxigp0_rdata_i;
wire [127:0] maxigp1_rdata_i;
wire [127:0] maxigp2_rdata_i;
wire [127:0] saxigp0_rdata_i;
wire [127:0] saxigp1_rdata_i;
wire [127:0] saxigp2_rdata_i;
wire [127:0] saxigp3_rdata_i;
wire [127:0] saxigp4_rdata_i;
wire [127:0] saxigp5_rdata_i;
wire [127:0] saxigp6_rdata_i;
wire [15:0] maxigp0_wstrb_i;
wire [15:0] maxigp1_wstrb_i;
wire [15:0] maxigp2_wstrb_i;
wire [15:0] saxigp0_wstrb_i;
wire [15:0] saxigp1_wstrb_i;
wire [15:0] saxigp2_wstrb_i;
wire [15:0] saxigp3_wstrb_i;
wire [15:0] saxigp4_wstrb_i;
wire [15:0] saxigp5_wstrb_i;
wire [15:0] saxigp6_wstrb_i;
wire [7:0] irq_f2p_0_i;
wire [7:0] irq_f2p_0_null = 8'h00;
wire [7:0] irq_f2p_1_i;
wire [7:0] irq_f2p_1_null = 8'h00;
wire [95:0] emio_gpio_o_temp;
wire [95:0] emio_gpio_i_temp;
wire [95:0] emio_gpio_t_temp;
wire saxihpc0_fpd_rclk_temp;
wire saxihpc0_fpd_wclk_temp;
wire saxihpc1_fpd_rclk_temp;
wire saxihpc1_fpd_wclk_temp;
wire saxihp0_fpd_rclk_temp;
wire saxihp0_fpd_wclk_temp;
wire saxihp1_fpd_rclk_temp;
wire saxihp1_fpd_wclk_temp;
wire saxihp2_fpd_rclk_temp;
wire saxihp2_fpd_wclk_temp;
wire saxihp3_fpd_rclk_temp;
wire saxihp3_fpd_wclk_temp;
wire saxi_lpd_rclk_temp;
wire saxi_lpd_wclk_temp;
wire emio_i2c0_sda_tri;
wire emio_i2c0_scl_tri;
wire emio_i2c1_sda_tri;
wire emio_i2c1_scl_tri;
wire emio_enet0_mdio_tri;
wire emio_enet1_mdio_tri;
wire emio_enet2_mdio_tri;
wire emio_enet3_mdio_tri;
wire emio_gpio_tri;
wire emio_spi0_sclk_tri;
wire emio_spi0_mo_tri;
wire emio_spi0_so_tri;
wire emio_spi0_ss_n_tri;
wire emio_spi1_sclk_tri;
wire emio_spi1_mo_tri;
wire emio_spi1_so_tri;
wire emio_spi1_ss_n_tri;
wire [18:0] ps_pl_irq_lpd_low;
wire [19:0] ps_pl_irq_fpd_low;
wire dp_video_ref_clk_i ;
wire dp_audio_ref_clk_i ;
wire fmio_gem0_fifo_rx_clk ;
wire fmio_gem0_fifo_tx_clk ;
wire fmio_gem0_fifo_rx_clk_temp ;
wire fmio_gem0_fifo_tx_clk_temp ;
wire fmio_gem1_fifo_rx_clk ;
wire fmio_gem1_fifo_tx_clk ;
wire fmio_gem1_fifo_rx_clk_temp ;
wire fmio_gem1_fifo_tx_clk_temp ;
wire fmio_gem2_fifo_rx_clk ;
wire fmio_gem2_fifo_tx_clk ;
wire fmio_gem2_fifo_rx_clk_temp ;
wire fmio_gem2_fifo_tx_clk_temp ;
wire fmio_gem3_fifo_rx_clk ;
wire fmio_gem3_fifo_tx_clk ;
wire fmio_gem3_fifo_rx_clk_temp ;
wire fmio_gem3_fifo_tx_clk_temp ;
generate
if (C_EN_FIFO_ENET0 == "1") begin
assign fmio_gem0_fifo_rx_clk = fmio_gem0_fifo_rx_clk_temp ;
assign fmio_gem0_fifo_tx_clk = fmio_gem0_fifo_tx_clk_temp ;
end else begin
assign fmio_gem0_fifo_rx_clk = 0;
assign fmio_gem0_fifo_tx_clk = 0;
end
endgenerate
generate
if (C_EN_FIFO_ENET1 == "1") begin
assign fmio_gem1_fifo_rx_clk = fmio_gem1_fifo_rx_clk_temp ;
assign fmio_gem1_fifo_tx_clk = fmio_gem1_fifo_tx_clk_temp ;
end else begin
assign fmio_gem1_fifo_rx_clk = 0;
assign fmio_gem1_fifo_tx_clk = 0;
end
endgenerate
generate
if (C_EN_FIFO_ENET2 == "1") begin
assign fmio_gem2_fifo_rx_clk = fmio_gem2_fifo_rx_clk_temp ;
assign fmio_gem2_fifo_tx_clk = fmio_gem2_fifo_tx_clk_temp ;
end else begin
assign fmio_gem2_fifo_rx_clk = 0;
assign fmio_gem2_fifo_tx_clk = 0;
end
endgenerate
generate
if (C_EN_FIFO_ENET3 == "1") begin
assign fmio_gem3_fifo_rx_clk = fmio_gem3_fifo_rx_clk_temp ;
assign fmio_gem3_fifo_tx_clk = fmio_gem3_fifo_tx_clk_temp ;
end else begin
assign fmio_gem3_fifo_rx_clk = 0;
assign fmio_gem3_fifo_tx_clk = 0;
end
endgenerate
assign fmio_gem0_fifo_rx_clk_to_pl_bufg = fmio_gem0_fifo_rx_clk_temp ;
assign fmio_gem0_fifo_tx_clk_to_pl_bufg = fmio_gem0_fifo_tx_clk_temp ;
assign fmio_gem1_fifo_rx_clk_to_pl_bufg = fmio_gem1_fifo_rx_clk_temp ;
assign fmio_gem1_fifo_tx_clk_to_pl_bufg = fmio_gem1_fifo_tx_clk_temp ;
assign fmio_gem2_fifo_rx_clk_to_pl_bufg = fmio_gem2_fifo_rx_clk_temp ;
assign fmio_gem2_fifo_tx_clk_to_pl_bufg = fmio_gem2_fifo_tx_clk_temp ;
assign fmio_gem3_fifo_rx_clk_to_pl_bufg = fmio_gem3_fifo_rx_clk_temp ;
assign fmio_gem3_fifo_tx_clk_to_pl_bufg = fmio_gem3_fifo_tx_clk_temp ;
// Adding tristate inverters
assign emio_sdio0_cmdena = ~emio_sdio0_cmdena_i ;
assign emio_sdio0_dataena = ~emio_sdio0_dataena_i ;
assign emio_sdio1_cmdena = ~emio_sdio1_cmdena_i ;
assign emio_sdio1_dataena = ~emio_sdio1_dataena_i;
assign emio_i2c0_sda_t_n = emio_i2c0_sda_tri;
assign emio_i2c0_sda_t = ~emio_i2c0_sda_tri;
assign emio_i2c0_scl_t_n = emio_i2c0_scl_tri;
assign emio_i2c0_scl_t = ~emio_i2c0_scl_tri;
assign emio_i2c1_sda_t_n = emio_i2c1_sda_tri;
assign emio_i2c1_sda_t = ~emio_i2c1_sda_tri;
assign emio_i2c1_scl_t_n = emio_i2c1_scl_tri;
assign emio_i2c1_scl_t = ~emio_i2c1_scl_tri;
assign emio_enet0_mdio_t_n = emio_enet0_mdio_tri;
assign emio_enet0_mdio_t = ~emio_enet0_mdio_tri;
assign emio_enet1_mdio_t_n = emio_enet1_mdio_tri;
assign emio_enet1_mdio_t = ~emio_enet1_mdio_tri;
assign emio_enet2_mdio_t_n = emio_enet2_mdio_tri;
assign emio_enet2_mdio_t = ~emio_enet2_mdio_tri;
assign emio_enet3_mdio_t_n = emio_enet3_mdio_tri;
assign emio_enet3_mdio_t = ~emio_enet3_mdio_tri;
assign emio_spi0_sclk_t_n = emio_spi0_sclk_tri;
assign emio_spi0_sclk_t = ~emio_spi0_sclk_tri;
assign emio_spi1_sclk_t_n = emio_spi1_sclk_tri;
assign emio_spi1_sclk_t = ~emio_spi1_sclk_tri;
assign emio_spi0_mo_t_n = emio_spi0_mo_tri;
assign emio_spi0_mo_t = ~emio_spi0_mo_tri;
assign emio_spi1_mo_t_n = emio_spi1_mo_tri;
assign emio_spi1_mo_t = ~emio_spi1_mo_tri;
assign emio_spi0_so_t_n = emio_spi0_so_tri;
assign emio_spi0_so_t = ~emio_spi0_so_tri;
assign emio_spi1_so_t_n = emio_spi1_so_tri;
assign emio_spi1_so_t = ~emio_spi1_so_tri;
assign emio_spi0_ss_n_t_n = emio_spi0_ss_n_tri;
assign emio_spi0_ss_n_t = ~emio_spi0_ss_n_tri;
assign emio_spi1_ss_n_t_n = emio_spi1_ss_n_tri;
assign emio_spi1_ss_n_t = ~emio_spi1_ss_n_tri;
generate
if (C_USE_DIFF_RW_CLK_GP0 == 0) begin : clk_assign0
assign saxihpc0_fpd_rclk_temp = saxihpc0_fpd_aclk ;
assign saxihpc0_fpd_wclk_temp = saxihpc0_fpd_aclk ;
end
else begin
assign saxihpc0_fpd_rclk_temp = saxihpc0_fpd_rclk ;
assign saxihpc0_fpd_wclk_temp = saxihpc0_fpd_wclk ;
end
if (C_USE_DIFF_RW_CLK_GP1 == 0) begin : clk_assign1
assign saxihpc1_fpd_rclk_temp = saxihpc1_fpd_aclk ;
assign saxihpc1_fpd_wclk_temp = saxihpc1_fpd_aclk ;
end
else begin
assign saxihpc1_fpd_rclk_temp = saxihpc1_fpd_rclk ;
assign saxihpc1_fpd_wclk_temp = saxihpc1_fpd_wclk ;
end
if (C_USE_DIFF_RW_CLK_GP2 == 0) begin : clk_assign2
assign saxihp0_fpd_rclk_temp = saxihp0_fpd_aclk ;
assign saxihp0_fpd_wclk_temp = saxihp0_fpd_aclk ;
end
else begin
assign saxihp0_fpd_rclk_temp = saxihp0_fpd_rclk ;
assign saxihp0_fpd_wclk_temp = saxihp0_fpd_wclk ;
end
if (C_USE_DIFF_RW_CLK_GP3 == 0) begin : clk_assign3
assign saxihp1_fpd_rclk_temp = saxihp1_fpd_aclk ;
assign saxihp1_fpd_wclk_temp = saxihp1_fpd_aclk ;
end
else begin
assign saxihp1_fpd_rclk_temp = saxihp1_fpd_rclk ;
assign saxihp1_fpd_wclk_temp = saxihp1_fpd_wclk ;
end
if (C_USE_DIFF_RW_CLK_GP4 == 0) begin : clk_assign4
assign saxihp2_fpd_rclk_temp = saxihp2_fpd_aclk ;
assign saxihp2_fpd_wclk_temp = saxihp2_fpd_aclk ;
end
else begin
assign saxihp2_fpd_rclk_temp = saxihp2_fpd_rclk ;
assign saxihp2_fpd_wclk_temp = saxihp2_fpd_wclk ;
end
if (C_USE_DIFF_RW_CLK_GP5 == 0) begin : clk_assign5
assign saxihp3_fpd_rclk_temp = saxihp3_fpd_aclk ;
assign saxihp3_fpd_wclk_temp = saxihp3_fpd_aclk ;
end
else begin
assign saxihp3_fpd_rclk_temp = saxihp3_fpd_rclk ;
assign saxihp3_fpd_wclk_temp = saxihp3_fpd_wclk ;
end
if (C_USE_DIFF_RW_CLK_GP6 == 0) begin : clk_assign6
assign saxi_lpd_rclk_temp = saxi_lpd_aclk ;
assign saxi_lpd_wclk_temp = saxi_lpd_aclk ;
end
else begin
assign saxi_lpd_rclk_temp = saxi_lpd_rclk ;
assign saxi_lpd_wclk_temp = saxi_lpd_wclk ;
end
endgenerate
generate
if ( (C_PL_CLK0_BUF == "true") | (C_PL_CLK0_BUF == "TRUE") | (C_PL_CLK0_BUF == 1) | (C_PL_CLK0_BUF == 'b1)) begin : buffer_pl_clk_0
BUFG_PS PL_CLK_0_BUFG (.I(pl_clk_unbuffered[0]), .O(pl_clk_buffered[0]));
end
else begin
assign pl_clk_buffered[0] = pl_clk_unbuffered[0];
end
if ( (C_PL_CLK1_BUF == "true") | (C_PL_CLK1_BUF == "TRUE") | (C_PL_CLK1_BUF == 1) | (C_PL_CLK1_BUF == 'b1)) begin : buffer_pl_clk_1
BUFG_PS PL_CLK_1_BUFG (.I(pl_clk_unbuffered[1]), .O(pl_clk_buffered[1]));
end
else begin
assign pl_clk_buffered[1] = pl_clk_unbuffered[1];
end
if ( (C_PL_CLK2_BUF == "true") | (C_PL_CLK2_BUF == "TRUE") | (C_PL_CLK2_BUF == 1) | (C_PL_CLK2_BUF == 'b1))begin : buffer_pl_clk_2
BUFG_PS PL_CLK_2_BUFG (.I(pl_clk_unbuffered[2]), .O(pl_clk_buffered[2]));
end
else begin
assign pl_clk_buffered[2] = pl_clk_unbuffered[2];
end
if ( (C_PL_CLK3_BUF == "true") | (C_PL_CLK3_BUF == "TRUE") | (C_PL_CLK3_BUF == 1) | (C_PL_CLK3_BUF == 'b1)) begin : buffer_pl_clk_3
BUFG_PS PL_CLK_3_BUFG (.I(pl_clk_unbuffered[3]), .O(pl_clk_buffered[3]));
end
else begin
assign pl_clk_buffered[3] = pl_clk_unbuffered[3];
end
endgenerate
// Assigning the F2P IRQ
//input wire [7:0] pl_ps_irq0,
//input wire [7:0] pl_ps_irq1,
//output wire [99:0] ps_pl_irq_lpd,
//output wire [63:0] ps_pl_irq_fpd,
generate
if(C_NUM_F2P_0_INTR_INPUTS == 0) begin : irq_f2p_0_select_null
assign irq_f2p_0_i[7:0] = {irq_f2p_0_null[7:0]};
end else if(C_NUM_F2P_0_INTR_INPUTS == 8) begin : irq_f2p_select_all
assign irq_f2p_0_i[7:0] = {pl_ps_irq0[7:0]};
end else begin : irq_f2p_select
begin
assign irq_f2p_0_i[7:0] = {irq_f2p_0_null[(7-C_NUM_F2P_0_INTR_INPUTS):0],
pl_ps_irq0[(C_NUM_F2P_0_INTR_INPUTS-1):0]};
end
end
if(C_NUM_F2P_1_INTR_INPUTS == 0) begin : irq_f2p_1_select_null
assign irq_f2p_1_i[7:0] = {irq_f2p_1_null[7:0]};
end else if(C_NUM_F2P_1_INTR_INPUTS == 8) begin : irq_f2p_select_all1
assign irq_f2p_1_i[7:0] = {pl_ps_irq1[7:0]};
end else begin : irq_f2p_select_1
begin
assign irq_f2p_1_i[7:0] = {irq_f2p_1_null[(7-C_NUM_F2P_1_INTR_INPUTS):0],
pl_ps_irq1[(C_NUM_F2P_1_INTR_INPUTS-1):0]};
end
end
endgenerate
//workaround for reset signals using gpio_o signals
generate
assign emio_gpio_o = emio_gpio_o_temp[(C_EMIO_GPIO_WIDTH -1):0];
assign emio_gpio_t = ~emio_gpio_t_temp[(C_EMIO_GPIO_WIDTH -1):0];
assign emio_gpio_t_n = emio_gpio_t_temp[(C_EMIO_GPIO_WIDTH -1):0];
assign emio_gpio_i_temp = {{(96-C_EMIO_GPIO_WIDTH){1'b0}},emio_gpio_i};
if(C_NUM_FABRIC_RESETS == 1) begin
assign pl_resetn0 = emio_gpio_o_temp[95];
assign pl_resetn1 = 1'b1;
assign pl_resetn2 = 1'b1;
assign pl_resetn3 = 1'b1;
end else if(C_NUM_FABRIC_RESETS == 2) begin
assign pl_resetn0 = emio_gpio_o_temp[95];
assign pl_resetn1 = emio_gpio_o_temp[94];
assign pl_resetn2 = 1'b1;
assign pl_resetn3 = 1'b1;
end else if(C_NUM_FABRIC_RESETS == 3) begin
assign pl_resetn0 = emio_gpio_o_temp[95];
assign pl_resetn1 = emio_gpio_o_temp[94];
assign pl_resetn2 = emio_gpio_o_temp[93];
assign pl_resetn3 = 1'b1;
end else begin
assign pl_resetn0 = emio_gpio_o_temp[95];
assign pl_resetn1 = emio_gpio_o_temp[94];
assign pl_resetn2 = emio_gpio_o_temp[93];
assign pl_resetn3 = emio_gpio_o_temp[92];
end
endgenerate
assign pl_clk0 = ((C_PL_CLK0_BUF == "true") | (C_PL_CLK0_BUF == "TRUE") | (C_PL_CLK0_BUF == 1) | (C_PL_CLK0_BUF == 'b1)) ? pl_clk_buffered[0] : pl_clk_unbuffered[0];
assign pl_clk1 = ((C_PL_CLK1_BUF == "true") | (C_PL_CLK1_BUF == "TRUE") | (C_PL_CLK1_BUF == 1) | (C_PL_CLK1_BUF == 'b1)) ? pl_clk_buffered[1] : pl_clk_unbuffered[1];
assign pl_clk2 = ((C_PL_CLK2_BUF == "true") | (C_PL_CLK2_BUF == "TRUE") | (C_PL_CLK2_BUF == 1) | (C_PL_CLK2_BUF == 'b1)) ? pl_clk_buffered[2] : pl_clk_unbuffered[2];
assign pl_clk3 = ((C_PL_CLK3_BUF == "true") | (C_PL_CLK3_BUF == "TRUE") | (C_PL_CLK3_BUF == 1) | (C_PL_CLK3_BUF == 'b1)) ? pl_clk_buffered[3] : pl_clk_unbuffered[3];
wire [C_TRACE_DATA_WIDTH-1:0] trace_data_i;
wire trace_ctl_i;
(* keep = "true" *) reg trace_ctl_pipe [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [C_TRACE_DATA_WIDTH-1:0] trace_data_pipe [(C_TRACE_PIPELINE_WIDTH - 1):0];
// maxigp0
assign maxigp0_wdata = (C_MAXIGP0_DATA_WIDTH == 128) ?
maxigp0_wdata_i : ( (C_MAXIGP0_DATA_WIDTH == 64) ? maxigp0_wdata_i[63:0] : maxigp0_wdata_i[31:0] ) ;
assign maxigp0_wstrb = (C_MAXIGP0_DATA_WIDTH > 0) ? maxigp0_wstrb_i[(C_MAXIGP0_DATA_WIDTH/8)-1:0] : maxigp0_wstrb_i[(32/8)-1:0];
assign maxigp0_rdata_i = (C_MAXIGP0_DATA_WIDTH == 128) ?
maxigp0_rdata : ((C_MAXIGP0_DATA_WIDTH == 64) ? {64'b0, maxigp0_rdata} : {96'b0, maxigp0_rdata}) ;
// maxigp1
assign maxigp1_wdata = (C_MAXIGP1_DATA_WIDTH == 128) ?
maxigp1_wdata_i : ( (C_MAXIGP1_DATA_WIDTH == 64) ? maxigp1_wdata_i[63:0] : maxigp1_wdata_i[31:0] ) ;
assign maxigp1_wstrb = (C_MAXIGP1_DATA_WIDTH > 0) ? maxigp1_wstrb_i[(C_MAXIGP1_DATA_WIDTH/8)-1:0] : maxigp1_wstrb_i[(32/8)-1:0];
assign maxigp1_rdata_i = (C_MAXIGP1_DATA_WIDTH == 128) ?
maxigp1_rdata : ((C_MAXIGP1_DATA_WIDTH == 64) ? {64'b0, maxigp1_rdata} : {96'b0, maxigp1_rdata}) ;
// maxigp2
assign maxigp2_wdata = (C_MAXIGP2_DATA_WIDTH == 128) ?
maxigp2_wdata_i : ( (C_MAXIGP2_DATA_WIDTH == 64) ? maxigp2_wdata_i[63:0] : maxigp2_wdata_i[31:0] ) ;
assign maxigp2_wstrb = (C_MAXIGP2_DATA_WIDTH > 0) ? maxigp2_wstrb_i[(C_MAXIGP2_DATA_WIDTH/8)-1:0] : maxigp2_wstrb_i[(32/8)-1:0];
assign maxigp2_rdata_i = (C_MAXIGP2_DATA_WIDTH == 128) ?
maxigp2_rdata : ((C_MAXIGP2_DATA_WIDTH == 64) ? {64'b0, maxigp2_rdata} : {96'b0, maxigp2_rdata}) ;
// saxigp0
assign saxigp0_wdata_i = (C_SAXIGP0_DATA_WIDTH == 128) ?
saxigp0_wdata : ((C_SAXIGP0_DATA_WIDTH == 64) ? {64'b0, saxigp0_wdata} : {96'b0, saxigp0_wdata}) ;
assign saxigp0_wstrb_i = (C_SAXIGP0_DATA_WIDTH == 128) ?
saxigp0_wstrb : ((C_SAXIGP0_DATA_WIDTH == 64) ? {8'b0, saxigp0_wstrb} : {12'b0, saxigp0_wstrb}) ;
assign saxigp0_rdata = (C_SAXIGP0_DATA_WIDTH == 128) ?
saxigp0_rdata_i : ( (C_SAXIGP0_DATA_WIDTH == 64) ? saxigp0_rdata_i[63:0] : saxigp0_rdata_i[31:0] ) ;
// saxigp1
assign saxigp1_wdata_i = (C_SAXIGP1_DATA_WIDTH == 128) ?
saxigp1_wdata : ((C_SAXIGP1_DATA_WIDTH == 64) ? {64'b0, saxigp1_wdata} : {96'b0, saxigp1_wdata}) ;
assign saxigp1_wstrb_i = (C_SAXIGP1_DATA_WIDTH == 128) ?
saxigp1_wstrb : ((C_SAXIGP1_DATA_WIDTH == 64) ? {8'b0, saxigp1_wstrb} : {12'b0, saxigp1_wstrb}) ;
assign saxigp1_rdata = (C_SAXIGP1_DATA_WIDTH == 128) ?
saxigp1_rdata_i : ( (C_SAXIGP1_DATA_WIDTH == 64) ? saxigp1_rdata_i[63:0] : saxigp1_rdata_i[31:0] ) ;
// saxigp2
assign saxigp2_wdata_i = (C_SAXIGP2_DATA_WIDTH == 128) ?
saxigp2_wdata : ((C_SAXIGP2_DATA_WIDTH == 64) ? {64'b0, saxigp2_wdata} : {96'b0, saxigp2_wdata}) ;
assign saxigp2_wstrb_i = (C_SAXIGP2_DATA_WIDTH == 128) ?
saxigp2_wstrb : ((C_SAXIGP2_DATA_WIDTH == 64) ? {8'b0, saxigp2_wstrb} : {12'b0, saxigp2_wstrb}) ;
assign saxigp2_rdata = (C_SAXIGP2_DATA_WIDTH == 128) ?
saxigp2_rdata_i : ( (C_SAXIGP2_DATA_WIDTH == 64) ? saxigp2_rdata_i[63:0] : saxigp2_rdata_i[31:0] ) ;
// saxigp3
assign saxigp3_wdata_i = (C_SAXIGP3_DATA_WIDTH == 128) ?
saxigp3_wdata : ((C_SAXIGP3_DATA_WIDTH == 64) ? {64'b0, saxigp3_wdata} : {96'b0, saxigp3_wdata}) ;
assign saxigp3_wstrb_i = (C_SAXIGP3_DATA_WIDTH == 128) ?
saxigp3_wstrb : ((C_SAXIGP3_DATA_WIDTH == 64) ? {8'b0, saxigp3_wstrb} : {12'b0, saxigp3_wstrb}) ;
assign saxigp3_rdata = (C_SAXIGP3_DATA_WIDTH == 128) ?
saxigp3_rdata_i : ( (C_SAXIGP3_DATA_WIDTH == 64) ? saxigp3_rdata_i[63:0] : saxigp3_rdata_i[31:0] ) ;
// saxigp4
assign saxigp4_wdata_i = (C_SAXIGP4_DATA_WIDTH == 128) ?
saxigp4_wdata : ((C_SAXIGP4_DATA_WIDTH == 64) ? {64'b0, saxigp4_wdata} : {96'b0, saxigp4_wdata}) ;
assign saxigp4_wstrb_i = (C_SAXIGP4_DATA_WIDTH == 128) ?
saxigp4_wstrb : ((C_SAXIGP4_DATA_WIDTH == 64) ? {8'b0, saxigp4_wstrb} : {12'b0, saxigp4_wstrb}) ;
assign saxigp4_rdata = (C_SAXIGP4_DATA_WIDTH == 128) ?
saxigp4_rdata_i : ( (C_SAXIGP4_DATA_WIDTH == 64) ? saxigp4_rdata_i[63:0] : saxigp4_rdata_i[31:0] ) ;
// saxigp5
assign saxigp5_wdata_i = (C_SAXIGP5_DATA_WIDTH == 128) ?
saxigp5_wdata : ((C_SAXIGP5_DATA_WIDTH == 64) ? {64'b0, saxigp5_wdata} : {96'b0, saxigp5_wdata}) ;
assign saxigp5_wstrb_i = (C_SAXIGP5_DATA_WIDTH == 128) ?
saxigp5_wstrb : ((C_SAXIGP5_DATA_WIDTH == 64) ? {8'b0, saxigp5_wstrb} : {12'b0, saxigp5_wstrb}) ;
assign saxigp5_rdata = (C_SAXIGP5_DATA_WIDTH == 128) ?
saxigp5_rdata_i : ( (C_SAXIGP5_DATA_WIDTH == 64) ? saxigp5_rdata_i[63:0] : saxigp5_rdata_i[31:0] ) ;
// saxigp6
assign saxigp6_wdata_i = (C_SAXIGP6_DATA_WIDTH == 128) ?
saxigp6_wdata : ((C_SAXIGP6_DATA_WIDTH == 64) ? {64'b0, saxigp6_wdata} : {96'b0, saxigp6_wdata}) ;
assign saxigp6_wstrb_i = (C_SAXIGP6_DATA_WIDTH == 128) ?
saxigp6_wstrb : ((C_SAXIGP6_DATA_WIDTH == 64) ? {8'b0, saxigp6_wstrb} : {12'b0, saxigp6_wstrb}) ;
assign saxigp6_rdata = (C_SAXIGP6_DATA_WIDTH == 128) ?
saxigp6_rdata_i : ( (C_SAXIGP6_DATA_WIDTH == 64) ? saxigp6_rdata_i[63:0] : saxigp6_rdata_i[31:0] ) ;
//Trace Pipeline and clk out
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin //Enable EMIO Trace
always @(posedge pl_ps_trace_clk)
begin
//Add date to end of the pipeline
trace_ctl_pipe[C_TRACE_PIPELINE_WIDTH - 1] <= trace_ctl_i;
trace_data_pipe[C_TRACE_PIPELINE_WIDTH - 1] <= trace_data_i;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
trace_ctl_pipe[j-1] <= trace_ctl_pipe[j];
trace_data_pipe[j-1] <= trace_data_pipe[j];
end
//Create Divide by two clock
trace_clk_out <= ~trace_clk_out;
end
end
else begin
always @(posedge pl_ps_trace_clk)
begin
trace_clk_out <= ~trace_clk_out;
end
end
endgenerate
assign ps_pl_tracectl = trace_ctl_pipe[0];
assign ps_pl_tracedata = trace_data_pipe[0];
generate
if (C_DP_USE_VIDEO == 0) begin
assign dp_video_ref_clk = dp_video_ref_clk_i ;
end
else begin
BUFG_PS DP_VID_CLK_BUFG (.I(dp_video_ref_clk_i), .O(dp_video_ref_clk));
end
endgenerate
generate
if(C_DP_USE_AUDIO == 0) begin
assign dp_audi_ref_clk = dp_audio_ref_clk_i ;
end
else
begin
BUFG_PS DP_AUD_CLK_BUFG (.I(dp_audio_ref_clk_i), .O(dp_audio_ref_clk));
end
endgenerate
generate
if (C_USE_DEBUG_TEST == 1) begin
PS8_TEST PS8_TEST_i (
.MAXIGP0ACLK (maxihpm0_fpd_aclk),
.MAXIGP0AWID (maxigp0_awid),
.MAXIGP0AWADDR (maxigp0_awaddr),
.MAXIGP0AWLEN (maxigp0_awlen),
.MAXIGP0AWSIZE (maxigp0_awsize),
.MAXIGP0AWBURST (maxigp0_awburst),
.MAXIGP0AWLOCK (maxigp0_awlock),
.MAXIGP0AWCACHE (maxigp0_awcache),
.MAXIGP0AWPROT (maxigp0_awprot),
.MAXIGP0AWVALID (maxigp0_awvalid),
.MAXIGP0AWUSER (maxigp0_awuser),
.MAXIGP0AWREADY (maxigp0_awready),
.MAXIGP0WDATA (maxigp0_wdata_i),
.MAXIGP0WSTRB (maxigp0_wstrb_i),
.MAXIGP0WLAST (maxigp0_wlast),
.MAXIGP0WVALID (maxigp0_wvalid),
.MAXIGP0WREADY (maxigp0_wready),
.MAXIGP0BID (maxigp0_bid),
.MAXIGP0BRESP (maxigp0_bresp),
.MAXIGP0BVALID (maxigp0_bvalid),
.MAXIGP0BREADY (maxigp0_bready),
.MAXIGP0ARID (maxigp0_arid),
.MAXIGP0ARADDR (maxigp0_araddr),
.MAXIGP0ARLEN (maxigp0_arlen),
.MAXIGP0ARSIZE (maxigp0_arsize),
.MAXIGP0ARBURST (maxigp0_arburst),
.MAXIGP0ARLOCK (maxigp0_arlock),
.MAXIGP0ARCACHE (maxigp0_arcache),
.MAXIGP0ARPROT (maxigp0_arprot),
.MAXIGP0ARVALID (maxigp0_arvalid),
.MAXIGP0ARUSER (maxigp0_aruser),
.MAXIGP0ARREADY (maxigp0_arready),
.MAXIGP0RID (maxigp0_rid),
.MAXIGP0RDATA (maxigp0_rdata_i),
.MAXIGP0RRESP (maxigp0_rresp),
.MAXIGP0RLAST (maxigp0_rlast),
.MAXIGP0RVALID (maxigp0_rvalid),
.MAXIGP0RREADY (maxigp0_rready),
.MAXIGP0AWQOS (maxigp0_awqos),
.MAXIGP0ARQOS (maxigp0_arqos),
.MAXIGP1ACLK (maxihpm1_fpd_aclk),
.MAXIGP1AWID (maxigp1_awid),
.MAXIGP1AWADDR (maxigp1_awaddr),
.MAXIGP1AWLEN (maxigp1_awlen),
.MAXIGP1AWSIZE (maxigp1_awsize),
.MAXIGP1AWBURST (maxigp1_awburst),
.MAXIGP1AWLOCK (maxigp1_awlock),
.MAXIGP1AWCACHE (maxigp1_awcache),
.MAXIGP1AWPROT (maxigp1_awprot),
.MAXIGP1AWVALID (maxigp1_awvalid),
.MAXIGP1AWUSER (maxigp1_awuser),
.MAXIGP1AWREADY (maxigp1_awready),
.MAXIGP1WDATA (maxigp1_wdata_i),
.MAXIGP1WSTRB (maxigp1_wstrb_i),
.MAXIGP1WLAST (maxigp1_wlast),
.MAXIGP1WVALID (maxigp1_wvalid),
.MAXIGP1WREADY (maxigp1_wready),
.MAXIGP1BID (maxigp1_bid),
.MAXIGP1BRESP (maxigp1_bresp),
.MAXIGP1BVALID (maxigp1_bvalid),
.MAXIGP1BREADY (maxigp1_bready),
.MAXIGP1ARID (maxigp1_arid),
.MAXIGP1ARADDR (maxigp1_araddr),
.MAXIGP1ARLEN (maxigp1_arlen),
.MAXIGP1ARSIZE (maxigp1_arsize),
.MAXIGP1ARBURST (maxigp1_arburst),
.MAXIGP1ARLOCK (maxigp1_arlock),
.MAXIGP1ARCACHE (maxigp1_arcache),
.MAXIGP1ARPROT (maxigp1_arprot),
.MAXIGP1ARVALID (maxigp1_arvalid),
.MAXIGP1ARUSER (maxigp1_aruser),
.MAXIGP1ARREADY (maxigp1_arready),
.MAXIGP1RID (maxigp1_rid),
.MAXIGP1RDATA (maxigp1_rdata_i),
.MAXIGP1RRESP (maxigp1_rresp),
.MAXIGP1RLAST (maxigp1_rlast),
.MAXIGP1RVALID (maxigp1_rvalid),
.MAXIGP1RREADY (maxigp1_rready),
.MAXIGP1AWQOS (maxigp1_awqos),
.MAXIGP1ARQOS (maxigp1_arqos),
.MAXIGP2ACLK (maxihpm0_lpd_aclk),
.MAXIGP2AWID (maxigp2_awid),
.MAXIGP2AWADDR (maxigp2_awaddr),
.MAXIGP2AWLEN (maxigp2_awlen),
.MAXIGP2AWSIZE (maxigp2_awsize),
.MAXIGP2AWBURST (maxigp2_awburst),
.MAXIGP2AWLOCK (maxigp2_awlock),
.MAXIGP2AWCACHE (maxigp2_awcache),
.MAXIGP2AWPROT (maxigp2_awprot),
.MAXIGP2AWVALID (maxigp2_awvalid),
.MAXIGP2AWUSER (maxigp2_awuser),
.MAXIGP2AWREADY (maxigp2_awready),
.MAXIGP2WDATA (maxigp2_wdata_i),
.MAXIGP2WSTRB (maxigp2_wstrb_i),
.MAXIGP2WLAST (maxigp2_wlast),
.MAXIGP2WVALID (maxigp2_wvalid),
.MAXIGP2WREADY (maxigp2_wready),
.MAXIGP2BID (maxigp2_bid),
.MAXIGP2BRESP (maxigp2_bresp),
.MAXIGP2BVALID (maxigp2_bvalid),
.MAXIGP2BREADY (maxigp2_bready),
.MAXIGP2ARID (maxigp2_arid),
.MAXIGP2ARADDR (maxigp2_araddr),
.MAXIGP2ARLEN (maxigp2_arlen),
.MAXIGP2ARSIZE (maxigp2_arsize),
.MAXIGP2ARBURST (maxigp2_arburst),
.MAXIGP2ARLOCK (maxigp2_arlock),
.MAXIGP2ARCACHE (maxigp2_arcache),
.MAXIGP2ARPROT (maxigp2_arprot),
.MAXIGP2ARVALID (maxigp2_arvalid),
.MAXIGP2ARUSER (maxigp2_aruser),
.MAXIGP2ARREADY (maxigp2_arready),
.MAXIGP2RID (maxigp2_rid),
.MAXIGP2RDATA (maxigp2_rdata_i),
.MAXIGP2RRESP (maxigp2_rresp),
.MAXIGP2RLAST (maxigp2_rlast),
.MAXIGP2RVALID (maxigp2_rvalid),
.MAXIGP2RREADY (maxigp2_rready),
.MAXIGP2AWQOS (maxigp2_awqos),
.MAXIGP2ARQOS (maxigp2_arqos),
.SAXIGP0RCLK (saxihpc0_fpd_rclk_temp),
.SAXIGP0WCLK (saxihpc0_fpd_wclk_temp),
.SAXIGP0ARUSER (saxigp0_aruser),
.SAXIGP0AWUSER (saxigp0_awuser),
.SAXIGP0AWID (saxigp0_awid),
.SAXIGP0AWADDR (saxigp0_awaddr),
.SAXIGP0AWLEN (saxigp0_awlen),
.SAXIGP0AWSIZE (saxigp0_awsize),
.SAXIGP0AWBURST (saxigp0_awburst),
.SAXIGP0AWLOCK (saxigp0_awlock),
.SAXIGP0AWCACHE (saxigp0_awcache),
.SAXIGP0AWPROT (saxigp0_awprot),
.SAXIGP0AWVALID (saxigp0_awvalid),
.SAXIGP0AWREADY (saxigp0_awready),
.SAXIGP0WDATA (saxigp0_wdata_i),
.SAXIGP0WSTRB (saxigp0_wstrb_i),
.SAXIGP0WLAST (saxigp0_wlast),
.SAXIGP0WVALID (saxigp0_wvalid),
.SAXIGP0WREADY (saxigp0_wready),
.SAXIGP0BID (saxigp0_bid),
.SAXIGP0BRESP (saxigp0_bresp),
.SAXIGP0BVALID (saxigp0_bvalid),
.SAXIGP0BREADY (saxigp0_bready),
.SAXIGP0ARID (saxigp0_arid),
.SAXIGP0ARADDR (saxigp0_araddr),
.SAXIGP0ARLEN (saxigp0_arlen),
.SAXIGP0ARSIZE (saxigp0_arsize),
.SAXIGP0ARBURST (saxigp0_arburst),
.SAXIGP0ARLOCK (saxigp0_arlock),
.SAXIGP0ARCACHE (saxigp0_arcache),
.SAXIGP0ARPROT (saxigp0_arprot),
.SAXIGP0ARVALID (saxigp0_arvalid),
.SAXIGP0ARREADY (saxigp0_arready),
.SAXIGP0RID (saxigp0_rid),
.SAXIGP0RDATA (saxigp0_rdata_i),
.SAXIGP0RRESP (saxigp0_rresp),
.SAXIGP0RLAST (saxigp0_rlast),
.SAXIGP0RVALID (saxigp0_rvalid),
.SAXIGP0RREADY (saxigp0_rready),
.SAXIGP0AWQOS (saxigp0_awqos),
.SAXIGP0ARQOS (saxigp0_arqos),
.SAXIGP0RCOUNT (saxigp0_rcount),
.SAXIGP0WCOUNT (saxigp0_wcount),
.SAXIGP0RACOUNT (saxigp0_racount),
.SAXIGP0WACOUNT (saxigp0_wacount),
.SAXIGP1RCLK (saxihpc1_fpd_rclk_temp),
.SAXIGP1WCLK (saxihpc1_fpd_wclk_temp),
.SAXIGP1ARUSER (saxigp1_aruser),
.SAXIGP1AWUSER (saxigp1_awuser),
.SAXIGP1AWID (saxigp1_awid),
.SAXIGP1AWADDR (saxigp1_awaddr),
.SAXIGP1AWLEN (saxigp1_awlen),
.SAXIGP1AWSIZE (saxigp1_awsize),
.SAXIGP1AWBURST (saxigp1_awburst),
.SAXIGP1AWLOCK (saxigp1_awlock),
.SAXIGP1AWCACHE (saxigp1_awcache),
.SAXIGP1AWPROT (saxigp1_awprot),
.SAXIGP1AWVALID (saxigp1_awvalid),
.SAXIGP1AWREADY (saxigp1_awready),
.SAXIGP1WDATA (saxigp1_wdata_i),
.SAXIGP1WSTRB (saxigp1_wstrb_i),
.SAXIGP1WLAST (saxigp1_wlast),
.SAXIGP1WVALID (saxigp1_wvalid),
.SAXIGP1WREADY (saxigp1_wready),
.SAXIGP1BID (saxigp1_bid),
.SAXIGP1BRESP (saxigp1_bresp),
.SAXIGP1BVALID (saxigp1_bvalid),
.SAXIGP1BREADY (saxigp1_bready),
.SAXIGP1ARID (saxigp1_arid),
.SAXIGP1ARADDR (saxigp1_araddr),
.SAXIGP1ARLEN (saxigp1_arlen),
.SAXIGP1ARSIZE (saxigp1_arsize),
.SAXIGP1ARBURST (saxigp1_arburst),
.SAXIGP1ARLOCK (saxigp1_arlock),
.SAXIGP1ARCACHE (saxigp1_arcache),
.SAXIGP1ARPROT (saxigp1_arprot),
.SAXIGP1ARVALID (saxigp1_arvalid),
.SAXIGP1ARREADY (saxigp1_arready),
.SAXIGP1RID (saxigp1_rid),
.SAXIGP1RDATA (saxigp1_rdata_i),
.SAXIGP1RRESP (saxigp1_rresp),
.SAXIGP1RLAST (saxigp1_rlast),
.SAXIGP1RVALID (saxigp1_rvalid),
.SAXIGP1RREADY (saxigp1_rready),
.SAXIGP1AWQOS (saxigp1_awqos),
.SAXIGP1ARQOS (saxigp1_arqos),
.SAXIGP1RCOUNT (saxigp1_rcount),
.SAXIGP1WCOUNT (saxigp1_wcount),
.SAXIGP1RACOUNT (saxigp1_racount),
.SAXIGP1WACOUNT (saxigp1_wacount),
.SAXIGP2RCLK (saxihp0_fpd_rclk_temp),
.SAXIGP2WCLK (saxihp0_fpd_wclk_temp),
.SAXIGP2ARUSER (saxigp2_aruser),
.SAXIGP2AWUSER (saxigp2_awuser),
.SAXIGP2AWID (saxigp2_awid),
.SAXIGP2AWADDR (saxigp2_awaddr),
.SAXIGP2AWLEN (saxigp2_awlen),
.SAXIGP2AWSIZE (saxigp2_awsize),
.SAXIGP2AWBURST (saxigp2_awburst),
.SAXIGP2AWLOCK (saxigp2_awlock),
.SAXIGP2AWCACHE (saxigp2_awcache),
.SAXIGP2AWPROT (saxigp2_awprot),
.SAXIGP2AWVALID (saxigp2_awvalid),
.SAXIGP2AWREADY (saxigp2_awready),
.SAXIGP2WDATA (saxigp2_wdata_i),
.SAXIGP2WSTRB (saxigp2_wstrb_i),
.SAXIGP2WLAST (saxigp2_wlast),
.SAXIGP2WVALID (saxigp2_wvalid),
.SAXIGP2WREADY (saxigp2_wready),
.SAXIGP2BID (saxigp2_bid),
.SAXIGP2BRESP (saxigp2_bresp),
.SAXIGP2BVALID (saxigp2_bvalid),
.SAXIGP2BREADY (saxigp2_bready),
.SAXIGP2ARID (saxigp2_arid),
.SAXIGP2ARADDR (saxigp2_araddr),
.SAXIGP2ARLEN (saxigp2_arlen),
.SAXIGP2ARSIZE (saxigp2_arsize),
.SAXIGP2ARBURST (saxigp2_arburst),
.SAXIGP2ARLOCK (saxigp2_arlock),
.SAXIGP2ARCACHE (saxigp2_arcache),
.SAXIGP2ARPROT (saxigp2_arprot),
.SAXIGP2ARVALID (saxigp2_arvalid),
.SAXIGP2ARREADY (saxigp2_arready),
.SAXIGP2RID (saxigp2_rid),
.SAXIGP2RDATA (saxigp2_rdata_i),
.SAXIGP2RRESP (saxigp2_rresp),
.SAXIGP2RLAST (saxigp2_rlast),
.SAXIGP2RVALID (saxigp2_rvalid),
.SAXIGP2RREADY (saxigp2_rready),
.SAXIGP2AWQOS (saxigp2_awqos),
.SAXIGP2ARQOS (saxigp2_arqos),
.SAXIGP2RCOUNT (saxigp2_rcount),
.SAXIGP2WCOUNT (saxigp2_wcount),
.SAXIGP2RACOUNT (saxigp2_racount),
.SAXIGP2WACOUNT (saxigp2_wacount),
.SAXIGP3RCLK (saxihp1_fpd_rclk_temp),
.SAXIGP3WCLK (saxihp1_fpd_wclk_temp),
.SAXIGP3ARUSER (saxigp3_aruser),
.SAXIGP3AWUSER (saxigp3_awuser),
.SAXIGP3AWID (saxigp3_awid),
.SAXIGP3AWADDR (saxigp3_awaddr),
.SAXIGP3AWLEN (saxigp3_awlen),
.SAXIGP3AWSIZE (saxigp3_awsize),
.SAXIGP3AWBURST (saxigp3_awburst),
.SAXIGP3AWLOCK (saxigp3_awlock),
.SAXIGP3AWCACHE (saxigp3_awcache),
.SAXIGP3AWPROT (saxigp3_awprot),
.SAXIGP3AWVALID (saxigp3_awvalid),
.SAXIGP3AWREADY (saxigp3_awready),
.SAXIGP3WDATA (saxigp3_wdata_i),
.SAXIGP3WSTRB (saxigp3_wstrb_i),
.SAXIGP3WLAST (saxigp3_wlast),
.SAXIGP3WVALID (saxigp3_wvalid),
.SAXIGP3WREADY (saxigp3_wready),
.SAXIGP3BID (saxigp3_bid),
.SAXIGP3BRESP (saxigp3_bresp),
.SAXIGP3BVALID (saxigp3_bvalid),
.SAXIGP3BREADY (saxigp3_bready),
.SAXIGP3ARID (saxigp3_arid),
.SAXIGP3ARADDR (saxigp3_araddr),
.SAXIGP3ARLEN (saxigp3_arlen),
.SAXIGP3ARSIZE (saxigp3_arsize),
.SAXIGP3ARBURST (saxigp3_arburst),
.SAXIGP3ARLOCK (saxigp3_arlock),
.SAXIGP3ARCACHE (saxigp3_arcache),
.SAXIGP3ARPROT (saxigp3_arprot),
.SAXIGP3ARVALID (saxigp3_arvalid),
.SAXIGP3ARREADY (saxigp3_arready),
.SAXIGP3RID (saxigp3_rid),
.SAXIGP3RDATA (saxigp3_rdata_i),
.SAXIGP3RRESP (saxigp3_rresp),
.SAXIGP3RLAST (saxigp3_rlast),
.SAXIGP3RVALID (saxigp3_rvalid),
.SAXIGP3RREADY (saxigp3_rready),
.SAXIGP3AWQOS (saxigp3_awqos),
.SAXIGP3ARQOS (saxigp3_arqos),
.SAXIGP3RCOUNT (saxigp3_rcount),
.SAXIGP3WCOUNT (saxigp3_wcount),
.SAXIGP3RACOUNT (saxigp3_racount),
.SAXIGP3WACOUNT (saxigp3_wacount),
.SAXIGP4RCLK (saxihp2_fpd_rclk_temp),
.SAXIGP4WCLK (saxihp2_fpd_wclk_temp),
.SAXIGP4ARUSER (saxigp4_aruser),
.SAXIGP4AWUSER (saxigp4_awuser),
.SAXIGP4AWID (saxigp4_awid),
.SAXIGP4AWADDR (saxigp4_awaddr),
.SAXIGP4AWLEN (saxigp4_awlen),
.SAXIGP4AWSIZE (saxigp4_awsize),
.SAXIGP4AWBURST (saxigp4_awburst),
.SAXIGP4AWLOCK (saxigp4_awlock),
.SAXIGP4AWCACHE (saxigp4_awcache),
.SAXIGP4AWPROT (saxigp4_awprot),
.SAXIGP4AWVALID (saxigp4_awvalid),
.SAXIGP4AWREADY (saxigp4_awready),
.SAXIGP4WDATA (saxigp4_wdata_i),
.SAXIGP4WSTRB (saxigp4_wstrb_i),
.SAXIGP4WLAST (saxigp4_wlast),
.SAXIGP4WVALID (saxigp4_wvalid),
.SAXIGP4WREADY (saxigp4_wready),
.SAXIGP4BID (saxigp4_bid),
.SAXIGP4BRESP (saxigp4_bresp),
.SAXIGP4BVALID (saxigp4_bvalid),
.SAXIGP4BREADY (saxigp4_bready),
.SAXIGP4ARID (saxigp4_arid),
.SAXIGP4ARADDR (saxigp4_araddr),
.SAXIGP4ARLEN (saxigp4_arlen),
.SAXIGP4ARSIZE (saxigp4_arsize),
.SAXIGP4ARBURST (saxigp4_arburst),
.SAXIGP4ARLOCK (saxigp4_arlock),
.SAXIGP4ARCACHE (saxigp4_arcache),
.SAXIGP4ARPROT (saxigp4_arprot),
.SAXIGP4ARVALID (saxigp4_arvalid),
.SAXIGP4ARREADY (saxigp4_arready),
.SAXIGP4RID (saxigp4_rid),
.SAXIGP4RDATA (saxigp4_rdata_i),
.SAXIGP4RRESP (saxigp4_rresp),
.SAXIGP4RLAST (saxigp4_rlast),
.SAXIGP4RVALID (saxigp4_rvalid),
.SAXIGP4RREADY (saxigp4_rready),
.SAXIGP4AWQOS (saxigp4_awqos),
.SAXIGP4ARQOS (saxigp4_arqos),
.SAXIGP4RCOUNT (saxigp4_rcount),
.SAXIGP4WCOUNT (saxigp4_wcount),
.SAXIGP4RACOUNT (saxigp4_racount),
.SAXIGP4WACOUNT (saxigp4_wacount),
.SAXIGP5RCLK (saxihp3_fpd_rclk_temp),
.SAXIGP5WCLK (saxihp3_fpd_wclk_temp),
.SAXIGP5ARUSER (saxigp5_aruser),
.SAXIGP5AWUSER (saxigp5_awuser),
.SAXIGP5AWID (saxigp5_awid),
.SAXIGP5AWADDR (saxigp5_awaddr),
.SAXIGP5AWLEN (saxigp5_awlen),
.SAXIGP5AWSIZE (saxigp5_awsize),
.SAXIGP5AWBURST (saxigp5_awburst),
.SAXIGP5AWLOCK (saxigp5_awlock),
.SAXIGP5AWCACHE (saxigp5_awcache),
.SAXIGP5AWPROT (saxigp5_awprot),
.SAXIGP5AWVALID (saxigp5_awvalid),
.SAXIGP5AWREADY (saxigp5_awready),
.SAXIGP5WDATA (saxigp5_wdata_i),
.SAXIGP5WSTRB (saxigp5_wstrb_i),
.SAXIGP5WLAST (saxigp5_wlast),
.SAXIGP5WVALID (saxigp5_wvalid),
.SAXIGP5WREADY (saxigp5_wready),
.SAXIGP5BID (saxigp5_bid),
.SAXIGP5BRESP (saxigp5_bresp),
.SAXIGP5BVALID (saxigp5_bvalid),
.SAXIGP5BREADY (saxigp5_bready),
.SAXIGP5ARID (saxigp5_arid),
.SAXIGP5ARADDR (saxigp5_araddr),
.SAXIGP5ARLEN (saxigp5_arlen),
.SAXIGP5ARSIZE (saxigp5_arsize),
.SAXIGP5ARBURST (saxigp5_arburst),
.SAXIGP5ARLOCK (saxigp5_arlock),
.SAXIGP5ARCACHE (saxigp5_arcache),
.SAXIGP5ARPROT (saxigp5_arprot),
.SAXIGP5ARVALID (saxigp5_arvalid),
.SAXIGP5ARREADY (saxigp5_arready),
.SAXIGP5RID (saxigp5_rid),
.SAXIGP5RDATA (saxigp5_rdata_i),
.SAXIGP5RRESP (saxigp5_rresp),
.SAXIGP5RLAST (saxigp5_rlast),
.SAXIGP5RVALID (saxigp5_rvalid),
.SAXIGP5RREADY (saxigp5_rready),
.SAXIGP5AWQOS (saxigp5_awqos),
.SAXIGP5ARQOS (saxigp5_arqos),
.SAXIGP5RCOUNT (saxigp5_rcount),
.SAXIGP5WCOUNT (saxigp5_wcount),
.SAXIGP5RACOUNT (saxigp5_racount),
.SAXIGP5WACOUNT (saxigp5_wacount),
.SAXIGP6RCLK (saxi_lpd_rclk_temp),
.SAXIGP6WCLK (saxi_lpd_wclk_temp),
.SAXIGP6ARUSER (saxigp6_aruser),
.SAXIGP6AWUSER (saxigp6_awuser),
.SAXIGP6AWID (saxigp6_awid),
.SAXIGP6AWADDR (saxigp6_awaddr),
.SAXIGP6AWLEN (saxigp6_awlen),
.SAXIGP6AWSIZE (saxigp6_awsize),
.SAXIGP6AWBURST (saxigp6_awburst),
.SAXIGP6AWLOCK (saxigp6_awlock),
.SAXIGP6AWCACHE (saxigp6_awcache),
.SAXIGP6AWPROT (saxigp6_awprot),
.SAXIGP6AWVALID (saxigp6_awvalid),
.SAXIGP6AWREADY (saxigp6_awready),
.SAXIGP6WDATA (saxigp6_wdata_i),
.SAXIGP6WSTRB (saxigp6_wstrb_i),
.SAXIGP6WLAST (saxigp6_wlast),
.SAXIGP6WVALID (saxigp6_wvalid),
.SAXIGP6WREADY (saxigp6_wready),
.SAXIGP6BID (saxigp6_bid),
.SAXIGP6BRESP (saxigp6_bresp),
.SAXIGP6BVALID (saxigp6_bvalid),
.SAXIGP6BREADY (saxigp6_bready),
.SAXIGP6ARID (saxigp6_arid),
.SAXIGP6ARADDR (saxigp6_araddr),
.SAXIGP6ARLEN (saxigp6_arlen),
.SAXIGP6ARSIZE (saxigp6_arsize),
.SAXIGP6ARBURST (saxigp6_arburst),
.SAXIGP6ARLOCK (saxigp6_arlock),
.SAXIGP6ARCACHE (saxigp6_arcache),
.SAXIGP6ARPROT (saxigp6_arprot),
.SAXIGP6ARVALID (saxigp6_arvalid),
.SAXIGP6ARREADY (saxigp6_arready),
.SAXIGP6RID (saxigp6_rid),
.SAXIGP6RDATA (saxigp6_rdata_i),
.SAXIGP6RRESP (saxigp6_rresp),
.SAXIGP6RLAST (saxigp6_rlast),
.SAXIGP6RVALID (saxigp6_rvalid),
.SAXIGP6RREADY (saxigp6_rready),
.SAXIGP6AWQOS (saxigp6_awqos),
.SAXIGP6ARQOS (saxigp6_arqos),
.SAXIGP6RCOUNT (saxigp6_rcount),
.SAXIGP6WCOUNT (saxigp6_wcount),
.SAXIGP6RACOUNT (saxigp6_racount),
.SAXIGP6WACOUNT (saxigp6_wacount),
.SAXIACPACLK (saxiacp_fpd_aclk),
.SAXIACPAWADDR (saxiacp_awaddr),
.SAXIACPAWID (saxiacp_awid),
.SAXIACPAWLEN (saxiacp_awlen),
.SAXIACPAWSIZE (saxiacp_awsize),
.SAXIACPAWBURST (saxiacp_awburst),
.SAXIACPAWLOCK (saxiacp_awlock),
.SAXIACPAWCACHE (saxiacp_awcache),
.SAXIACPAWPROT (saxiacp_awprot),
.SAXIACPAWVALID (saxiacp_awvalid),
.SAXIACPAWREADY (saxiacp_awready),
.SAXIACPAWUSER (saxiacp_awuser),
.SAXIACPAWQOS (saxiacp_awqos),
.SAXIACPWLAST (saxiacp_wlast),
.SAXIACPWDATA (saxiacp_wdata),
.SAXIACPWSTRB (saxiacp_wstrb),
.SAXIACPWVALID (saxiacp_wvalid),
.SAXIACPWREADY (saxiacp_wready),
.SAXIACPBRESP (saxiacp_bresp),
.SAXIACPBID (saxiacp_bid),
.SAXIACPBVALID (saxiacp_bvalid),
.SAXIACPBREADY (saxiacp_bready),
.SAXIACPARADDR (saxiacp_araddr),
.SAXIACPARID (saxiacp_arid),
.SAXIACPARLEN (saxiacp_arlen),
.SAXIACPARSIZE (saxiacp_arsize),
.SAXIACPARBURST (saxiacp_arburst),
.SAXIACPARLOCK (saxiacp_arlock),
.SAXIACPARCACHE (saxiacp_arcache),
.SAXIACPARPROT (saxiacp_arprot),
.SAXIACPARVALID (saxiacp_arvalid),
.SAXIACPARREADY (saxiacp_arready),
.SAXIACPARUSER (saxiacp_aruser),
.SAXIACPARQOS (saxiacp_arqos),
.SAXIACPRID (saxiacp_rid),
.SAXIACPRLAST (saxiacp_rlast),
.SAXIACPRDATA (saxiacp_rdata),
.SAXIACPRRESP (saxiacp_rresp),
.SAXIACPRVALID (saxiacp_rvalid),
.SAXIACPRREADY (saxiacp_rready),
.PLACECLK (sacefpd_aclk),
.SACEFPDAWVALID (sacefpd_awvalid),
.SACEFPDAWREADY (sacefpd_awready),
.SACEFPDAWID (sacefpd_awid),
.SACEFPDAWADDR (sacefpd_awaddr),
.SACEFPDAWREGION (sacefpd_awregion),
.SACEFPDAWLEN (sacefpd_awlen),
.SACEFPDAWSIZE (sacefpd_awsize),
.SACEFPDAWBURST (sacefpd_awburst),
.SACEFPDAWLOCK (sacefpd_awlock),
.SACEFPDAWCACHE (sacefpd_awcache),
.SACEFPDAWPROT (sacefpd_awprot),
.SACEFPDAWDOMAIN (sacefpd_awdomain),
.SACEFPDAWSNOOP (sacefpd_awsnoop),
.SACEFPDAWBAR (sacefpd_awbar),
.SACEFPDAWQOS (sacefpd_awqos),
.SACEFPDAWUSER ({6'b000000,4'b1111,sacefpd_awuser[5:0]}),
.SACEFPDWVALID (sacefpd_wvalid),
.SACEFPDWREADY (sacefpd_wready),
.SACEFPDWDATA (sacefpd_wdata),
.SACEFPDWSTRB (sacefpd_wstrb),
.SACEFPDWLAST (sacefpd_wlast),
.SACEFPDWUSER (sacefpd_wuser),
.SACEFPDBVALID (sacefpd_bvalid),
.SACEFPDBREADY (sacefpd_bready),
.SACEFPDBID (sacefpd_bid),
.SACEFPDBRESP (sacefpd_bresp),
.SACEFPDBUSER (sacefpd_buser),
.SACEFPDARVALID (sacefpd_arvalid),
.SACEFPDARREADY (sacefpd_arready),
.SACEFPDARID (sacefpd_arid),
.SACEFPDARADDR (sacefpd_araddr),
.SACEFPDARREGION (sacefpd_arregion),
.SACEFPDARLEN (sacefpd_arlen),
.SACEFPDARSIZE (sacefpd_arsize),
.SACEFPDARBURST (sacefpd_arburst),
.SACEFPDARLOCK (sacefpd_arlock),
.SACEFPDARCACHE (sacefpd_arcache),
.SACEFPDARPROT (sacefpd_arprot),
.SACEFPDARDOMAIN (sacefpd_ardomain),
.SACEFPDARSNOOP (sacefpd_arsnoop),
.SACEFPDARBAR (sacefpd_arbar),
.SACEFPDARQOS (sacefpd_arqos),
.SACEFPDARUSER ({6'b000000,4'b1111,sacefpd_aruser[5:0]}),
.SACEFPDRVALID (sacefpd_rvalid),
.SACEFPDRREADY (sacefpd_rready),
.SACEFPDRID (sacefpd_rid),
.SACEFPDRDATA (sacefpd_rdata),
.SACEFPDRRESP (sacefpd_rresp),
.SACEFPDRLAST (sacefpd_rlast),
.SACEFPDRUSER (sacefpd_ruser),
.SACEFPDACVALID (sacefpd_acvalid),
.SACEFPDACREADY (sacefpd_acready),
.SACEFPDACADDR (sacefpd_acaddr),
.SACEFPDACSNOOP (sacefpd_acsnoop),
.SACEFPDACPROT (sacefpd_acprot),
.SACEFPDCRVALID (sacefpd_crvalid),
.SACEFPDCRREADY (sacefpd_crready),
.SACEFPDCRRESP (sacefpd_crresp),
.SACEFPDCDVALID (sacefpd_cdvalid),
.SACEFPDCDREADY (sacefpd_cdready),
.SACEFPDCDDATA (sacefpd_cddata),
.SACEFPDCDLAST (sacefpd_cdlast),
.SACEFPDWACK (sacefpd_wack),
.SACEFPDRACK (sacefpd_rack),
.EMIOCAN0PHYTX (emio_can0_phy_tx),
.EMIOCAN0PHYRX (emio_can0_phy_rx),
.EMIOCAN1PHYTX (emio_can1_phy_tx),
.EMIOCAN1PHYRX (emio_can1_phy_rx),
.EMIOENET0GMIIRXCLK (emio_enet0_gmii_rx_clk),
.EMIOENET0SPEEDMODE (emio_enet0_speed_mode),
.EMIOENET0GMIICRS (emio_enet0_gmii_crs),
.EMIOENET0GMIICOL (emio_enet0_gmii_col),
.EMIOENET0GMIIRXD (emio_enet0_gmii_rxd),
.EMIOENET0GMIIRXER (emio_enet0_gmii_rx_er),
.EMIOENET0GMIIRXDV (emio_enet0_gmii_rx_dv),
.EMIOENET0GMIITXCLK (emio_enet0_gmii_tx_clk),
.EMIOENET0GMIITXD (emio_enet0_gmii_txd),
.EMIOENET0GMIITXEN (emio_enet0_gmii_tx_en),
.EMIOENET0GMIITXER (emio_enet0_gmii_tx_er),
.EMIOENET0MDIOMDC (emio_enet0_mdio_mdc),
.EMIOENET0MDIOI (emio_enet0_mdio_i),
.EMIOENET0MDIOO (emio_enet0_mdio_o),
.EMIOENET0MDIOTN (emio_enet0_mdio_tri),
.EMIOENET1GMIIRXCLK (emio_enet1_gmii_rx_clk),
.EMIOENET1SPEEDMODE (emio_enet1_speed_mode),
.EMIOENET1GMIICRS (emio_enet1_gmii_crs),
.EMIOENET1GMIICOL (emio_enet1_gmii_col),
.EMIOENET1GMIIRXD (emio_enet1_gmii_rxd),
.EMIOENET1GMIIRXER (emio_enet1_gmii_rx_er),
.EMIOENET1GMIIRXDV (emio_enet1_gmii_rx_dv),
.EMIOENET1GMIITXCLK (emio_enet1_gmii_tx_clk),
.EMIOENET1GMIITXD (emio_enet1_gmii_txd),
.EMIOENET1GMIITXEN (emio_enet1_gmii_tx_en),
.EMIOENET1GMIITXER (emio_enet1_gmii_tx_er),
.EMIOENET1MDIOMDC (emio_enet1_mdio_mdc),
.EMIOENET1MDIOI (emio_enet1_mdio_i),
.EMIOENET1MDIOO (emio_enet1_mdio_o),
.EMIOENET1MDIOTN (emio_enet1_mdio_tri),
.EMIOENET2GMIIRXCLK (emio_enet2_gmii_rx_clk),
.EMIOENET2SPEEDMODE (emio_enet2_speed_mode),
.EMIOENET2GMIICRS (emio_enet2_gmii_crs),
.EMIOENET2GMIICOL (emio_enet2_gmii_col),
.EMIOENET2GMIIRXD (emio_enet2_gmii_rxd),
.EMIOENET2GMIIRXER (emio_enet2_gmii_rx_er),
.EMIOENET2GMIIRXDV (emio_enet2_gmii_rx_dv),
.EMIOENET2GMIITXCLK (emio_enet2_gmii_tx_clk),
.EMIOENET2GMIITXD (emio_enet2_gmii_txd),
.EMIOENET2GMIITXEN (emio_enet2_gmii_tx_en),
.EMIOENET2GMIITXER (emio_enet2_gmii_tx_er),
.EMIOENET2MDIOMDC (emio_enet2_mdio_mdc),
.EMIOENET2MDIOI (emio_enet2_mdio_i),
.EMIOENET2MDIOO (emio_enet2_mdio_o),
.EMIOENET2MDIOTN (emio_enet2_mdio_tri),
.EMIOENET3GMIIRXCLK (emio_enet3_gmii_rx_clk),
.EMIOENET3SPEEDMODE (emio_enet3_speed_mode),
.EMIOENET3GMIICRS (emio_enet3_gmii_crs),
.EMIOENET3GMIICOL (emio_enet3_gmii_col),
.EMIOENET3GMIIRXD (emio_enet3_gmii_rxd),
.EMIOENET3GMIIRXER (emio_enet3_gmii_rx_er),
.EMIOENET3GMIIRXDV (emio_enet3_gmii_rx_dv),
.EMIOENET3GMIITXCLK (emio_enet3_gmii_tx_clk),
.EMIOENET3GMIITXD (emio_enet3_gmii_txd),
.EMIOENET3GMIITXEN (emio_enet3_gmii_tx_en),
.EMIOENET3GMIITXER (emio_enet3_gmii_tx_er),
.EMIOENET3MDIOMDC (emio_enet3_mdio_mdc),
.EMIOENET3MDIOI (emio_enet3_mdio_i),
.EMIOENET3MDIOO (emio_enet3_mdio_o),
.EMIOENET3MDIOTN (emio_enet3_mdio_tri),
.EMIOENET0TXRDATARDY (emio_enet0_tx_r_data_rdy),
.EMIOENET0TXRRD (emio_enet0_tx_r_rd),
.EMIOENET0TXRVALID (emio_enet0_tx_r_valid),
.EMIOENET0TXRDATA (emio_enet0_tx_r_data),
.EMIOENET0TXRSOP (emio_enet0_tx_r_sop),
.EMIOENET0TXREOP (emio_enet0_tx_r_eop),
.EMIOENET0TXRERR (emio_enet0_tx_r_err),
.EMIOENET0TXRUNDERFLOW (emio_enet0_tx_r_underflow),
.EMIOENET0TXRFLUSHED (emio_enet0_tx_r_flushed),
.EMIOENET0TXRCONTROL (emio_enet0_tx_r_control),
.EMIOENET0DMATXENDTOG (emio_enet0_dma_tx_end_tog),
.EMIOENET0DMATXSTATUSTOG (emio_enet0_dma_tx_status_tog),
.EMIOENET0TXRSTATUS (emio_enet0_tx_r_status),
.EMIOENET0RXWWR (emio_enet0_rx_w_wr),
.EMIOENET0RXWDATA (emio_enet0_rx_w_data),
.EMIOENET0RXWSOP (emio_enet0_rx_w_sop),
.EMIOENET0RXWEOP (emio_enet0_rx_w_eop),
.EMIOENET0RXWSTATUS (emio_enet0_rx_w_status),
.EMIOENET0RXWERR (emio_enet0_rx_w_err),
.EMIOENET0RXWOVERFLOW (emio_enet0_rx_w_overflow),
.FMIOGEM0SIGNALDETECT (emio_enet0_signal_detect),
.EMIOENET0RXWFLUSH (emio_enet0_rx_w_flush),
.EMIOGEM0TXRFIXEDLAT (emio_enet0_tx_r_fixed_lat),
.FMIOGEM0FIFOTXCLKFROMPL (fmio_gem0_fifo_tx_clk),
.FMIOGEM0FIFORXCLKFROMPL (fmio_gem0_fifo_rx_clk),
.FMIOGEM0FIFOTXCLKTOPLBUFG (fmio_gem0_fifo_tx_clk_temp),
.FMIOGEM0FIFORXCLKTOPLBUFG (fmio_gem0_fifo_rx_clk_temp),
.EMIOENET1TXRDATARDY (emio_enet1_tx_r_data_rdy),
.EMIOENET1TXRRD (emio_enet1_tx_r_rd),
.EMIOENET1TXRVALID (emio_enet1_tx_r_valid),
.EMIOENET1TXRDATA (emio_enet1_tx_r_data),
.EMIOENET1TXRSOP (emio_enet1_tx_r_sop),
.EMIOENET1TXREOP (emio_enet1_tx_r_eop),
.EMIOENET1TXRERR (emio_enet1_tx_r_err),
.EMIOENET1TXRUNDERFLOW (emio_enet1_tx_r_underflow),
.EMIOENET1TXRFLUSHED (emio_enet1_tx_r_flushed),
.EMIOENET1TXRCONTROL (emio_enet1_tx_r_control),
.EMIOENET1DMATXENDTOG (emio_enet1_dma_tx_end_tog),
.EMIOENET1DMATXSTATUSTOG (emio_enet1_dma_tx_status_tog),
.EMIOENET1TXRSTATUS (emio_enet1_tx_r_status),
.EMIOENET1RXWWR (emio_enet1_rx_w_wr),
.EMIOENET1RXWDATA (emio_enet1_rx_w_data),
.EMIOENET1RXWSOP (emio_enet1_rx_w_sop),
.EMIOENET1RXWEOP (emio_enet1_rx_w_eop),
.EMIOENET1RXWSTATUS (emio_enet1_rx_w_status),
.EMIOENET1RXWERR (emio_enet1_rx_w_err),
.EMIOENET1RXWOVERFLOW (emio_enet1_rx_w_overflow),
.FMIOGEM1SIGNALDETECT (emio_enet1_signal_detect),
.EMIOENET1RXWFLUSH (emio_enet1_rx_w_flush),
.EMIOGEM1TXRFIXEDLAT (emio_enet1_tx_r_fixed_lat),
.FMIOGEM1FIFOTXCLKFROMPL (fmio_gem1_fifo_tx_clk),
.FMIOGEM1FIFORXCLKFROMPL (fmio_gem1_fifo_rx_clk),
.FMIOGEM1FIFOTXCLKTOPLBUFG (fmio_gem1_fifo_tx_clk_temp),
.FMIOGEM1FIFORXCLKTOPLBUFG (fmio_gem1_fifo_rx_clk_temp),
.EMIOENET2TXRDATARDY (emio_enet2_tx_r_data_rdy),
.EMIOENET2TXRRD (emio_enet2_tx_r_rd),
.EMIOENET2TXRVALID (emio_enet2_tx_r_valid),
.EMIOENET2TXRDATA (emio_enet2_tx_r_data),
.EMIOENET2TXRSOP (emio_enet2_tx_r_sop),
.EMIOENET2TXREOP (emio_enet2_tx_r_eop),
.EMIOENET2TXRERR (emio_enet2_tx_r_err),
.EMIOENET2TXRUNDERFLOW (emio_enet2_tx_r_underflow),
.EMIOENET2TXRFLUSHED (emio_enet2_tx_r_flushed),
.EMIOENET2TXRCONTROL (emio_enet2_tx_r_control),
.EMIOENET2DMATXENDTOG (emio_enet2_dma_tx_end_tog),
.EMIOENET2DMATXSTATUSTOG (emio_enet2_dma_tx_status_tog),
.EMIOENET2TXRSTATUS (emio_enet2_tx_r_status),
.EMIOENET2RXWWR (emio_enet2_rx_w_wr),
.EMIOENET2RXWDATA (emio_enet2_rx_w_data),
.EMIOENET2RXWSOP (emio_enet2_rx_w_sop),
.EMIOENET2RXWEOP (emio_enet2_rx_w_eop),
.EMIOENET2RXWSTATUS (emio_enet2_rx_w_status),
.EMIOENET2RXWERR (emio_enet2_rx_w_err),
.EMIOENET2RXWOVERFLOW (emio_enet2_rx_w_overflow),
.FMIOGEM2SIGNALDETECT (emio_enet2_signal_detect),
.EMIOENET2RXWFLUSH (emio_enet2_rx_w_flush),
.EMIOGEM2TXRFIXEDLAT (emio_enet2_tx_r_fixed_lat),
.FMIOGEM2FIFOTXCLKFROMPL (fmio_gem2_fifo_tx_clk),
.FMIOGEM2FIFORXCLKFROMPL (fmio_gem2_fifo_rx_clk),
.FMIOGEM2FIFOTXCLKTOPLBUFG (fmio_gem2_fifo_tx_clk_temp),
.FMIOGEM2FIFORXCLKTOPLBUFG (fmio_gem2_fifo_rx_clk_temp),
.EMIOENET3TXRDATARDY (emio_enet3_tx_r_data_rdy),
.EMIOENET3TXRRD (emio_enet3_tx_r_rd),
.EMIOENET3TXRVALID (emio_enet3_tx_r_valid),
.EMIOENET3TXRDATA (emio_enet3_tx_r_data),
.EMIOENET3TXRSOP (emio_enet3_tx_r_sop),
.EMIOENET3TXREOP (emio_enet3_tx_r_eop),
.EMIOENET3TXRERR (emio_enet3_tx_r_err),
.EMIOENET3TXRUNDERFLOW (emio_enet3_tx_r_underflow),
.EMIOENET3TXRFLUSHED (emio_enet3_tx_r_flushed),
.EMIOENET3TXRCONTROL (emio_enet3_tx_r_control),
.EMIOENET3DMATXENDTOG (emio_enet3_dma_tx_end_tog),
.EMIOENET3DMATXSTATUSTOG (emio_enet3_dma_tx_status_tog),
.EMIOENET3TXRSTATUS (emio_enet3_tx_r_status),
.EMIOENET3RXWWR (emio_enet3_rx_w_wr),
.EMIOENET3RXWDATA (emio_enet3_rx_w_data),
.EMIOENET3RXWSOP (emio_enet3_rx_w_sop),
.EMIOENET3RXWEOP (emio_enet3_rx_w_eop),
.EMIOENET3RXWSTATUS (emio_enet3_rx_w_status),
.EMIOENET3RXWERR (emio_enet3_rx_w_err),
.EMIOENET3RXWOVERFLOW (emio_enet3_rx_w_overflow),
.FMIOGEM3SIGNALDETECT (emio_enet3_signal_detect),
.EMIOENET3RXWFLUSH (emio_enet3_rx_w_flush),
.EMIOGEM3TXRFIXEDLAT (emio_enet3_tx_r_fixed_lat),
.FMIOGEM3FIFOTXCLKFROMPL (fmio_gem3_fifo_tx_clk),
.FMIOGEM3FIFORXCLKFROMPL (fmio_gem3_fifo_rx_clk),
.FMIOGEM3FIFOTXCLKTOPLBUFG (fmio_gem3_fifo_tx_clk_temp),
.FMIOGEM3FIFORXCLKTOPLBUFG (fmio_gem3_fifo_rx_clk_temp),
.EMIOGEM0TXSOF (emio_enet0_tx_sof),
.EMIOGEM0SYNCFRAMETX (emio_enet0_sync_frame_tx),
.EMIOGEM0DELAYREQTX (emio_enet0_delay_req_tx),
.EMIOGEM0PDELAYREQTX (emio_enet0_pdelay_req_tx),
.EMIOGEM0PDELAYRESPTX (emio_enet0_pdelay_resp_tx),
.EMIOGEM0RXSOF (emio_enet0_rx_sof),
.EMIOGEM0SYNCFRAMERX (emio_enet0_sync_frame_rx),
.EMIOGEM0DELAYREQRX (emio_enet0_delay_req_rx),
.EMIOGEM0PDELAYREQRX (emio_enet0_pdelay_req_rx),
.EMIOGEM0PDELAYRESPRX (emio_enet0_pdelay_resp_rx),
.EMIOGEM0TSUINCCTRL (emio_enet0_tsu_inc_ctrl),
.EMIOGEM0TSUTIMERCMPVAL (emio_enet0_tsu_timer_cmp_val),
.EMIOGEM1TXSOF (emio_enet1_tx_sof),
.EMIOGEM1SYNCFRAMETX (emio_enet1_sync_frame_tx),
.EMIOGEM1DELAYREQTX (emio_enet1_delay_req_tx),
.EMIOGEM1PDELAYREQTX (emio_enet1_pdelay_req_tx),
.EMIOGEM1PDELAYRESPTX (emio_enet1_pdelay_resp_tx),
.EMIOGEM1RXSOF (emio_enet1_rx_sof),
.EMIOGEM1SYNCFRAMERX (emio_enet1_sync_frame_rx),
.EMIOGEM1DELAYREQRX (emio_enet1_delay_req_rx),
.EMIOGEM1PDELAYREQRX (emio_enet1_pdelay_req_rx),
.EMIOGEM1PDELAYRESPRX (emio_enet1_pdelay_resp_rx),
.EMIOGEM1TSUINCCTRL (emio_enet1_tsu_inc_ctrl),
.EMIOGEM1TSUTIMERCMPVAL (emio_enet1_tsu_timer_cmp_val),
.EMIOGEM2TXSOF (emio_enet2_tx_sof),
.EMIOGEM2SYNCFRAMETX (emio_enet2_sync_frame_tx),
.EMIOGEM2DELAYREQTX (emio_enet2_delay_req_tx),
.EMIOGEM2PDELAYREQTX (emio_enet2_pdelay_req_tx),
.EMIOGEM2PDELAYRESPTX (emio_enet2_pdelay_resp_tx),
.EMIOGEM2RXSOF (emio_enet2_rx_sof),
.EMIOGEM2SYNCFRAMERX (emio_enet2_sync_frame_rx),
.EMIOGEM2DELAYREQRX (emio_enet2_delay_req_rx),
.EMIOGEM2PDELAYREQRX (emio_enet2_pdelay_req_rx),
.EMIOGEM2PDELAYRESPRX (emio_enet2_pdelay_resp_rx),
.EMIOGEM2TSUINCCTRL (emio_enet2_tsu_inc_ctrl),
.EMIOGEM2TSUTIMERCMPVAL (emio_enet2_tsu_timer_cmp_val),
.EMIOGEM3TXSOF (emio_enet3_tx_sof),
.EMIOGEM3SYNCFRAMETX (emio_enet3_sync_frame_tx),
.EMIOGEM3DELAYREQTX (emio_enet3_delay_req_tx),
.EMIOGEM3PDELAYREQTX (emio_enet3_pdelay_req_tx),
.EMIOGEM3PDELAYRESPTX (emio_enet3_pdelay_resp_tx),
.EMIOGEM3RXSOF (emio_enet3_rx_sof),
.EMIOGEM3SYNCFRAMERX (emio_enet3_sync_frame_rx),
.EMIOGEM3DELAYREQRX (emio_enet3_delay_req_rx),
.EMIOGEM3PDELAYREQRX (emio_enet3_pdelay_req_rx),
.EMIOGEM3PDELAYRESPRX (emio_enet3_pdelay_resp_rx),
.EMIOGEM3TSUINCCTRL (emio_enet3_tsu_inc_ctrl),
.EMIOGEM3TSUTIMERCMPVAL (emio_enet3_tsu_timer_cmp_val),
.FMIOGEMTSUCLKFROMPL (fmio_gem_tsu_clk_from_pl),
.FMIOGEMTSUCLKTOPLBUFG (fmio_gem_tsu_clk_to_pl_bufg),
.EMIOENETTSUCLK (emio_enet_tsu_clk),
.EMIOENET0GEMTSUTIMERCNT (emio_enet0_enet_tsu_timer_cnt),
.EMIOENET0EXTINTIN (emio_enet0_ext_int_in),
.EMIOENET1EXTINTIN (emio_enet1_ext_int_in),
.EMIOENET2EXTINTIN (emio_enet2_ext_int_in),
.EMIOENET3EXTINTIN (emio_enet3_ext_int_in),
.EMIOENET0DMABUSWIDTH (emio_enet0_dma_bus_width),
.EMIOENET1DMABUSWIDTH (emio_enet1_dma_bus_width),
.EMIOENET2DMABUSWIDTH (emio_enet2_dma_bus_width),
.EMIOENET3DMABUSWIDTH (emio_enet3_dma_bus_width),
.EMIOGPIOI (emio_gpio_i_temp),
.EMIOGPIOO (emio_gpio_o_temp),
.EMIOGPIOTN (emio_gpio_t_temp),
.EMIOI2C0SCLI (emio_i2c0_scl_i),
.EMIOI2C0SCLO (emio_i2c0_scl_o),
.EMIOI2C0SCLTN (emio_i2c0_scl_tri),
.EMIOI2C0SDAI (emio_i2c0_sda_i),
.EMIOI2C0SDAO (emio_i2c0_sda_o),
.EMIOI2C0SDATN (emio_i2c0_sda_tri),
.EMIOI2C1SCLI (emio_i2c1_scl_i),
.EMIOI2C1SCLO (emio_i2c1_scl_o),
.EMIOI2C1SCLTN (emio_i2c1_scl_tri),
.EMIOI2C1SDAI (emio_i2c1_sda_i),
.EMIOI2C1SDAO (emio_i2c1_sda_o),
.EMIOI2C1SDATN (emio_i2c1_sda_tri),
.EMIOUART0TX (emio_uart0_txd),
.EMIOUART0RX (emio_uart0_rxd),
.EMIOUART0CTSN (emio_uart0_ctsn),
.EMIOUART0RTSN (emio_uart0_rtsn),
.EMIOUART0DSRN (emio_uart0_dsrn),
.EMIOUART0DCDN (emio_uart0_dcdn),
.EMIOUART0RIN (emio_uart0_rin),
.EMIOUART0DTRN (emio_uart0_dtrn),
.EMIOUART1TX (emio_uart1_txd),
.EMIOUART1RX (emio_uart1_rxd),
.EMIOUART1CTSN (emio_uart1_ctsn),
.EMIOUART1RTSN (emio_uart1_rtsn),
.EMIOUART1DSRN (emio_uart1_dsrn),
.EMIOUART1DCDN (emio_uart1_dcdn),
.EMIOUART1RIN (emio_uart1_rin),
.EMIOUART1DTRN (emio_uart1_dtrn),
.EMIOSDIO0CLKOUT (emio_sdio0_clkout),
.EMIOSDIO0FBCLKIN (emio_sdio0_fb_clk_in),
.EMIOSDIO0CMDOUT (emio_sdio0_cmdout),
.EMIOSDIO0CMDIN (emio_sdio0_cmdin),
.EMIOSDIO0CMDENA (emio_sdio0_cmdena_i),
.EMIOSDIO0DATAIN (emio_sdio0_datain),
.EMIOSDIO0DATAOUT (emio_sdio0_dataout),
.EMIOSDIO0DATAENA (emio_sdio0_dataena_i),
.EMIOSDIO0CDN (emio_sdio0_cd_n),
.EMIOSDIO0WP (emio_sdio0_wp),
.EMIOSDIO0LEDCONTROL (emio_sdio0_ledcontrol),
.EMIOSDIO0BUSPOWER (emio_sdio0_buspower),
.EMIOSDIO0BUSVOLT (emio_sdio0_bus_volt),
.EMIOSDIO1CLKOUT (emio_sdio1_clkout),
.EMIOSDIO1FBCLKIN (emio_sdio1_fb_clk_in),
.EMIOSDIO1CMDOUT (emio_sdio1_cmdout),
.EMIOSDIO1CMDIN (emio_sdio1_cmdin),
.EMIOSDIO1CMDENA (emio_sdio1_cmdena_i),
.EMIOSDIO1DATAIN (emio_sdio1_datain),
.EMIOSDIO1DATAOUT (emio_sdio1_dataout),
.EMIOSDIO1DATAENA (emio_sdio1_dataena_i),
.EMIOSDIO1CDN (emio_sdio1_cd_n),
.EMIOSDIO1WP (emio_sdio1_wp),
.EMIOSDIO1LEDCONTROL (emio_sdio1_ledcontrol),
.EMIOSDIO1BUSPOWER (emio_sdio1_buspower),
.EMIOSDIO1BUSVOLT (emio_sdio1_bus_volt),
.EMIOSPI0SCLKI (emio_spi0_sclk_i),
.EMIOSPI0SCLKO (emio_spi0_sclk_o),
.EMIOSPI0SCLKTN (emio_spi0_sclk_tri),
.EMIOSPI0MI (emio_spi0_m_i),
.EMIOSPI0MO (emio_spi0_m_o),
.EMIOSPI0MOTN (emio_spi0_mo_tri),
.EMIOSPI0SI (emio_spi0_s_i),
.EMIOSPI0SO (emio_spi0_s_o),
.EMIOSPI0STN (emio_spi0_so_tri),
.EMIOSPI0SSIN (emio_spi0_ss_i_n),
.EMIOSPI0SSON ({emio_spi0_ss2_o_n,emio_spi0_ss1_o_n,emio_spi0_ss_o_n}),
.EMIOSPI0SSNTN (emio_spi0_ss_n_tri),
.EMIOSPI1SCLKI (emio_spi1_sclk_i),
.EMIOSPI1SCLKO (emio_spi1_sclk_o),
.EMIOSPI1SCLKTN (emio_spi1_sclk_tri),
.EMIOSPI1MI (emio_spi1_m_i),
.EMIOSPI1MO (emio_spi1_m_o),
.EMIOSPI1MOTN (emio_spi1_mo_tri),
.EMIOSPI1SI (emio_spi1_s_i),
.EMIOSPI1SO (emio_spi1_s_o),
.EMIOSPI1STN (emio_spi1_so_tri),
.EMIOSPI1SSIN (emio_spi1_ss_i_n),
.EMIOSPI1SSON ({emio_spi1_ss2_o_n,emio_spi1_ss1_o_n,emio_spi1_ss_o_n}),
.EMIOSPI1SSNTN (emio_spi1_ss_n_tri),
.PLPSTRACECLK (pl_ps_trace_clk),
.PSPLTRACECTL (trace_ctl_i),
.PSPLTRACEDATA (trace_data_i),
.EMIOTTC0WAVEO (emio_ttc0_wave_o),
.EMIOTTC0CLKI (emio_ttc0_clk_i),
.EMIOTTC1WAVEO (emio_ttc1_wave_o),
.EMIOTTC1CLKI (emio_ttc1_clk_i),
.EMIOTTC2WAVEO (emio_ttc2_wave_o),
.EMIOTTC2CLKI (emio_ttc2_clk_i),
.EMIOTTC3WAVEO (emio_ttc3_wave_o),
.EMIOTTC3CLKI (emio_ttc3_clk_i),
.EMIOWDT0CLKI (emio_wdt0_clk_i),
.EMIOWDT0RSTO (emio_wdt0_rst_o),
.EMIOWDT1CLKI (emio_wdt1_clk_i),
.EMIOWDT1RSTO (emio_wdt1_rst_o),
.EMIOHUBPORTOVERCRNTUSB30 (emio_hub_port_overcrnt_usb3_0),
.EMIOHUBPORTOVERCRNTUSB31 (emio_hub_port_overcrnt_usb3_1),
.EMIOHUBPORTOVERCRNTUSB20 (emio_hub_port_overcrnt_usb2_0),
.EMIOHUBPORTOVERCRNTUSB21 (emio_hub_port_overcrnt_usb2_1),
.EMIOU2DSPORTVBUSCTRLUSB30 (emio_u2dsport_vbus_ctrl_usb3_0),
.EMIOU2DSPORTVBUSCTRLUSB31 (emio_u2dsport_vbus_ctrl_usb3_1),
.EMIOU3DSPORTVBUSCTRLUSB30 (emio_u3dsport_vbus_ctrl_usb3_0),
.EMIOU3DSPORTVBUSCTRLUSB31 (emio_u3dsport_vbus_ctrl_usb3_1),
.ADMAFCICLK (adma_fci_clk),
.PL2ADMACVLD (pl2adma_cvld),
.PL2ADMATACK (pl2adma_tack),
.ADMA2PLCACK (adma2pl_cack),
.ADMA2PLTVLD (adma2pl_tvld),
.GDMAFCICLK (perif_gdma_clk),
.PL2GDMACVLD (perif_gdma_cvld),
.PL2GDMATACK (perif_gdma_tack),
.GDMA2PLCACK (gdma_perif_cack),
.GDMA2PLTVLD (gdma_perif_tvld),
.PLFPGASTOP (pl_clock_stop),
.PLLAUXREFCLKLPD (pll_aux_refclk_lpd),
.PLLAUXREFCLKFPD (pll_aux_refclk_fpd),
.DPSAXISAUDIOTDATA (dp_s_axis_audio_tdata),
.DPSAXISAUDIOTID (dp_s_axis_audio_tid),
.DPSAXISAUDIOTVALID (dp_s_axis_audio_tvalid),
.DPSAXISAUDIOTREADY (dp_s_axis_audio_tready),
.DPMAXISMIXEDAUDIOTDATA (dp_m_axis_mixed_audio_tdata),
.DPMAXISMIXEDAUDIOTID (dp_m_axis_mixed_audio_tid),
.DPMAXISMIXEDAUDIOTVALID (dp_m_axis_mixed_audio_tvalid),
.DPMAXISMIXEDAUDIOTREADY (dp_m_axis_mixed_audio_tready),
.DPSAXISAUDIOCLK (dp_s_axis_audio_clk),
.DPLIVEVIDEOINVSYNC (dp_live_video_in_vsync),
.DPLIVEVIDEOINHSYNC (dp_live_video_in_hsync),
.DPLIVEVIDEOINDE (dp_live_video_in_de),
.DPLIVEVIDEOINPIXEL1 (dp_live_video_in_pixel1),
.DPVIDEOINCLK (dp_video_in_clk),
.DPVIDEOOUTHSYNC (dp_video_out_hsync),
.DPVIDEOOUTVSYNC (dp_video_out_vsync),
.DPVIDEOOUTPIXEL1 (dp_video_out_pixel1),
.DPAUXDATAIN (dp_aux_data_in),
.DPAUXDATAOUT (dp_aux_data_out),
.DPAUXDATAOEN (dp_aux_data_oe_n),
.DPLIVEGFXALPHAIN (dp_live_gfx_alpha_in),
.DPLIVEGFXPIXEL1IN (dp_live_gfx_pixel1_in),
.DPHOTPLUGDETECT (dp_hot_plug_detect),
.DPEXTERNALCUSTOMEVENT1 (dp_external_custom_event1),
.DPEXTERNALCUSTOMEVENT2 (dp_external_custom_event2),
.DPEXTERNALVSYNCEVENT (dp_external_vsync_event),
.DPLIVEVIDEODEOUT (dp_live_video_de_out),
.PLPSEVENTI (pl_ps_eventi),
.PSPLEVENTO (ps_pl_evento),
.PSPLSTANDBYWFE (ps_pl_standbywfe),
.PSPLSTANDBYWFI (ps_pl_standbywfi),
.PLPSAPUGICIRQ (pl_ps_apugic_irq),
.PLPSAPUGICFIQ (pl_ps_apugic_fiq),
.RPUEVENTI0 (rpu_eventi0),
.RPUEVENTI1 (rpu_eventi1),
.RPUEVENTO0 (rpu_evento0),
.RPUEVENTO1 (rpu_evento1),
.NFIQ0LPDRPU (nfiq0_lpd_rpu),
.NFIQ1LPDRPU (nfiq1_lpd_rpu),
.NIRQ0LPDRPU (nirq0_lpd_rpu),
.NIRQ1LPDRPU (nirq1_lpd_rpu),
.STMEVENT (stm_event),
.PLPSTRIGACK ({pl_ps_trigack_3, pl_ps_trigack_2, pl_ps_trigack_1, pl_ps_trigack_0}),
.PLPSTRIGGER ({pl_ps_trigger_3, pl_ps_trigger_2, pl_ps_trigger_1, pl_ps_trigger_0}),
.PSPLTRIGACK ({ps_pl_trigack_3, ps_pl_trigack_2, ps_pl_trigack_1, ps_pl_trigack_0}),
.PSPLTRIGGER ({ps_pl_trigger_3, ps_pl_trigger_2, ps_pl_trigger_1, ps_pl_trigger_0}),
.FTMGPO (ftm_gpo),
.FTMGPI (ftm_gpi),
.PLPSIRQ0 (irq_f2p_0_i),
.PLPSIRQ1 (irq_f2p_1_i),
.PSPLIRQLPD ({ps_pl_irq_lpd_low[18:8], ps_pl_irq_xmpu_lpd, ps_pl_irq_efuse, ps_pl_irq_csu_dma, ps_pl_irq_csu, ps_pl_irq_adma_chan, ps_pl_irq_usb3_0_pmu_wakeup, ps_pl_irq_usb3_1_otg, ps_pl_irq_usb3_1_endpoint, ps_pl_irq_usb3_0_otg, ps_pl_irq_usb3_0_endpoint, ps_pl_irq_enet3_wake, ps_pl_irq_enet3, ps_pl_irq_enet2_wake, ps_pl_irq_enet2, ps_pl_irq_enet1_wake, ps_pl_irq_enet1, ps_pl_irq_enet0_wake, ps_pl_irq_enet0, ps_pl_irq_ams, ps_pl_irq_aib_axi, ps_pl_irq_atb_err_lpd, ps_pl_irq_csu_pmu_wdt, ps_pl_irq_lp_wdt, ps_pl_irq_sdio1_wake, ps_pl_irq_sdio0_wake, ps_pl_irq_sdio1, ps_pl_irq_sdio0, ps_pl_irq_ttc3_2, ps_pl_irq_ttc3_1, ps_pl_irq_ttc3_0, ps_pl_irq_ttc2_2, ps_pl_irq_ttc2_1, ps_pl_irq_ttc2_0, ps_pl_irq_ttc1_2, ps_pl_irq_ttc1_1, ps_pl_irq_ttc1_0, ps_pl_irq_ttc0_2, ps_pl_irq_ttc0_1, ps_pl_irq_ttc0_0, ps_pl_irq_ipi_channel0, ps_pl_irq_ipi_channel1, ps_pl_irq_ipi_channel2, ps_pl_irq_ipi_channel10, ps_pl_irq_ipi_channel9, ps_pl_irq_ipi_channel8, ps_pl_irq_ipi_channel7, ps_pl_irq_clkmon, ps_pl_irq_rtc_seconds, ps_pl_irq_rtc_alaram, ps_pl_irq_lpd_apm, ps_pl_irq_can1, ps_pl_irq_can0, ps_pl_irq_uart1, ps_pl_irq_uart0, ps_pl_irq_spi1, ps_pl_irq_spi0, ps_pl_irq_i2c1, ps_pl_irq_i2c0, ps_pl_irq_gpio, ps_pl_irq_qspi, ps_pl_irq_nand, ps_pl_irq_r5_core1_ecc_error, ps_pl_irq_r5_core0_ecc_error, ps_pl_irq_lpd_apb_intr, ps_pl_irq_ocm_error, ps_pl_irq_rpu_pm, ps_pl_irq_lpd_low[7:0]}),
.PSPLIRQFPD ({ps_pl_irq_fpd_low[19:12], ps_pl_irq_intf_fpd_smmu, ps_pl_irq_intf_ppd_cci, ps_pl_irq_apu_regs, ps_pl_irq_apu_exterr, ps_pl_irq_apu_l2err, ps_pl_irq_apu_comm, ps_pl_irq_apu_pmu, ps_pl_irq_apu_cti, ps_pl_irq_apu_cpumnt, ps_pl_irq_xmpu_fpd, ps_pl_irq_sata, ps_pl_irq_gpu, ps_pl_irq_gdma_chan, ps_pl_irq_apm_fpd, ps_pl_irq_dpdma, ps_pl_irq_fpd_atb_error, ps_pl_irq_fpd_apb_int, ps_pl_irq_dport, ps_pl_irq_pcie_msc, ps_pl_irq_pcie_dma, ps_pl_irq_pcie_legacy, ps_pl_irq_pcie_msi, ps_pl_irq_fp_wdt, ps_pl_irq_ddr_ss, ps_pl_irq_fpd_low[11:0]}),
.OSCRTCCLK (osc_rtc_clk),
.PLPMUGPI (pl_pmu_gpi),
.PMUPLGPO (pmu_pl_gpo),
.AIBPMUAFIFMFPDACK (aib_pmu_afifm_fpd_ack),
.AIBPMUAFIFMLPDACK (aib_pmu_afifm_lpd_ack),
.PMUAIBAFIFMFPDREQ (pmu_aib_afifm_fpd_req),
.PMUAIBAFIFMLPDREQ (pmu_aib_afifm_lpd_req),
.PMUERRORTOPL (pmu_error_to_pl),
.PMUERRORFROMPL (pmu_error_from_pl),
.DDRCEXTREFRESHRANK0REQ (ddrc_ext_refresh_rank0_req),
.DDRCEXTREFRESHRANK1REQ (ddrc_ext_refresh_rank1_req),
.DDRCREFRESHPLCLK (ddrc_refresh_pl_clk),
.PLACPINACT (pl_acpinact),
.PLCLK (pl_clk_unbuffered),
.TESTADCCLK (test_adc_clk),
.TESTADCIN (test_adc_in),
.TESTADC2IN (test_adc2_in),
.TESTDB (test_db),
.TESTADCOUT (test_adc_out),
.TESTAMSOSC (test_ams_osc),
.TESTMONDATA (test_mon_data),
.TESTDCLK (test_dclk),
.TESTDEN (test_den),
.TESTDWE (test_dwe),
.TESTDADDR (test_daddr),
.TESTDI (test_di),
.TESTDRDY (test_drdy),
.TESTDO (test_do),
.TESTCONVST (test_convst),
.PSTPPLCLK (pstp_pl_clk),
.PSTPPLIN (pstp_pl_in),
.PSTPPLOUT (pstp_pl_out),
.PSTPPLTS (pstp_pl_ts),
.FMIOTESTGEMSCANMUX1 (fmio_test_gem_scanmux_1),
.FMIOTESTGEMSCANMUX2 (fmio_test_gem_scanmux_2),
.TESTCHARMODEFPDN (test_char_mode_fpd_n),
.TESTCHARMODELPDN (test_char_mode_lpd_n),
.FMIOTESTIOCHARSCANCLOCK (fmio_test_io_char_scan_clock),
.FMIOTESTIOCHARSCANENABLE (fmio_test_io_char_scanenable),
.FMIOTESTIOCHARSCANIN (fmio_test_io_char_scan_in),
.FMIOTESTIOCHARSCANOUT (fmio_test_io_char_scan_out),
.FMIOTESTIOCHARSCANRESETN (fmio_test_io_char_scan_reset_n),
.FMIOCHARAFIFSLPDTESTSELECTN (fmio_char_afifslpd_test_select_n),
.FMIOCHARAFIFSLPDTESTINPUT (fmio_char_afifslpd_test_input),
.FMIOCHARAFIFSLPDTESTOUTPUT (fmio_char_afifslpd_test_output),
.FMIOCHARAFIFSFPDTESTSELECTN (fmio_char_afifsfpd_test_select_n),
.FMIOCHARAFIFSFPDTESTINPUT (fmio_char_afifsfpd_test_input),
.FMIOCHARAFIFSFPDTESTOUTPUT (fmio_char_afifsfpd_test_output),
.IOCHARAUDIOINTESTDATA (io_char_audio_in_test_data),
.IOCHARAUDIOMUXSELN (io_char_audio_mux_sel_n),
.IOCHARVIDEOINTESTDATA (io_char_video_in_test_data),
.IOCHARVIDEOMUXSELN (io_char_video_mux_sel_n),
.IOCHARVIDEOOUTTESTDATA (io_char_video_out_test_data),
.IOCHARAUDIOOUTTESTDATA (io_char_audio_out_test_data),
.FMIOTESTQSPISCANMUX1N (fmio_test_qspi_scanmux_1_n),
.FMIOTESTSDIOSCANMUX1 (fmio_test_sdio_scanmux_1),
.FMIOTESTSDIOSCANMUX2 (fmio_test_sdio_scanmux_2),
.FMIOSD0DLLTESTINN (fmio_sd0_dll_test_in_n),
.FMIOSD0DLLTESTOUT (fmio_sd0_dll_test_out),
.FMIOSD1DLLTESTINN (fmio_sd1_dll_test_in_n),
.FMIOSD1DLLTESTOUT (fmio_sd1_dll_test_out),
.TESTPLSCANCHOPPERSI (test_pl_scan_chopper_si),
.TESTPLSCANCHOPPERSO (test_pl_scan_chopper_so),
.TESTPLSCANCHOPPERTRIG (test_pl_scan_chopper_trig),
.TESTPLSCANCLK0 (test_pl_scan_clk0),
.TESTPLSCANCLK1 (test_pl_scan_clk1),
.TESTPLSCANEDTCLK (test_pl_scan_edt_clk),
.TESTPLSCANEDTINAPU (test_pl_scan_edt_in_apu),
.TESTPLSCANEDTINCPU (test_pl_scan_edt_in_cpu),
.TESTPLSCANEDTINDDR (test_pl_scan_edt_in_ddr),
.TESTPLSCANEDTINFP (test_pl_scan_edt_in_fp),
.TESTPLSCANEDTINGPU (test_pl_scan_edt_in_gpu),
.TESTPLSCANEDTINLP (test_pl_scan_edt_in_lp),
.TESTPLSCANEDTINUSB3 (test_pl_scan_edt_in_usb3),
.TESTPLSCANEDTOUTAPU (test_pl_scan_edt_out_apu),
.TESTPLSCANEDTOUTCPU0 (test_pl_scan_edt_out_cpu0),
.TESTPLSCANEDTOUTCPU1 (test_pl_scan_edt_out_cpu1),
.TESTPLSCANEDTOUTCPU2 (test_pl_scan_edt_out_cpu2),
.TESTPLSCANEDTOUTCPU3 (test_pl_scan_edt_out_cpu3),
.TESTPLSCANEDTOUTDDR (test_pl_scan_edt_out_ddr),
.TESTPLSCANEDTOUTFP (test_pl_scan_edt_out_fp),
.TESTPLSCANEDTOUTGPU (test_pl_scan_edt_out_gpu),
.TESTPLSCANEDTOUTLP (test_pl_scan_edt_out_lp),
.TESTPLSCANEDTOUTUSB3 (test_pl_scan_edt_out_usb3),
.TESTPLSCANEDTUPDATE (test_pl_scan_edt_update),
.TESTPLSCANRESETN (test_pl_scan_reset_n),
.TESTPLSCANENABLE (test_pl_scanenable),
.TESTPLSCANPLLRESET (test_pl_scan_pll_reset),
.TESTPLSCANSPAREIN0 (test_pl_scan_spare_in0),
.TESTPLSCANSPAREIN1 (test_pl_scan_spare_in1),
.TESTPLSCANSPAREOUT0 (test_pl_scan_spare_out0),
.TESTPLSCANSPAREOUT1 (test_pl_scan_spare_out1),
.TESTPLSCANWRAPCLK (test_pl_scan_wrap_clk),
.TESTPLSCANWRAPISHIFT (test_pl_scan_wrap_ishift),
.TESTPLSCANWRAPOSHIFT (test_pl_scan_wrap_oshift),
.TESTPLSCANSLCRCONFIGCLK (test_pl_scan_slcr_config_clk),
.TESTPLSCANSLCRCONFIGRSTN (test_pl_scan_slcr_config_rstn),
.TESTPLSCANSLCRCONFIGSI (test_pl_scan_slcr_config_si),
.TESTPLSCANSPAREIN2 (test_pl_scan_spare_in2),
.TESTPLSCANENABLESLCREN (test_pl_scanenable_slcr_en),
.TESTPLPLLLOCKOUT (test_pl_pll_lock_out),
.TESTPLSCANSLCRCONFIGSO (test_pl_scan_slcr_config_so),
.TSTRTCCALIBREGIN (tst_rtc_calibreg_in),
.TSTRTCCALIBREGOUT (tst_rtc_calibreg_out),
.TSTRTCCALIBREGWE (tst_rtc_calibreg_we),
.TSTRTCCLK (tst_rtc_clk),
.TSTRTCOSCCLKOUT (tst_rtc_osc_clk_out),
.TSTRTCSECCOUNTEROUT (tst_rtc_sec_counter_out),
.TSTRTCSECONDSRAWINT (tst_rtc_seconds_raw_int),
.TSTRTCTESTCLOCKSELECTN (tst_rtc_testclock_select_n),
.TSTRTCTICKCOUNTEROUT (tst_rtc_tick_counter_out),
.TSTRTCTIMESETREGIN (tst_rtc_timesetreg_in),
.TSTRTCTIMESETREGOUT (tst_rtc_timesetreg_out),
.TSTRTCDISABLEBATOP (tst_rtc_disable_bat_op),
.TSTRTCOSCCNTRLIN (tst_rtc_osc_cntrl_in),
.TSTRTCOSCCNTRLOUT (tst_rtc_osc_cntrl_out),
.TSTRTCOSCCNTRLWE (tst_rtc_osc_cntrl_we),
.TSTRTCSECRELOAD (tst_rtc_sec_reload),
.TSTRTCTIMESETREGWE (tst_rtc_timesetreg_we),
.TSTRTCTESTMODEN (tst_rtc_testmode_n),
.TESTUSB0FUNCMUX0N (test_usb0_funcmux_0_n),
.TESTUSB1FUNCMUX0N (test_usb1_funcmux_0_n),
.TESTUSB0SCANMUX0N (test_usb0_scanmux_0_n),
.TESTUSB1SCANMUX0N (test_usb1_scanmux_0_n),
.LPDPLLTESTOUT (lpd_pll_test_out),
.PLLPDPLLTESTCKSELN (pl_lpd_pll_test_ck_sel_n),
.PLLPDPLLTESTFRACTCLKSELN (pl_lpd_pll_test_fract_clk_sel_n),
.PLLPDPLLTESTFRACTENN (pl_lpd_pll_test_fract_en_n),
.PLLPDPLLTESTMUXSEL (pl_lpd_pll_test_mux_sel),
.PLLPDPLLTESTSEL (pl_lpd_pll_test_sel),
.FPDPLLTESTOUT (fpd_pll_test_out),
.PLFPDPLLTESTCKSELN (pl_fpd_pll_test_ck_sel_n),
.PLFPDPLLTESTFRACTCLKSELN (pl_fpd_pll_test_fract_clk_sel_n),
.PLFPDPLLTESTFRACTENN (pl_fpd_pll_test_fract_en_n),
.PLFPDPLLTESTMUXSEL (pl_fpd_pll_test_mux_sel),
.PLFPDPLLTESTSEL (pl_fpd_pll_test_sel),
.FMIOCHARGEMSELECTION (fmio_char_gem_selection),
.FMIOCHARGEMTESTSELECTN (fmio_char_gem_test_select_n),
.FMIOCHARGEMTESTINPUT (fmio_char_gem_test_input),
.FMIOCHARGEMTESTOUTPUT (fmio_char_gem_test_output),
.TESTDDR2PLDCDSKEWOUT (test_ddr2pl_dcd_skewout),
.TESTPL2DDRDCDSAMPLEPULSE (test_pl2ddr_dcd_sample_pulse),
.TESTBSCANENN (test_bscan_en_n),
.TESTBSCANTDI (test_bscan_tdi),
.TESTBSCANUPDATEDR (test_bscan_updatedr),
.TESTBSCANSHIFTDR (test_bscan_shiftdr),
.TESTBSCANRESETTAPB (test_bscan_reset_tap_b),
.TESTBSCANMISRJTAGLOAD (test_bscan_misr_jtag_load),
.TESTBSCANINTEST (test_bscan_intest),
.TESTBSCANEXTEST (test_bscan_extest),
.TESTBSCANCLOCKDR (test_bscan_clockdr),
.TESTBSCANACMODE (test_bscan_ac_mode),
.TESTBSCANACTEST (test_bscan_ac_test),
.TESTBSCANINITMEMORY (test_bscan_init_memory),
.TESTBSCANMODEC (test_bscan_mode_c),
.TESTBSCANTDO (test_bscan_tdo),
.IDBGL0TXCLK (i_dbg_l0_txclk),
.IDBGL0RXCLK (i_dbg_l0_rxclk),
.IDBGL1TXCLK (i_dbg_l1_txclk),
.IDBGL1RXCLK (i_dbg_l1_rxclk),
.IDBGL2TXCLK (i_dbg_l2_txclk),
.IDBGL2RXCLK (i_dbg_l2_rxclk),
.IDBGL3TXCLK (i_dbg_l3_txclk),
.IDBGL3RXCLK (i_dbg_l3_rxclk),
.IAFERXSYMBOLCLKBY2PL (i_afe_rx_symbol_clk_by_2_pl),
.PLFPDSPARE0IN (pl_fpd_spare_0_in),
.PLFPDSPARE1IN (pl_fpd_spare_1_in),
.PLFPDSPARE2IN (pl_fpd_spare_2_in),
.PLFPDSPARE3IN (pl_fpd_spare_3_in),
.PLFPDSPARE4IN (pl_fpd_spare_4_in),
.FPDPLSPARE0OUT (fpd_pl_spare_0_out),
.FPDPLSPARE1OUT (fpd_pl_spare_1_out),
.FPDPLSPARE2OUT (fpd_pl_spare_2_out),
.FPDPLSPARE3OUT (fpd_pl_spare_3_out),
.FPDPLSPARE4OUT (fpd_pl_spare_4_out),
.PLLPDSPARE0IN (pl_lpd_spare_0_in),
.PLLPDSPARE1IN (pl_lpd_spare_1_in),
.PLLPDSPARE2IN (pl_lpd_spare_2_in),
.PLLPDSPARE3IN (pl_lpd_spare_3_in),
.PLLPDSPARE4IN (pl_lpd_spare_4_in),
.LPDPLSPARE0OUT (lpd_pl_spare_0_out),
.LPDPLSPARE1OUT (lpd_pl_spare_1_out),
.LPDPLSPARE2OUT (lpd_pl_spare_2_out),
.LPDPLSPARE3OUT (lpd_pl_spare_3_out),
.LPDPLSPARE4OUT (lpd_pl_spare_4_out),
.ODBGL0PHYSTATUS (o_dbg_l0_phystatus),
.ODBGL0RXDATA (o_dbg_l0_rxdata),
.ODBGL0RXDATAK (o_dbg_l0_rxdatak),
.ODBGL0RXVALID (o_dbg_l0_rxvalid),
.ODBGL0RXSTATUS (o_dbg_l0_rxstatus),
.ODBGL0RXELECIDLE (o_dbg_l0_rxelecidle),
.ODBGL0RSTB (o_dbg_l0_rstb),
.ODBGL0TXDATA (o_dbg_l0_txdata),
.ODBGL0TXDATAK (o_dbg_l0_txdatak),
.ODBGL0RATE (o_dbg_l0_rate),
.ODBGL0POWERDOWN (o_dbg_l0_powerdown),
.ODBGL0TXELECIDLE (o_dbg_l0_txelecidle),
.ODBGL0TXDETRXLPBACK (o_dbg_l0_txdetrx_lpback),
.ODBGL0RXPOLARITY (o_dbg_l0_rxpolarity),
.ODBGL0TXSGMIIEWRAP (o_dbg_l0_tx_sgmii_ewrap),
.ODBGL0RXSGMIIENCDET (o_dbg_l0_rx_sgmii_en_cdet),
.ODBGL0SATACORERXDATA (o_dbg_l0_sata_corerxdata),
.ODBGL0SATACORERXDATAVALID (o_dbg_l0_sata_corerxdatavalid),
.ODBGL0SATACOREREADY (o_dbg_l0_sata_coreready),
.ODBGL0SATACORECLOCKREADY (o_dbg_l0_sata_coreclockready),
.ODBGL0SATACORERXSIGNALDET (o_dbg_l0_sata_corerxsignaldet),
.ODBGL0SATAPHYCTRLTXDATA (o_dbg_l0_sata_phyctrltxdata),
.ODBGL0SATAPHYCTRLTXIDLE (o_dbg_l0_sata_phyctrltxidle),
.ODBGL0SATAPHYCTRLTXRATE (o_dbg_l0_sata_phyctrltxrate),
.ODBGL0SATAPHYCTRLRXRATE (o_dbg_l0_sata_phyctrlrxrate),
.ODBGL0SATAPHYCTRLTXRST (o_dbg_l0_sata_phyctrltxrst),
.ODBGL0SATAPHYCTRLRXRST (o_dbg_l0_sata_phyctrlrxrst),
.ODBGL0SATAPHYCTRLRESET (o_dbg_l0_sata_phyctrlreset),
.ODBGL0SATAPHYCTRLPARTIAL (o_dbg_l0_sata_phyctrlpartial),
.ODBGL0SATAPHYCTRLSLUMBER (o_dbg_l0_sata_phyctrlslumber),
.ODBGL1PHYSTATUS (o_dbg_l1_phystatus),
.ODBGL1RXDATA (o_dbg_l1_rxdata),
.ODBGL1RXDATAK (o_dbg_l1_rxdatak),
.ODBGL1RXVALID (o_dbg_l1_rxvalid),
.ODBGL1RXSTATUS (o_dbg_l1_rxstatus),
.ODBGL1RXELECIDLE (o_dbg_l1_rxelecidle),
.ODBGL1RSTB (o_dbg_l1_rstb),
.ODBGL1TXDATA (o_dbg_l1_txdata),
.ODBGL1TXDATAK (o_dbg_l1_txdatak),
.ODBGL1RATE (o_dbg_l1_rate),
.ODBGL1POWERDOWN (o_dbg_l1_powerdown),
.ODBGL1TXELECIDLE (o_dbg_l1_txelecidle),
.ODBGL1TXDETRXLPBACK (o_dbg_l1_txdetrx_lpback),
.ODBGL1RXPOLARITY (o_dbg_l1_rxpolarity),
.ODBGL1TXSGMIIEWRAP (o_dbg_l1_tx_sgmii_ewrap),
.ODBGL1RXSGMIIENCDET (o_dbg_l1_rx_sgmii_en_cdet),
.ODBGL1SATACORERXDATA (o_dbg_l1_sata_corerxdata),
.ODBGL1SATACORERXDATAVALID (o_dbg_l1_sata_corerxdatavalid),
.ODBGL1SATACOREREADY (o_dbg_l1_sata_coreready),
.ODBGL1SATACORECLOCKREADY (o_dbg_l1_sata_coreclockready),
.ODBGL1SATACORERXSIGNALDET (o_dbg_l1_sata_corerxsignaldet),
.ODBGL1SATAPHYCTRLTXDATA (o_dbg_l1_sata_phyctrltxdata),
.ODBGL1SATAPHYCTRLTXIDLE (o_dbg_l1_sata_phyctrltxidle),
.ODBGL1SATAPHYCTRLTXRATE (o_dbg_l1_sata_phyctrltxrate),
.ODBGL1SATAPHYCTRLRXRATE (o_dbg_l1_sata_phyctrlrxrate),
.ODBGL1SATAPHYCTRLTXRST (o_dbg_l1_sata_phyctrltxrst),
.ODBGL1SATAPHYCTRLRXRST (o_dbg_l1_sata_phyctrlrxrst),
.ODBGL1SATAPHYCTRLRESET (o_dbg_l1_sata_phyctrlreset),
.ODBGL1SATAPHYCTRLPARTIAL (o_dbg_l1_sata_phyctrlpartial),
.ODBGL1SATAPHYCTRLSLUMBER (o_dbg_l1_sata_phyctrlslumber),
.ODBGL2PHYSTATUS (o_dbg_l2_phystatus),
.ODBGL2RXDATA (o_dbg_l2_rxdata),
.ODBGL2RXDATAK (o_dbg_l2_rxdatak),
.ODBGL2RXVALID (o_dbg_l2_rxvalid),
.ODBGL2RXSTATUS (o_dbg_l2_rxstatus),
.ODBGL2RXELECIDLE (o_dbg_l2_rxelecidle),
.ODBGL2RSTB (o_dbg_l2_rstb),
.ODBGL2TXDATA (o_dbg_l2_txdata),
.ODBGL2TXDATAK (o_dbg_l2_txdatak),
.ODBGL2RATE (o_dbg_l2_rate),
.ODBGL2POWERDOWN (o_dbg_l2_powerdown),
.ODBGL2TXELECIDLE (o_dbg_l2_txelecidle),
.ODBGL2TXDETRXLPBACK (o_dbg_l2_txdetrx_lpback),
.ODBGL2RXPOLARITY (o_dbg_l2_rxpolarity),
.ODBGL2TXSGMIIEWRAP (o_dbg_l2_tx_sgmii_ewrap),
.ODBGL2RXSGMIIENCDET (o_dbg_l2_rx_sgmii_en_cdet),
.ODBGL2SATACORERXDATA (o_dbg_l2_sata_corerxdata),
.ODBGL2SATACORERXDATAVALID (o_dbg_l2_sata_corerxdatavalid),
.ODBGL2SATACOREREADY (o_dbg_l2_sata_coreready),
.ODBGL2SATACORECLOCKREADY (o_dbg_l2_sata_coreclockready),
.ODBGL2SATACORERXSIGNALDET (o_dbg_l2_sata_corerxsignaldet),
.ODBGL2SATAPHYCTRLTXDATA (o_dbg_l2_sata_phyctrltxdata),
.ODBGL2SATAPHYCTRLTXIDLE (o_dbg_l2_sata_phyctrltxidle),
.ODBGL2SATAPHYCTRLTXRATE (o_dbg_l2_sata_phyctrltxrate),
.ODBGL2SATAPHYCTRLRXRATE (o_dbg_l2_sata_phyctrlrxrate),
.ODBGL2SATAPHYCTRLTXRST (o_dbg_l2_sata_phyctrltxrst),
.ODBGL2SATAPHYCTRLRXRST (o_dbg_l2_sata_phyctrlrxrst),
.ODBGL2SATAPHYCTRLRESET (o_dbg_l2_sata_phyctrlreset),
.ODBGL2SATAPHYCTRLPARTIAL (o_dbg_l2_sata_phyctrlpartial),
.ODBGL2SATAPHYCTRLSLUMBER (o_dbg_l2_sata_phyctrlslumber),
.ODBGL3PHYSTATUS (o_dbg_l3_phystatus),
.ODBGL3RXDATA (o_dbg_l3_rxdata),
.ODBGL3RXDATAK (o_dbg_l3_rxdatak),
.ODBGL3RXVALID (o_dbg_l3_rxvalid),
.ODBGL3RXSTATUS (o_dbg_l3_rxstatus),
.ODBGL3RXELECIDLE (o_dbg_l3_rxelecidle),
.ODBGL3RSTB (o_dbg_l3_rstb),
.ODBGL3TXDATA (o_dbg_l3_txdata),
.ODBGL3TXDATAK (o_dbg_l3_txdatak),
.ODBGL3RATE (o_dbg_l3_rate),
.ODBGL3POWERDOWN (o_dbg_l3_powerdown),
.ODBGL3TXELECIDLE (o_dbg_l3_txelecidle),
.ODBGL3TXDETRXLPBACK (o_dbg_l3_txdetrx_lpback),
.ODBGL3RXPOLARITY (o_dbg_l3_rxpolarity),
.ODBGL3TXSGMIIEWRAP (o_dbg_l3_tx_sgmii_ewrap),
.ODBGL3RXSGMIIENCDET (o_dbg_l3_rx_sgmii_en_cdet),
.ODBGL3SATACORERXDATA (o_dbg_l3_sata_corerxdata),
.ODBGL3SATACORERXDATAVALID (o_dbg_l3_sata_corerxdatavalid),
.ODBGL3SATACOREREADY (o_dbg_l3_sata_coreready),
.ODBGL3SATACORECLOCKREADY (o_dbg_l3_sata_coreclockready),
.ODBGL3SATACORERXSIGNALDET (o_dbg_l3_sata_corerxsignaldet),
.ODBGL3SATAPHYCTRLTXDATA (o_dbg_l3_sata_phyctrltxdata),
.ODBGL3SATAPHYCTRLTXIDLE (o_dbg_l3_sata_phyctrltxidle),
.ODBGL3SATAPHYCTRLTXRATE (o_dbg_l3_sata_phyctrltxrate),
.ODBGL3SATAPHYCTRLRXRATE (o_dbg_l3_sata_phyctrlrxrate),
.ODBGL3SATAPHYCTRLTXRST (o_dbg_l3_sata_phyctrltxrst),
.ODBGL3SATAPHYCTRLRXRST (o_dbg_l3_sata_phyctrlrxrst),
.ODBGL3SATAPHYCTRLRESET (o_dbg_l3_sata_phyctrlreset),
.ODBGL3SATAPHYCTRLPARTIAL (o_dbg_l3_sata_phyctrlpartial),
.ODBGL3SATAPHYCTRLSLUMBER (o_dbg_l3_sata_phyctrlslumber),
.DBGPATHFIFOBYPASS (dbg_path_fifo_bypass),
.IAFEPLLPDHSCLOCKR (i_afe_pll_pd_hs_clock_r),
.IAFEMODE (i_afe_mode),
.IBGCALAFEMODE (i_bgcal_afe_mode),
.OAFECMNCALIBCOMPOUT (o_afe_cmn_calib_comp_out),
.IAFECMNBGENABLELOWLEAKAGE (i_afe_cmn_bg_enable_low_leakage),
.IAFECMNBGISOCTRLBAR (i_afe_cmn_bg_iso_ctrl_bar),
.IAFECMNBGPD (i_afe_cmn_bg_pd),
.IAFECMNBGPDBGOK (i_afe_cmn_bg_pd_bg_ok),
.IAFECMNBGPDPTAT (i_afe_cmn_bg_pd_ptat),
.IAFECMNCALIBENICONST (i_afe_cmn_calib_en_iconst),
.IAFECMNCALIBENABLELOWLEAKAGE (i_afe_cmn_calib_enable_low_leakage),
.IAFECMNCALIBISOCTRLBAR (i_afe_cmn_calib_iso_ctrl_bar),
.OAFEPLLDCOCOUNT (o_afe_pll_dco_count),
.OAFEPLLCLKSYMHS (o_afe_pll_clk_sym_hs),
.OAFEPLLFBCLKFRAC (o_afe_pll_fbclk_frac),
.OAFERXPIPELFPSBCNRXELECIDLE (o_afe_rx_pipe_lfpsbcn_rxelecidle),
.OAFERXPIPESIGDET (o_afe_rx_pipe_sigdet),
.OAFERXSYMBOL (o_afe_rx_symbol),
.OAFERXSYMBOLCLKBY2 (o_afe_rx_symbol_clk_by_2),
.OAFERXUPHYSAVECALCODE (o_afe_rx_uphy_save_calcode),
.OAFERXUPHYSTARTLOOPBUF (o_afe_rx_uphy_startloop_buf),
.OAFERXUPHYRXCALIBDONE (o_afe_rx_uphy_rx_calib_done),
.IAFERXRXPMARSTB (i_afe_rx_rxpma_rstb),
.IAFERXUPHYRESTORECALCODEDATA (i_afe_rx_uphy_restore_calcode_data),
.IAFERXPIPERXEQTRAINING (i_afe_rx_pipe_rxeqtraining),
.IAFERXISOHSRXCTRLBAR (i_afe_rx_iso_hsrx_ctrl_bar),
.IAFERXISOLFPSCTRLBAR (i_afe_rx_iso_lfps_ctrl_bar),
.IAFERXISOSIGDETCTRLBAR (i_afe_rx_iso_sigdet_ctrl_bar),
.IAFERXHSRXCLOCKSTOPREQ (i_afe_rx_hsrx_clock_stop_req),
.OAFERXUPHYSAVECALCODEDATA (o_afe_rx_uphy_save_calcode_data),
.OAFERXHSRXCLOCKSTOPACK (o_afe_rx_hsrx_clock_stop_ack),
.OAFEPGAVDDCR (o_afe_pg_avddcr),
.OAFEPGAVDDIO (o_afe_pg_avddio),
.OAFEPGDVDDCR (o_afe_pg_dvddcr),
.OAFEPGSTATICAVDDCR (o_afe_pg_static_avddcr),
.OAFEPGSTATICAVDDIO (o_afe_pg_static_avddio),
.IPLLAFEMODE (i_pll_afe_mode),
.IAFEPLLCOARSECODE (i_afe_pll_coarse_code),
.IAFEPLLENCLOCKHSDIV2 (i_afe_pll_en_clock_hs_div2),
.IAFEPLLFBDIV (i_afe_pll_fbdiv),
.IAFEPLLLOADFBDIV (i_afe_pll_load_fbdiv),
.IAFEPLLPD (i_afe_pll_pd),
.IAFEPLLPDPFD (i_afe_pll_pd_pfd),
.IAFEPLLRSTFDBKDIV (i_afe_pll_rst_fdbk_div),
.IAFEPLLSTARTLOOP (i_afe_pll_startloop),
.IAFEPLLV2ICODE (i_afe_pll_v2i_code),
.IAFEPLLV2IPROG (i_afe_pll_v2i_prog),
.IAFEPLLVCOCNTWINDOW (i_afe_pll_vco_cnt_window),
.IAFERXMPHYGATESYMBOLCLK (i_afe_rx_mphy_gate_symbol_clk),
.IAFERXMPHYMUXHSBLS (i_afe_rx_mphy_mux_hsb_ls),
.IAFERXPIPERXTERMENABLE (i_afe_rx_pipe_rx_term_enable),
.IAFERXUPHYBIASGENICONSTCOREMIRRORENABLE (i_afe_rx_uphy_biasgen_iconst_core_mirror_enable),
.IAFERXUPHYBIASGENICONSTIOMIRRORENABLE (i_afe_rx_uphy_biasgen_iconst_io_mirror_enable),
.IAFERXUPHYBIASGENIRCONSTCOREMIRRORENABLE (i_afe_rx_uphy_biasgen_irconst_core_mirror_enable),
.IAFERXUPHYENABLECDR (i_afe_rx_uphy_enable_cdr),
.IAFERXUPHYENABLELOWLEAKAGE (i_afe_rx_uphy_enable_low_leakage),
.IAFERXRXPMAREFCLKDIG (i_afe_rx_rxpma_refclk_dig),
.IAFERXUPHYHSRXRSTB (i_afe_rx_uphy_hsrx_rstb),
.IAFERXUPHYPDNHSDES (i_afe_rx_uphy_pdn_hs_des),
.IAFERXUPHYPDSAMPC2C (i_afe_rx_uphy_pd_samp_c2c),
.IAFERXUPHYPDSAMPC2CECLK (i_afe_rx_uphy_pd_samp_c2c_eclk),
.IAFERXUPHYPSOCLKLANE (i_afe_rx_uphy_pso_clk_lane),
.IAFERXUPHYPSOEQ (i_afe_rx_uphy_pso_eq),
.IAFERXUPHYPSOHSRXDIG (i_afe_rx_uphy_pso_hsrxdig),
.IAFERXUPHYPSOIQPI (i_afe_rx_uphy_pso_iqpi),
.IAFERXUPHYPSOLFPSBCN (i_afe_rx_uphy_pso_lfpsbcn),
.IAFERXUPHYPSOSAMPFLOPS (i_afe_rx_uphy_pso_samp_flops),
.IAFERXUPHYPSOSIGDET (i_afe_rx_uphy_pso_sigdet),
.IAFERXUPHYRESTORECALCODE (i_afe_rx_uphy_restore_calcode),
.IAFERXUPHYRUNCALIB (i_afe_rx_uphy_run_calib),
.IAFERXUPHYRXLANEPOLARITYSWAP (i_afe_rx_uphy_rx_lane_polarity_swap),
.IAFERXUPHYSTARTLOOPPLL (i_afe_rx_uphy_startloop_pll),
.IAFERXUPHYHSCLKDIVISIONFACTOR (i_afe_rx_uphy_hsclk_division_factor),
.IAFERXUPHYRXPMAOPMODE (i_afe_rx_uphy_rx_pma_opmode),
.IAFETXENABLEHSCLKDIVISION (i_afe_tx_enable_hsclk_division),
.IAFETXENABLELDO (i_afe_tx_enable_ldo),
.IAFETXENABLEREF (i_afe_tx_enable_ref),
.IAFETXENABLESUPPLYHSCLK (i_afe_tx_enable_supply_hsclk),
.IAFETXENABLESUPPLYPIPE (i_afe_tx_enable_supply_pipe),
.IAFETXENABLESUPPLYSERIALIZER (i_afe_tx_enable_supply_serializer),
.IAFETXENABLESUPPLYUPHY (i_afe_tx_enable_supply_uphy),
.IAFETXHSSERRSTB (i_afe_tx_hs_ser_rstb),
.IAFETXHSSYMBOL (i_afe_tx_hs_symbol),
.IAFETXMPHYTXLSDATA (i_afe_tx_mphy_tx_ls_data),
.IAFETXPIPETXENABLEIDLEMODE (i_afe_tx_pipe_tx_enable_idle_mode),
.IAFETXPIPETXENABLELFPS (i_afe_tx_pipe_tx_enable_lfps),
.IAFETXPIPETXENABLERXDET (i_afe_tx_pipe_tx_enable_rxdet),
.IAFETXUPHYTXPMAOPMODE (i_afe_TX_uphy_txpma_opmode),
.IAFETXPMADIGDIGITALRESETN (i_afe_TX_pmadig_digital_reset_n),
.IAFETXSERIALIZERRSTREL (i_afe_TX_serializer_rst_rel),
.IAFETXPLLSYMBCLK2 (i_afe_TX_pll_symb_clk_2),
.IAFETXANAIFRATE (i_afe_TX_ana_if_rate),
.IAFETXENDIGSUBLPMODE (i_afe_TX_en_dig_sublp_mode),
.IAFETXLPBKSEL (i_afe_TX_LPBK_SEL),
.IAFETXISOCTRLBAR (i_afe_TX_iso_ctrl_bar),
.IAFETXSERISOCTRLBAR (i_afe_TX_ser_iso_ctrl_bar),
.IAFETXLFPSCLK (i_afe_TX_lfps_clk),
.IAFETXSERIALIZERRSTB (i_afe_TX_serializer_rstb),
.OAFETXDIGRESETRELACK (o_afe_TX_dig_reset_rel_ack),
.OAFETXPIPETXDNRXDET (o_afe_TX_pipe_TX_dn_rxdet),
.OAFETXPIPETXDPRXDET (o_afe_TX_pipe_TX_dp_rxdet),
.IAFETXPIPETXFASTESTCOMMONMODE (i_afe_tx_pipe_tx_fast_est_common_mode),
.ODBGL0TXCLK (o_dbg_l0_txclk),
.ODBGL0RXCLK (o_dbg_l0_rxclk),
.ODBGL1TXCLK (o_dbg_l1_txclk),
.ODBGL1RXCLK (o_dbg_l1_rxclk),
.ODBGL2TXCLK (o_dbg_l2_txclk),
.ODBGL2RXCLK (o_dbg_l2_rxclk),
.ODBGL3TXCLK (o_dbg_l3_txclk),
.ODBGL3RXCLK (o_dbg_l3_rxclk),
.DPVIDEOREFCLK(dp_video_ref_clk_i),
.DPAUDIOREFCLK(dp_audio_ref_clk_i)
);
end
else begin
PS8 PS8_i (
.MAXIGP0ACLK (maxihpm0_fpd_aclk),
.MAXIGP0AWID (maxigp0_awid),
.MAXIGP0AWADDR (maxigp0_awaddr),
.MAXIGP0AWLEN (maxigp0_awlen),
.MAXIGP0AWSIZE (maxigp0_awsize),
.MAXIGP0AWBURST (maxigp0_awburst),
.MAXIGP0AWLOCK (maxigp0_awlock),
.MAXIGP0AWCACHE (maxigp0_awcache),
.MAXIGP0AWPROT (maxigp0_awprot),
.MAXIGP0AWVALID (maxigp0_awvalid),
.MAXIGP0AWUSER (maxigp0_awuser),
.MAXIGP0AWREADY (maxigp0_awready),
.MAXIGP0WDATA (maxigp0_wdata_i),
.MAXIGP0WSTRB (maxigp0_wstrb_i),
.MAXIGP0WLAST (maxigp0_wlast),
.MAXIGP0WVALID (maxigp0_wvalid),
.MAXIGP0WREADY (maxigp0_wready),
.MAXIGP0BID (maxigp0_bid),
.MAXIGP0BRESP (maxigp0_bresp),
.MAXIGP0BVALID (maxigp0_bvalid),
.MAXIGP0BREADY (maxigp0_bready),
.MAXIGP0ARID (maxigp0_arid),
.MAXIGP0ARADDR (maxigp0_araddr),
.MAXIGP0ARLEN (maxigp0_arlen),
.MAXIGP0ARSIZE (maxigp0_arsize),
.MAXIGP0ARBURST (maxigp0_arburst),
.MAXIGP0ARLOCK (maxigp0_arlock),
.MAXIGP0ARCACHE (maxigp0_arcache),
.MAXIGP0ARPROT (maxigp0_arprot),
.MAXIGP0ARVALID (maxigp0_arvalid),
.MAXIGP0ARUSER (maxigp0_aruser),
.MAXIGP0ARREADY (maxigp0_arready),
.MAXIGP0RID (maxigp0_rid),
.MAXIGP0RDATA (maxigp0_rdata_i),
.MAXIGP0RRESP (maxigp0_rresp),
.MAXIGP0RLAST (maxigp0_rlast),
.MAXIGP0RVALID (maxigp0_rvalid),
.MAXIGP0RREADY (maxigp0_rready),
.MAXIGP0AWQOS (maxigp0_awqos),
.MAXIGP0ARQOS (maxigp0_arqos),
.MAXIGP1ACLK (maxihpm1_fpd_aclk),
.MAXIGP1AWID (maxigp1_awid),
.MAXIGP1AWADDR (maxigp1_awaddr),
.MAXIGP1AWLEN (maxigp1_awlen),
.MAXIGP1AWSIZE (maxigp1_awsize),
.MAXIGP1AWBURST (maxigp1_awburst),
.MAXIGP1AWLOCK (maxigp1_awlock),
.MAXIGP1AWCACHE (maxigp1_awcache),
.MAXIGP1AWPROT (maxigp1_awprot),
.MAXIGP1AWVALID (maxigp1_awvalid),
.MAXIGP1AWUSER (maxigp1_awuser),
.MAXIGP1AWREADY (maxigp1_awready),
.MAXIGP1WDATA (maxigp1_wdata_i),
.MAXIGP1WSTRB (maxigp1_wstrb_i),
.MAXIGP1WLAST (maxigp1_wlast),
.MAXIGP1WVALID (maxigp1_wvalid),
.MAXIGP1WREADY (maxigp1_wready),
.MAXIGP1BID (maxigp1_bid),
.MAXIGP1BRESP (maxigp1_bresp),
.MAXIGP1BVALID (maxigp1_bvalid),
.MAXIGP1BREADY (maxigp1_bready),
.MAXIGP1ARID (maxigp1_arid),
.MAXIGP1ARADDR (maxigp1_araddr),
.MAXIGP1ARLEN (maxigp1_arlen),
.MAXIGP1ARSIZE (maxigp1_arsize),
.MAXIGP1ARBURST (maxigp1_arburst),
.MAXIGP1ARLOCK (maxigp1_arlock),
.MAXIGP1ARCACHE (maxigp1_arcache),
.MAXIGP1ARPROT (maxigp1_arprot),
.MAXIGP1ARVALID (maxigp1_arvalid),
.MAXIGP1ARUSER (maxigp1_aruser),
.MAXIGP1ARREADY (maxigp1_arready),
.MAXIGP1RID (maxigp1_rid),
.MAXIGP1RDATA (maxigp1_rdata_i),
.MAXIGP1RRESP (maxigp1_rresp),
.MAXIGP1RLAST (maxigp1_rlast),
.MAXIGP1RVALID (maxigp1_rvalid),
.MAXIGP1RREADY (maxigp1_rready),
.MAXIGP1AWQOS (maxigp1_awqos),
.MAXIGP1ARQOS (maxigp1_arqos),
.MAXIGP2ACLK (maxihpm0_lpd_aclk),
.MAXIGP2AWID (maxigp2_awid),
.MAXIGP2AWADDR (maxigp2_awaddr),
.MAXIGP2AWLEN (maxigp2_awlen),
.MAXIGP2AWSIZE (maxigp2_awsize),
.MAXIGP2AWBURST (maxigp2_awburst),
.MAXIGP2AWLOCK (maxigp2_awlock),
.MAXIGP2AWCACHE (maxigp2_awcache),
.MAXIGP2AWPROT (maxigp2_awprot),
.MAXIGP2AWVALID (maxigp2_awvalid),
.MAXIGP2AWUSER (maxigp2_awuser),
.MAXIGP2AWREADY (maxigp2_awready),
.MAXIGP2WDATA (maxigp2_wdata_i),
.MAXIGP2WSTRB (maxigp2_wstrb_i),
.MAXIGP2WLAST (maxigp2_wlast),
.MAXIGP2WVALID (maxigp2_wvalid),
.MAXIGP2WREADY (maxigp2_wready),
.MAXIGP2BID (maxigp2_bid),
.MAXIGP2BRESP (maxigp2_bresp),
.MAXIGP2BVALID (maxigp2_bvalid),
.MAXIGP2BREADY (maxigp2_bready),
.MAXIGP2ARID (maxigp2_arid),
.MAXIGP2ARADDR (maxigp2_araddr),
.MAXIGP2ARLEN (maxigp2_arlen),
.MAXIGP2ARSIZE (maxigp2_arsize),
.MAXIGP2ARBURST (maxigp2_arburst),
.MAXIGP2ARLOCK (maxigp2_arlock),
.MAXIGP2ARCACHE (maxigp2_arcache),
.MAXIGP2ARPROT (maxigp2_arprot),
.MAXIGP2ARVALID (maxigp2_arvalid),
.MAXIGP2ARUSER (maxigp2_aruser),
.MAXIGP2ARREADY (maxigp2_arready),
.MAXIGP2RID (maxigp2_rid),
.MAXIGP2RDATA (maxigp2_rdata_i),
.MAXIGP2RRESP (maxigp2_rresp),
.MAXIGP2RLAST (maxigp2_rlast),
.MAXIGP2RVALID (maxigp2_rvalid),
.MAXIGP2RREADY (maxigp2_rready),
.MAXIGP2AWQOS (maxigp2_awqos),
.MAXIGP2ARQOS (maxigp2_arqos),
.SAXIGP0RCLK (saxihpc0_fpd_rclk_temp),
.SAXIGP0WCLK (saxihpc0_fpd_wclk_temp),
.SAXIGP0ARUSER (saxigp0_aruser),
.SAXIGP0AWUSER (saxigp0_awuser),
.SAXIGP0AWID (saxigp0_awid),
.SAXIGP0AWADDR (saxigp0_awaddr),
.SAXIGP0AWLEN (saxigp0_awlen),
.SAXIGP0AWSIZE (saxigp0_awsize),
.SAXIGP0AWBURST (saxigp0_awburst),
.SAXIGP0AWLOCK (saxigp0_awlock),
.SAXIGP0AWCACHE (saxigp0_awcache),
.SAXIGP0AWPROT (saxigp0_awprot),
.SAXIGP0AWVALID (saxigp0_awvalid),
.SAXIGP0AWREADY (saxigp0_awready),
.SAXIGP0WDATA (saxigp0_wdata_i),
.SAXIGP0WSTRB (saxigp0_wstrb_i),
.SAXIGP0WLAST (saxigp0_wlast),
.SAXIGP0WVALID (saxigp0_wvalid),
.SAXIGP0WREADY (saxigp0_wready),
.SAXIGP0BID (saxigp0_bid),
.SAXIGP0BRESP (saxigp0_bresp),
.SAXIGP0BVALID (saxigp0_bvalid),
.SAXIGP0BREADY (saxigp0_bready),
.SAXIGP0ARID (saxigp0_arid),
.SAXIGP0ARADDR (saxigp0_araddr),
.SAXIGP0ARLEN (saxigp0_arlen),
.SAXIGP0ARSIZE (saxigp0_arsize),
.SAXIGP0ARBURST (saxigp0_arburst),
.SAXIGP0ARLOCK (saxigp0_arlock),
.SAXIGP0ARCACHE (saxigp0_arcache),
.SAXIGP0ARPROT (saxigp0_arprot),
.SAXIGP0ARVALID (saxigp0_arvalid),
.SAXIGP0ARREADY (saxigp0_arready),
.SAXIGP0RID (saxigp0_rid),
.SAXIGP0RDATA (saxigp0_rdata_i),
.SAXIGP0RRESP (saxigp0_rresp),
.SAXIGP0RLAST (saxigp0_rlast),
.SAXIGP0RVALID (saxigp0_rvalid),
.SAXIGP0RREADY (saxigp0_rready),
.SAXIGP0AWQOS (saxigp0_awqos),
.SAXIGP0ARQOS (saxigp0_arqos),
.SAXIGP0RCOUNT (saxigp0_rcount),
.SAXIGP0WCOUNT (saxigp0_wcount),
.SAXIGP0RACOUNT (saxigp0_racount),
.SAXIGP0WACOUNT (saxigp0_wacount),
.SAXIGP1RCLK (saxihpc1_fpd_rclk_temp),
.SAXIGP1WCLK (saxihpc1_fpd_wclk_temp),
.SAXIGP1ARUSER (saxigp1_aruser),
.SAXIGP1AWUSER (saxigp1_awuser),
.SAXIGP1AWID (saxigp1_awid),
.SAXIGP1AWADDR (saxigp1_awaddr),
.SAXIGP1AWLEN (saxigp1_awlen),
.SAXIGP1AWSIZE (saxigp1_awsize),
.SAXIGP1AWBURST (saxigp1_awburst),
.SAXIGP1AWLOCK (saxigp1_awlock),
.SAXIGP1AWCACHE (saxigp1_awcache),
.SAXIGP1AWPROT (saxigp1_awprot),
.SAXIGP1AWVALID (saxigp1_awvalid),
.SAXIGP1AWREADY (saxigp1_awready),
.SAXIGP1WDATA (saxigp1_wdata_i),
.SAXIGP1WSTRB (saxigp1_wstrb_i),
.SAXIGP1WLAST (saxigp1_wlast),
.SAXIGP1WVALID (saxigp1_wvalid),
.SAXIGP1WREADY (saxigp1_wready),
.SAXIGP1BID (saxigp1_bid),
.SAXIGP1BRESP (saxigp1_bresp),
.SAXIGP1BVALID (saxigp1_bvalid),
.SAXIGP1BREADY (saxigp1_bready),
.SAXIGP1ARID (saxigp1_arid),
.SAXIGP1ARADDR (saxigp1_araddr),
.SAXIGP1ARLEN (saxigp1_arlen),
.SAXIGP1ARSIZE (saxigp1_arsize),
.SAXIGP1ARBURST (saxigp1_arburst),
.SAXIGP1ARLOCK (saxigp1_arlock),
.SAXIGP1ARCACHE (saxigp1_arcache),
.SAXIGP1ARPROT (saxigp1_arprot),
.SAXIGP1ARVALID (saxigp1_arvalid),
.SAXIGP1ARREADY (saxigp1_arready),
.SAXIGP1RID (saxigp1_rid),
.SAXIGP1RDATA (saxigp1_rdata_i),
.SAXIGP1RRESP (saxigp1_rresp),
.SAXIGP1RLAST (saxigp1_rlast),
.SAXIGP1RVALID (saxigp1_rvalid),
.SAXIGP1RREADY (saxigp1_rready),
.SAXIGP1AWQOS (saxigp1_awqos),
.SAXIGP1ARQOS (saxigp1_arqos),
.SAXIGP1RCOUNT (saxigp1_rcount),
.SAXIGP1WCOUNT (saxigp1_wcount),
.SAXIGP1RACOUNT (saxigp1_racount),
.SAXIGP1WACOUNT (saxigp1_wacount),
.SAXIGP2RCLK (saxihp0_fpd_rclk_temp),
.SAXIGP2WCLK (saxihp0_fpd_wclk_temp),
.SAXIGP2ARUSER (saxigp2_aruser),
.SAXIGP2AWUSER (saxigp2_awuser),
.SAXIGP2AWID (saxigp2_awid),
.SAXIGP2AWADDR (saxigp2_awaddr),
.SAXIGP2AWLEN (saxigp2_awlen),
.SAXIGP2AWSIZE (saxigp2_awsize),
.SAXIGP2AWBURST (saxigp2_awburst),
.SAXIGP2AWLOCK (saxigp2_awlock),
.SAXIGP2AWCACHE (saxigp2_awcache),
.SAXIGP2AWPROT (saxigp2_awprot),
.SAXIGP2AWVALID (saxigp2_awvalid),
.SAXIGP2AWREADY (saxigp2_awready),
.SAXIGP2WDATA (saxigp2_wdata_i),
.SAXIGP2WSTRB (saxigp2_wstrb_i),
.SAXIGP2WLAST (saxigp2_wlast),
.SAXIGP2WVALID (saxigp2_wvalid),
.SAXIGP2WREADY (saxigp2_wready),
.SAXIGP2BID (saxigp2_bid),
.SAXIGP2BRESP (saxigp2_bresp),
.SAXIGP2BVALID (saxigp2_bvalid),
.SAXIGP2BREADY (saxigp2_bready),
.SAXIGP2ARID (saxigp2_arid),
.SAXIGP2ARADDR (saxigp2_araddr),
.SAXIGP2ARLEN (saxigp2_arlen),
.SAXIGP2ARSIZE (saxigp2_arsize),
.SAXIGP2ARBURST (saxigp2_arburst),
.SAXIGP2ARLOCK (saxigp2_arlock),
.SAXIGP2ARCACHE (saxigp2_arcache),
.SAXIGP2ARPROT (saxigp2_arprot),
.SAXIGP2ARVALID (saxigp2_arvalid),
.SAXIGP2ARREADY (saxigp2_arready),
.SAXIGP2RID (saxigp2_rid),
.SAXIGP2RDATA (saxigp2_rdata_i),
.SAXIGP2RRESP (saxigp2_rresp),
.SAXIGP2RLAST (saxigp2_rlast),
.SAXIGP2RVALID (saxigp2_rvalid),
.SAXIGP2RREADY (saxigp2_rready),
.SAXIGP2AWQOS (saxigp2_awqos),
.SAXIGP2ARQOS (saxigp2_arqos),
.SAXIGP2RCOUNT (saxigp2_rcount),
.SAXIGP2WCOUNT (saxigp2_wcount),
.SAXIGP2RACOUNT (saxigp2_racount),
.SAXIGP2WACOUNT (saxigp2_wacount),
.SAXIGP3RCLK (saxihp1_fpd_rclk_temp),
.SAXIGP3WCLK (saxihp1_fpd_wclk_temp),
.SAXIGP3ARUSER (saxigp3_aruser),
.SAXIGP3AWUSER (saxigp3_awuser),
.SAXIGP3AWID (saxigp3_awid),
.SAXIGP3AWADDR (saxigp3_awaddr),
.SAXIGP3AWLEN (saxigp3_awlen),
.SAXIGP3AWSIZE (saxigp3_awsize),
.SAXIGP3AWBURST (saxigp3_awburst),
.SAXIGP3AWLOCK (saxigp3_awlock),
.SAXIGP3AWCACHE (saxigp3_awcache),
.SAXIGP3AWPROT (saxigp3_awprot),
.SAXIGP3AWVALID (saxigp3_awvalid),
.SAXIGP3AWREADY (saxigp3_awready),
.SAXIGP3WDATA (saxigp3_wdata_i),
.SAXIGP3WSTRB (saxigp3_wstrb_i),
.SAXIGP3WLAST (saxigp3_wlast),
.SAXIGP3WVALID (saxigp3_wvalid),
.SAXIGP3WREADY (saxigp3_wready),
.SAXIGP3BID (saxigp3_bid),
.SAXIGP3BRESP (saxigp3_bresp),
.SAXIGP3BVALID (saxigp3_bvalid),
.SAXIGP3BREADY (saxigp3_bready),
.SAXIGP3ARID (saxigp3_arid),
.SAXIGP3ARADDR (saxigp3_araddr),
.SAXIGP3ARLEN (saxigp3_arlen),
.SAXIGP3ARSIZE (saxigp3_arsize),
.SAXIGP3ARBURST (saxigp3_arburst),
.SAXIGP3ARLOCK (saxigp3_arlock),
.SAXIGP3ARCACHE (saxigp3_arcache),
.SAXIGP3ARPROT (saxigp3_arprot),
.SAXIGP3ARVALID (saxigp3_arvalid),
.SAXIGP3ARREADY (saxigp3_arready),
.SAXIGP3RID (saxigp3_rid),
.SAXIGP3RDATA (saxigp3_rdata_i),
.SAXIGP3RRESP (saxigp3_rresp),
.SAXIGP3RLAST (saxigp3_rlast),
.SAXIGP3RVALID (saxigp3_rvalid),
.SAXIGP3RREADY (saxigp3_rready),
.SAXIGP3AWQOS (saxigp3_awqos),
.SAXIGP3ARQOS (saxigp3_arqos),
.SAXIGP3RCOUNT (saxigp3_rcount),
.SAXIGP3WCOUNT (saxigp3_wcount),
.SAXIGP3RACOUNT (saxigp3_racount),
.SAXIGP3WACOUNT (saxigp3_wacount),
.SAXIGP4RCLK (saxihp2_fpd_rclk_temp),
.SAXIGP4WCLK (saxihp2_fpd_wclk_temp),
.SAXIGP4ARUSER (saxigp4_aruser),
.SAXIGP4AWUSER (saxigp4_awuser),
.SAXIGP4AWID (saxigp4_awid),
.SAXIGP4AWADDR (saxigp4_awaddr),
.SAXIGP4AWLEN (saxigp4_awlen),
.SAXIGP4AWSIZE (saxigp4_awsize),
.SAXIGP4AWBURST (saxigp4_awburst),
.SAXIGP4AWLOCK (saxigp4_awlock),
.SAXIGP4AWCACHE (saxigp4_awcache),
.SAXIGP4AWPROT (saxigp4_awprot),
.SAXIGP4AWVALID (saxigp4_awvalid),
.SAXIGP4AWREADY (saxigp4_awready),
.SAXIGP4WDATA (saxigp4_wdata_i),
.SAXIGP4WSTRB (saxigp4_wstrb_i),
.SAXIGP4WLAST (saxigp4_wlast),
.SAXIGP4WVALID (saxigp4_wvalid),
.SAXIGP4WREADY (saxigp4_wready),
.SAXIGP4BID (saxigp4_bid),
.SAXIGP4BRESP (saxigp4_bresp),
.SAXIGP4BVALID (saxigp4_bvalid),
.SAXIGP4BREADY (saxigp4_bready),
.SAXIGP4ARID (saxigp4_arid),
.SAXIGP4ARADDR (saxigp4_araddr),
.SAXIGP4ARLEN (saxigp4_arlen),
.SAXIGP4ARSIZE (saxigp4_arsize),
.SAXIGP4ARBURST (saxigp4_arburst),
.SAXIGP4ARLOCK (saxigp4_arlock),
.SAXIGP4ARCACHE (saxigp4_arcache),
.SAXIGP4ARPROT (saxigp4_arprot),
.SAXIGP4ARVALID (saxigp4_arvalid),
.SAXIGP4ARREADY (saxigp4_arready),
.SAXIGP4RID (saxigp4_rid),
.SAXIGP4RDATA (saxigp4_rdata_i),
.SAXIGP4RRESP (saxigp4_rresp),
.SAXIGP4RLAST (saxigp4_rlast),
.SAXIGP4RVALID (saxigp4_rvalid),
.SAXIGP4RREADY (saxigp4_rready),
.SAXIGP4AWQOS (saxigp4_awqos),
.SAXIGP4ARQOS (saxigp4_arqos),
.SAXIGP4RCOUNT (saxigp4_rcount),
.SAXIGP4WCOUNT (saxigp4_wcount),
.SAXIGP4RACOUNT (saxigp4_racount),
.SAXIGP4WACOUNT (saxigp4_wacount),
.SAXIGP5RCLK (saxihp3_fpd_rclk_temp),
.SAXIGP5WCLK (saxihp3_fpd_wclk_temp),
.SAXIGP5ARUSER (saxigp5_aruser),
.SAXIGP5AWUSER (saxigp5_awuser),
.SAXIGP5AWID (saxigp5_awid),
.SAXIGP5AWADDR (saxigp5_awaddr),
.SAXIGP5AWLEN (saxigp5_awlen),
.SAXIGP5AWSIZE (saxigp5_awsize),
.SAXIGP5AWBURST (saxigp5_awburst),
.SAXIGP5AWLOCK (saxigp5_awlock),
.SAXIGP5AWCACHE (saxigp5_awcache),
.SAXIGP5AWPROT (saxigp5_awprot),
.SAXIGP5AWVALID (saxigp5_awvalid),
.SAXIGP5AWREADY (saxigp5_awready),
.SAXIGP5WDATA (saxigp5_wdata_i),
.SAXIGP5WSTRB (saxigp5_wstrb_i),
.SAXIGP5WLAST (saxigp5_wlast),
.SAXIGP5WVALID (saxigp5_wvalid),
.SAXIGP5WREADY (saxigp5_wready),
.SAXIGP5BID (saxigp5_bid),
.SAXIGP5BRESP (saxigp5_bresp),
.SAXIGP5BVALID (saxigp5_bvalid),
.SAXIGP5BREADY (saxigp5_bready),
.SAXIGP5ARID (saxigp5_arid),
.SAXIGP5ARADDR (saxigp5_araddr),
.SAXIGP5ARLEN (saxigp5_arlen),
.SAXIGP5ARSIZE (saxigp5_arsize),
.SAXIGP5ARBURST (saxigp5_arburst),
.SAXIGP5ARLOCK (saxigp5_arlock),
.SAXIGP5ARCACHE (saxigp5_arcache),
.SAXIGP5ARPROT (saxigp5_arprot),
.SAXIGP5ARVALID (saxigp5_arvalid),
.SAXIGP5ARREADY (saxigp5_arready),
.SAXIGP5RID (saxigp5_rid),
.SAXIGP5RDATA (saxigp5_rdata_i),
.SAXIGP5RRESP (saxigp5_rresp),
.SAXIGP5RLAST (saxigp5_rlast),
.SAXIGP5RVALID (saxigp5_rvalid),
.SAXIGP5RREADY (saxigp5_rready),
.SAXIGP5AWQOS (saxigp5_awqos),
.SAXIGP5ARQOS (saxigp5_arqos),
.SAXIGP5RCOUNT (saxigp5_rcount),
.SAXIGP5WCOUNT (saxigp5_wcount),
.SAXIGP5RACOUNT (saxigp5_racount),
.SAXIGP5WACOUNT (saxigp5_wacount),
.SAXIGP6RCLK (saxi_lpd_rclk_temp),
.SAXIGP6WCLK (saxi_lpd_wclk_temp),
.SAXIGP6ARUSER (saxigp6_aruser),
.SAXIGP6AWUSER (saxigp6_awuser),
.SAXIGP6AWID (saxigp6_awid),
.SAXIGP6AWADDR (saxigp6_awaddr),
.SAXIGP6AWLEN (saxigp6_awlen),
.SAXIGP6AWSIZE (saxigp6_awsize),
.SAXIGP6AWBURST (saxigp6_awburst),
.SAXIGP6AWLOCK (saxigp6_awlock),
.SAXIGP6AWCACHE (saxigp6_awcache),
.SAXIGP6AWPROT (saxigp6_awprot),
.SAXIGP6AWVALID (saxigp6_awvalid),
.SAXIGP6AWREADY (saxigp6_awready),
.SAXIGP6WDATA (saxigp6_wdata_i),
.SAXIGP6WSTRB (saxigp6_wstrb_i),
.SAXIGP6WLAST (saxigp6_wlast),
.SAXIGP6WVALID (saxigp6_wvalid),
.SAXIGP6WREADY (saxigp6_wready),
.SAXIGP6BID (saxigp6_bid),
.SAXIGP6BRESP (saxigp6_bresp),
.SAXIGP6BVALID (saxigp6_bvalid),
.SAXIGP6BREADY (saxigp6_bready),
.SAXIGP6ARID (saxigp6_arid),
.SAXIGP6ARADDR (saxigp6_araddr),
.SAXIGP6ARLEN (saxigp6_arlen),
.SAXIGP6ARSIZE (saxigp6_arsize),
.SAXIGP6ARBURST (saxigp6_arburst),
.SAXIGP6ARLOCK (saxigp6_arlock),
.SAXIGP6ARCACHE (saxigp6_arcache),
.SAXIGP6ARPROT (saxigp6_arprot),
.SAXIGP6ARVALID (saxigp6_arvalid),
.SAXIGP6ARREADY (saxigp6_arready),
.SAXIGP6RID (saxigp6_rid),
.SAXIGP6RDATA (saxigp6_rdata_i),
.SAXIGP6RRESP (saxigp6_rresp),
.SAXIGP6RLAST (saxigp6_rlast),
.SAXIGP6RVALID (saxigp6_rvalid),
.SAXIGP6RREADY (saxigp6_rready),
.SAXIGP6AWQOS (saxigp6_awqos),
.SAXIGP6ARQOS (saxigp6_arqos),
.SAXIGP6RCOUNT (saxigp6_rcount),
.SAXIGP6WCOUNT (saxigp6_wcount),
.SAXIGP6RACOUNT (saxigp6_racount),
.SAXIGP6WACOUNT (saxigp6_wacount),
.SAXIACPACLK (saxiacp_fpd_aclk),
.SAXIACPAWADDR (saxiacp_awaddr),
.SAXIACPAWID (saxiacp_awid),
.SAXIACPAWLEN (saxiacp_awlen),
.SAXIACPAWSIZE (saxiacp_awsize),
.SAXIACPAWBURST (saxiacp_awburst),
.SAXIACPAWLOCK (saxiacp_awlock),
.SAXIACPAWCACHE (saxiacp_awcache),
.SAXIACPAWPROT (saxiacp_awprot),
.SAXIACPAWVALID (saxiacp_awvalid),
.SAXIACPAWREADY (saxiacp_awready),
.SAXIACPAWUSER (saxiacp_awuser),
.SAXIACPAWQOS (saxiacp_awqos),
.SAXIACPWLAST (saxiacp_wlast),
.SAXIACPWDATA (saxiacp_wdata),
.SAXIACPWSTRB (saxiacp_wstrb),
.SAXIACPWVALID (saxiacp_wvalid),
.SAXIACPWREADY (saxiacp_wready),
.SAXIACPBRESP (saxiacp_bresp),
.SAXIACPBID (saxiacp_bid),
.SAXIACPBVALID (saxiacp_bvalid),
.SAXIACPBREADY (saxiacp_bready),
.SAXIACPARADDR (saxiacp_araddr),
.SAXIACPARID (saxiacp_arid),
.SAXIACPARLEN (saxiacp_arlen),
.SAXIACPARSIZE (saxiacp_arsize),
.SAXIACPARBURST (saxiacp_arburst),
.SAXIACPARLOCK (saxiacp_arlock),
.SAXIACPARCACHE (saxiacp_arcache),
.SAXIACPARPROT (saxiacp_arprot),
.SAXIACPARVALID (saxiacp_arvalid),
.SAXIACPARREADY (saxiacp_arready),
.SAXIACPARUSER (saxiacp_aruser),
.SAXIACPARQOS (saxiacp_arqos),
.SAXIACPRID (saxiacp_rid),
.SAXIACPRLAST (saxiacp_rlast),
.SAXIACPRDATA (saxiacp_rdata),
.SAXIACPRRESP (saxiacp_rresp),
.SAXIACPRVALID (saxiacp_rvalid),
.SAXIACPRREADY (saxiacp_rready),
.PLACECLK (sacefpd_aclk),
.SACEFPDAWVALID (sacefpd_awvalid),
.SACEFPDAWREADY (sacefpd_awready),
.SACEFPDAWID (sacefpd_awid),
.SACEFPDAWADDR (sacefpd_awaddr),
.SACEFPDAWREGION (sacefpd_awregion),
.SACEFPDAWLEN (sacefpd_awlen),
.SACEFPDAWSIZE (sacefpd_awsize),
.SACEFPDAWBURST (sacefpd_awburst),
.SACEFPDAWLOCK (sacefpd_awlock),
.SACEFPDAWCACHE (sacefpd_awcache),
.SACEFPDAWPROT (sacefpd_awprot),
.SACEFPDAWDOMAIN (sacefpd_awdomain),
.SACEFPDAWSNOOP (sacefpd_awsnoop),
.SACEFPDAWBAR (sacefpd_awbar),
.SACEFPDAWQOS (sacefpd_awqos),
.SACEFPDAWUSER ({6'b000000,4'b1111,sacefpd_awuser[5:0]}),
.SACEFPDWVALID (sacefpd_wvalid),
.SACEFPDWREADY (sacefpd_wready),
.SACEFPDWDATA (sacefpd_wdata),
.SACEFPDWSTRB (sacefpd_wstrb),
.SACEFPDWLAST (sacefpd_wlast),
.SACEFPDWUSER (sacefpd_wuser),
.SACEFPDBVALID (sacefpd_bvalid),
.SACEFPDBREADY (sacefpd_bready),
.SACEFPDBID (sacefpd_bid),
.SACEFPDBRESP (sacefpd_bresp),
.SACEFPDBUSER (sacefpd_buser),
.SACEFPDARVALID (sacefpd_arvalid),
.SACEFPDARREADY (sacefpd_arready),
.SACEFPDARID (sacefpd_arid),
.SACEFPDARADDR (sacefpd_araddr),
.SACEFPDARREGION (sacefpd_arregion),
.SACEFPDARLEN (sacefpd_arlen),
.SACEFPDARSIZE (sacefpd_arsize),
.SACEFPDARBURST (sacefpd_arburst),
.SACEFPDARLOCK (sacefpd_arlock),
.SACEFPDARCACHE (sacefpd_arcache),
.SACEFPDARPROT (sacefpd_arprot),
.SACEFPDARDOMAIN (sacefpd_ardomain),
.SACEFPDARSNOOP (sacefpd_arsnoop),
.SACEFPDARBAR (sacefpd_arbar),
.SACEFPDARQOS (sacefpd_arqos),
.SACEFPDARUSER ({6'b000000,4'b1111,sacefpd_aruser[5:0]}),
.SACEFPDRVALID (sacefpd_rvalid),
.SACEFPDRREADY (sacefpd_rready),
.SACEFPDRID (sacefpd_rid),
.SACEFPDRDATA (sacefpd_rdata),
.SACEFPDRRESP (sacefpd_rresp),
.SACEFPDRLAST (sacefpd_rlast),
.SACEFPDRUSER (sacefpd_ruser),
.SACEFPDACVALID (sacefpd_acvalid),
.SACEFPDACREADY (sacefpd_acready),
.SACEFPDACADDR (sacefpd_acaddr),
.SACEFPDACSNOOP (sacefpd_acsnoop),
.SACEFPDACPROT (sacefpd_acprot),
.SACEFPDCRVALID (sacefpd_crvalid),
.SACEFPDCRREADY (sacefpd_crready),
.SACEFPDCRRESP (sacefpd_crresp),
.SACEFPDCDVALID (sacefpd_cdvalid),
.SACEFPDCDREADY (sacefpd_cdready),
.SACEFPDCDDATA (sacefpd_cddata),
.SACEFPDCDLAST (sacefpd_cdlast),
.SACEFPDWACK (sacefpd_wack),
.SACEFPDRACK (sacefpd_rack),
.EMIOCAN0PHYTX (emio_can0_phy_tx),
.EMIOCAN0PHYRX (emio_can0_phy_rx),
.EMIOCAN1PHYTX (emio_can1_phy_tx),
.EMIOCAN1PHYRX (emio_can1_phy_rx),
.EMIOENET0GMIIRXCLK (emio_enet0_gmii_rx_clk),
.EMIOENET0SPEEDMODE (emio_enet0_speed_mode),
.EMIOENET0GMIICRS (emio_enet0_gmii_crs),
.EMIOENET0GMIICOL (emio_enet0_gmii_col),
.EMIOENET0GMIIRXD (emio_enet0_gmii_rxd),
.EMIOENET0GMIIRXER (emio_enet0_gmii_rx_er),
.EMIOENET0GMIIRXDV (emio_enet0_gmii_rx_dv),
.EMIOENET0GMIITXCLK (emio_enet0_gmii_tx_clk),
.EMIOENET0GMIITXD (emio_enet0_gmii_txd),
.EMIOENET0GMIITXEN (emio_enet0_gmii_tx_en),
.EMIOENET0GMIITXER (emio_enet0_gmii_tx_er),
.EMIOENET0MDIOMDC (emio_enet0_mdio_mdc),
.EMIOENET0MDIOI (emio_enet0_mdio_i),
.EMIOENET0MDIOO (emio_enet0_mdio_o),
.EMIOENET0MDIOTN (emio_enet0_mdio_tri),
.EMIOENET1GMIIRXCLK (emio_enet1_gmii_rx_clk),
.EMIOENET1SPEEDMODE (emio_enet1_speed_mode),
.EMIOENET1GMIICRS (emio_enet1_gmii_crs),
.EMIOENET1GMIICOL (emio_enet1_gmii_col),
.EMIOENET1GMIIRXD (emio_enet1_gmii_rxd),
.EMIOENET1GMIIRXER (emio_enet1_gmii_rx_er),
.EMIOENET1GMIIRXDV (emio_enet1_gmii_rx_dv),
.EMIOENET1GMIITXCLK (emio_enet1_gmii_tx_clk),
.EMIOENET1GMIITXD (emio_enet1_gmii_txd),
.EMIOENET1GMIITXEN (emio_enet1_gmii_tx_en),
.EMIOENET1GMIITXER (emio_enet1_gmii_tx_er),
.EMIOENET1MDIOMDC (emio_enet1_mdio_mdc),
.EMIOENET1MDIOI (emio_enet1_mdio_i),
.EMIOENET1MDIOO (emio_enet1_mdio_o),
.EMIOENET1MDIOTN (emio_enet1_mdio_tri),
.EMIOENET2GMIIRXCLK (emio_enet2_gmii_rx_clk),
.EMIOENET2SPEEDMODE (emio_enet2_speed_mode),
.EMIOENET2GMIICRS (emio_enet2_gmii_crs),
.EMIOENET2GMIICOL (emio_enet2_gmii_col),
.EMIOENET2GMIIRXD (emio_enet2_gmii_rxd),
.EMIOENET2GMIIRXER (emio_enet2_gmii_rx_er),
.EMIOENET2GMIIRXDV (emio_enet2_gmii_rx_dv),
.EMIOENET2GMIITXCLK (emio_enet2_gmii_tx_clk),
.EMIOENET2GMIITXD (emio_enet2_gmii_txd),
.EMIOENET2GMIITXEN (emio_enet2_gmii_tx_en),
.EMIOENET2GMIITXER (emio_enet2_gmii_tx_er),
.EMIOENET2MDIOMDC (emio_enet2_mdio_mdc),
.EMIOENET2MDIOI (emio_enet2_mdio_i),
.EMIOENET2MDIOO (emio_enet2_mdio_o),
.EMIOENET2MDIOTN (emio_enet2_mdio_tri),
.EMIOENET3GMIIRXCLK (emio_enet3_gmii_rx_clk),
.EMIOENET3SPEEDMODE (emio_enet3_speed_mode),
.EMIOENET3GMIICRS (emio_enet3_gmii_crs),
.EMIOENET3GMIICOL (emio_enet3_gmii_col),
.EMIOENET3GMIIRXD (emio_enet3_gmii_rxd),
.EMIOENET3GMIIRXER (emio_enet3_gmii_rx_er),
.EMIOENET3GMIIRXDV (emio_enet3_gmii_rx_dv),
.EMIOENET3GMIITXCLK (emio_enet3_gmii_tx_clk),
.EMIOENET3GMIITXD (emio_enet3_gmii_txd),
.EMIOENET3GMIITXEN (emio_enet3_gmii_tx_en),
.EMIOENET3GMIITXER (emio_enet3_gmii_tx_er),
.EMIOENET3MDIOMDC (emio_enet3_mdio_mdc),
.EMIOENET3MDIOI (emio_enet3_mdio_i),
.EMIOENET3MDIOO (emio_enet3_mdio_o),
.EMIOENET3MDIOTN (emio_enet3_mdio_tri),
.EMIOENET0TXRDATARDY (emio_enet0_tx_r_data_rdy),
.EMIOENET0TXRRD (emio_enet0_tx_r_rd),
.EMIOENET0TXRVALID (emio_enet0_tx_r_valid),
.EMIOENET0TXRDATA (emio_enet0_tx_r_data),
.EMIOENET0TXRSOP (emio_enet0_tx_r_sop),
.EMIOENET0TXREOP (emio_enet0_tx_r_eop),
.EMIOENET0TXRERR (emio_enet0_tx_r_err),
.EMIOENET0TXRUNDERFLOW (emio_enet0_tx_r_underflow),
.EMIOENET0TXRFLUSHED (emio_enet0_tx_r_flushed),
.EMIOENET0TXRCONTROL (emio_enet0_tx_r_control),
.EMIOENET0DMATXENDTOG (emio_enet0_dma_tx_end_tog),
.EMIOENET0DMATXSTATUSTOG (emio_enet0_dma_tx_status_tog),
.EMIOENET0TXRSTATUS (emio_enet0_tx_r_status),
.EMIOENET0RXWWR (emio_enet0_rx_w_wr),
.EMIOENET0RXWDATA (emio_enet0_rx_w_data),
.EMIOENET0RXWSOP (emio_enet0_rx_w_sop),
.EMIOENET0RXWEOP (emio_enet0_rx_w_eop),
.EMIOENET0RXWSTATUS (emio_enet0_rx_w_status),
.EMIOENET0RXWERR (emio_enet0_rx_w_err),
.EMIOENET0RXWOVERFLOW (emio_enet0_rx_w_overflow),
.FMIOGEM0SIGNALDETECT (emio_enet0_signal_detect),
.EMIOENET0RXWFLUSH (emio_enet0_rx_w_flush),
.EMIOGEM0TXRFIXEDLAT (emio_enet0_tx_r_fixed_lat),
.FMIOGEM0FIFOTXCLKFROMPL (fmio_gem0_fifo_tx_clk),
.FMIOGEM0FIFORXCLKFROMPL (fmio_gem0_fifo_rx_clk),
.FMIOGEM0FIFOTXCLKTOPLBUFG (fmio_gem0_fifo_tx_clk_temp),
.FMIOGEM0FIFORXCLKTOPLBUFG (fmio_gem0_fifo_rx_clk_temp),
.EMIOENET1TXRDATARDY (emio_enet1_tx_r_data_rdy),
.EMIOENET1TXRRD (emio_enet1_tx_r_rd),
.EMIOENET1TXRVALID (emio_enet1_tx_r_valid),
.EMIOENET1TXRDATA (emio_enet1_tx_r_data),
.EMIOENET1TXRSOP (emio_enet1_tx_r_sop),
.EMIOENET1TXREOP (emio_enet1_tx_r_eop),
.EMIOENET1TXRERR (emio_enet1_tx_r_err),
.EMIOENET1TXRUNDERFLOW (emio_enet1_tx_r_underflow),
.EMIOENET1TXRFLUSHED (emio_enet1_tx_r_flushed),
.EMIOENET1TXRCONTROL (emio_enet1_tx_r_control),
.EMIOENET1DMATXENDTOG (emio_enet1_dma_tx_end_tog),
.EMIOENET1DMATXSTATUSTOG (emio_enet1_dma_tx_status_tog),
.EMIOENET1TXRSTATUS (emio_enet1_tx_r_status),
.EMIOENET1RXWWR (emio_enet1_rx_w_wr),
.EMIOENET1RXWDATA (emio_enet1_rx_w_data),
.EMIOENET1RXWSOP (emio_enet1_rx_w_sop),
.EMIOENET1RXWEOP (emio_enet1_rx_w_eop),
.EMIOENET1RXWSTATUS (emio_enet1_rx_w_status),
.EMIOENET1RXWERR (emio_enet1_rx_w_err),
.EMIOENET1RXWOVERFLOW (emio_enet1_rx_w_overflow),
.FMIOGEM1SIGNALDETECT (emio_enet1_signal_detect),
.EMIOENET1RXWFLUSH (emio_enet1_rx_w_flush),
.EMIOGEM1TXRFIXEDLAT (emio_enet1_tx_r_fixed_lat),
.FMIOGEM1FIFOTXCLKFROMPL (fmio_gem1_fifo_tx_clk),
.FMIOGEM1FIFORXCLKFROMPL (fmio_gem1_fifo_rx_clk),
.FMIOGEM1FIFOTXCLKTOPLBUFG (fmio_gem1_fifo_tx_clk_temp),
.FMIOGEM1FIFORXCLKTOPLBUFG (fmio_gem1_fifo_rx_clk_temp),
.EMIOENET2TXRDATARDY (emio_enet2_tx_r_data_rdy),
.EMIOENET2TXRRD (emio_enet2_tx_r_rd),
.EMIOENET2TXRVALID (emio_enet2_tx_r_valid),
.EMIOENET2TXRDATA (emio_enet2_tx_r_data),
.EMIOENET2TXRSOP (emio_enet2_tx_r_sop),
.EMIOENET2TXREOP (emio_enet2_tx_r_eop),
.EMIOENET2TXRERR (emio_enet2_tx_r_err),
.EMIOENET2TXRUNDERFLOW (emio_enet2_tx_r_underflow),
.EMIOENET2TXRFLUSHED (emio_enet2_tx_r_flushed),
.EMIOENET2TXRCONTROL (emio_enet2_tx_r_control),
.EMIOENET2DMATXENDTOG (emio_enet2_dma_tx_end_tog),
.EMIOENET2DMATXSTATUSTOG (emio_enet2_dma_tx_status_tog),
.EMIOENET2TXRSTATUS (emio_enet2_tx_r_status),
.EMIOENET2RXWWR (emio_enet2_rx_w_wr),
.EMIOENET2RXWDATA (emio_enet2_rx_w_data),
.EMIOENET2RXWSOP (emio_enet2_rx_w_sop),
.EMIOENET2RXWEOP (emio_enet2_rx_w_eop),
.EMIOENET2RXWSTATUS (emio_enet2_rx_w_status),
.EMIOENET2RXWERR (emio_enet2_rx_w_err),
.EMIOENET2RXWOVERFLOW (emio_enet2_rx_w_overflow),
.FMIOGEM2SIGNALDETECT (emio_enet2_signal_detect),
.EMIOENET2RXWFLUSH (emio_enet2_rx_w_flush),
.EMIOGEM2TXRFIXEDLAT (emio_enet2_tx_r_fixed_lat),
.FMIOGEM2FIFOTXCLKFROMPL (fmio_gem2_fifo_tx_clk),
.FMIOGEM2FIFORXCLKFROMPL (fmio_gem2_fifo_rx_clk),
.FMIOGEM2FIFOTXCLKTOPLBUFG (fmio_gem2_fifo_tx_clk_temp),
.FMIOGEM2FIFORXCLKTOPLBUFG (fmio_gem2_fifo_rx_clk_temp),
.EMIOENET3TXRDATARDY (emio_enet3_tx_r_data_rdy),
.EMIOENET3TXRRD (emio_enet3_tx_r_rd),
.EMIOENET3TXRVALID (emio_enet3_tx_r_valid),
.EMIOENET3TXRDATA (emio_enet3_tx_r_data),
.EMIOENET3TXRSOP (emio_enet3_tx_r_sop),
.EMIOENET3TXREOP (emio_enet3_tx_r_eop),
.EMIOENET3TXRERR (emio_enet3_tx_r_err),
.EMIOENET3TXRUNDERFLOW (emio_enet3_tx_r_underflow),
.EMIOENET3TXRFLUSHED (emio_enet3_tx_r_flushed),
.EMIOENET3TXRCONTROL (emio_enet3_tx_r_control),
.EMIOENET3DMATXENDTOG (emio_enet3_dma_tx_end_tog),
.EMIOENET3DMATXSTATUSTOG (emio_enet3_dma_tx_status_tog),
.EMIOENET3TXRSTATUS (emio_enet3_tx_r_status),
.EMIOENET3RXWWR (emio_enet3_rx_w_wr),
.EMIOENET3RXWDATA (emio_enet3_rx_w_data),
.EMIOENET3RXWSOP (emio_enet3_rx_w_sop),
.EMIOENET3RXWEOP (emio_enet3_rx_w_eop),
.EMIOENET3RXWSTATUS (emio_enet3_rx_w_status),
.EMIOENET3RXWERR (emio_enet3_rx_w_err),
.EMIOENET3RXWOVERFLOW (emio_enet3_rx_w_overflow),
.FMIOGEM3SIGNALDETECT (emio_enet3_signal_detect),
.EMIOENET3RXWFLUSH (emio_enet3_rx_w_flush),
.EMIOGEM3TXRFIXEDLAT (emio_enet3_tx_r_fixed_lat),
.FMIOGEM3FIFOTXCLKFROMPL (fmio_gem3_fifo_tx_clk),
.FMIOGEM3FIFORXCLKFROMPL (fmio_gem3_fifo_rx_clk),
.FMIOGEM3FIFOTXCLKTOPLBUFG (fmio_gem3_fifo_tx_clk_temp),
.FMIOGEM3FIFORXCLKTOPLBUFG (fmio_gem3_fifo_rx_clk_temp),
.EMIOGEM0TXSOF (emio_enet0_tx_sof),
.EMIOGEM0SYNCFRAMETX (emio_enet0_sync_frame_tx),
.EMIOGEM0DELAYREQTX (emio_enet0_delay_req_tx),
.EMIOGEM0PDELAYREQTX (emio_enet0_pdelay_req_tx),
.EMIOGEM0PDELAYRESPTX (emio_enet0_pdelay_resp_tx),
.EMIOGEM0RXSOF (emio_enet0_rx_sof),
.EMIOGEM0SYNCFRAMERX (emio_enet0_sync_frame_rx),
.EMIOGEM0DELAYREQRX (emio_enet0_delay_req_rx),
.EMIOGEM0PDELAYREQRX (emio_enet0_pdelay_req_rx),
.EMIOGEM0PDELAYRESPRX (emio_enet0_pdelay_resp_rx),
.EMIOGEM0TSUINCCTRL (emio_enet0_tsu_inc_ctrl),
.EMIOGEM0TSUTIMERCMPVAL (emio_enet0_tsu_timer_cmp_val),
.EMIOGEM1TXSOF (emio_enet1_tx_sof),
.EMIOGEM1SYNCFRAMETX (emio_enet1_sync_frame_tx),
.EMIOGEM1DELAYREQTX (emio_enet1_delay_req_tx),
.EMIOGEM1PDELAYREQTX (emio_enet1_pdelay_req_tx),
.EMIOGEM1PDELAYRESPTX (emio_enet1_pdelay_resp_tx),
.EMIOGEM1RXSOF (emio_enet1_rx_sof),
.EMIOGEM1SYNCFRAMERX (emio_enet1_sync_frame_rx),
.EMIOGEM1DELAYREQRX (emio_enet1_delay_req_rx),
.EMIOGEM1PDELAYREQRX (emio_enet1_pdelay_req_rx),
.EMIOGEM1PDELAYRESPRX (emio_enet1_pdelay_resp_rx),
.EMIOGEM1TSUINCCTRL (emio_enet1_tsu_inc_ctrl),
.EMIOGEM1TSUTIMERCMPVAL (emio_enet1_tsu_timer_cmp_val),
.EMIOGEM2TXSOF (emio_enet2_tx_sof),
.EMIOGEM2SYNCFRAMETX (emio_enet2_sync_frame_tx),
.EMIOGEM2DELAYREQTX (emio_enet2_delay_req_tx),
.EMIOGEM2PDELAYREQTX (emio_enet2_pdelay_req_tx),
.EMIOGEM2PDELAYRESPTX (emio_enet2_pdelay_resp_tx),
.EMIOGEM2RXSOF (emio_enet2_rx_sof),
.EMIOGEM2SYNCFRAMERX (emio_enet2_sync_frame_rx),
.EMIOGEM2DELAYREQRX (emio_enet2_delay_req_rx),
.EMIOGEM2PDELAYREQRX (emio_enet2_pdelay_req_rx),
.EMIOGEM2PDELAYRESPRX (emio_enet2_pdelay_resp_rx),
.EMIOGEM2TSUINCCTRL (emio_enet2_tsu_inc_ctrl),
.EMIOGEM2TSUTIMERCMPVAL (emio_enet2_tsu_timer_cmp_val),
.EMIOGEM3TXSOF (emio_enet3_tx_sof),
.EMIOGEM3SYNCFRAMETX (emio_enet3_sync_frame_tx),
.EMIOGEM3DELAYREQTX (emio_enet3_delay_req_tx),
.EMIOGEM3PDELAYREQTX (emio_enet3_pdelay_req_tx),
.EMIOGEM3PDELAYRESPTX (emio_enet3_pdelay_resp_tx),
.EMIOGEM3RXSOF (emio_enet3_rx_sof),
.EMIOGEM3SYNCFRAMERX (emio_enet3_sync_frame_rx),
.EMIOGEM3DELAYREQRX (emio_enet3_delay_req_rx),
.EMIOGEM3PDELAYREQRX (emio_enet3_pdelay_req_rx),
.EMIOGEM3PDELAYRESPRX (emio_enet3_pdelay_resp_rx),
.EMIOGEM3TSUINCCTRL (emio_enet3_tsu_inc_ctrl),
.EMIOGEM3TSUTIMERCMPVAL (emio_enet3_tsu_timer_cmp_val),
.FMIOGEMTSUCLKFROMPL (fmio_gem_tsu_clk_from_pl),
.FMIOGEMTSUCLKTOPLBUFG (fmio_gem_tsu_clk_to_pl_bufg),
.EMIOENETTSUCLK (emio_enet_tsu_clk),
.EMIOENET0GEMTSUTIMERCNT (emio_enet0_enet_tsu_timer_cnt),
.EMIOENET0EXTINTIN (emio_enet0_ext_int_in),
.EMIOENET1EXTINTIN (emio_enet1_ext_int_in),
.EMIOENET2EXTINTIN (emio_enet2_ext_int_in),
.EMIOENET3EXTINTIN (emio_enet3_ext_int_in),
.EMIOENET0DMABUSWIDTH (emio_enet0_dma_bus_width),
.EMIOENET1DMABUSWIDTH (emio_enet1_dma_bus_width),
.EMIOENET2DMABUSWIDTH (emio_enet2_dma_bus_width),
.EMIOENET3DMABUSWIDTH (emio_enet3_dma_bus_width),
.EMIOGPIOI (emio_gpio_i_temp),
.EMIOGPIOO (emio_gpio_o_temp),
.EMIOGPIOTN (emio_gpio_t_temp),
.EMIOI2C0SCLI (emio_i2c0_scl_i),
.EMIOI2C0SCLO (emio_i2c0_scl_o),
.EMIOI2C0SCLTN (emio_i2c0_scl_tri),
.EMIOI2C0SDAI (emio_i2c0_sda_i),
.EMIOI2C0SDAO (emio_i2c0_sda_o),
.EMIOI2C0SDATN (emio_i2c0_sda_tri),
.EMIOI2C1SCLI (emio_i2c1_scl_i),
.EMIOI2C1SCLO (emio_i2c1_scl_o),
.EMIOI2C1SCLTN (emio_i2c1_scl_tri),
.EMIOI2C1SDAI (emio_i2c1_sda_i),
.EMIOI2C1SDAO (emio_i2c1_sda_o),
.EMIOI2C1SDATN (emio_i2c1_sda_tri),
.EMIOUART0TX (emio_uart0_txd),
.EMIOUART0RX (emio_uart0_rxd),
.EMIOUART0CTSN (emio_uart0_ctsn),
.EMIOUART0RTSN (emio_uart0_rtsn),
.EMIOUART0DSRN (emio_uart0_dsrn),
.EMIOUART0DCDN (emio_uart0_dcdn),
.EMIOUART0RIN (emio_uart0_rin),
.EMIOUART0DTRN (emio_uart0_dtrn),
.EMIOUART1TX (emio_uart1_txd),
.EMIOUART1RX (emio_uart1_rxd),
.EMIOUART1CTSN (emio_uart1_ctsn),
.EMIOUART1RTSN (emio_uart1_rtsn),
.EMIOUART1DSRN (emio_uart1_dsrn),
.EMIOUART1DCDN (emio_uart1_dcdn),
.EMIOUART1RIN (emio_uart1_rin),
.EMIOUART1DTRN (emio_uart1_dtrn),
.EMIOSDIO0CLKOUT (emio_sdio0_clkout),
.EMIOSDIO0FBCLKIN (emio_sdio0_fb_clk_in),
.EMIOSDIO0CMDOUT (emio_sdio0_cmdout),
.EMIOSDIO0CMDIN (emio_sdio0_cmdin),
.EMIOSDIO0CMDENA (emio_sdio0_cmdena_i),
.EMIOSDIO0DATAIN (emio_sdio0_datain),
.EMIOSDIO0DATAOUT (emio_sdio0_dataout),
.EMIOSDIO0DATAENA (emio_sdio0_dataena_i),
.EMIOSDIO0CDN (emio_sdio0_cd_n),
.EMIOSDIO0WP (emio_sdio0_wp),
.EMIOSDIO0LEDCONTROL (emio_sdio0_ledcontrol),
.EMIOSDIO0BUSPOWER (emio_sdio0_buspower),
.EMIOSDIO0BUSVOLT (emio_sdio0_bus_volt),
.EMIOSDIO1CLKOUT (emio_sdio1_clkout),
.EMIOSDIO1FBCLKIN (emio_sdio1_fb_clk_in),
.EMIOSDIO1CMDOUT (emio_sdio1_cmdout),
.EMIOSDIO1CMDIN (emio_sdio1_cmdin),
.EMIOSDIO1CMDENA (emio_sdio1_cmdena_i),
.EMIOSDIO1DATAIN (emio_sdio1_datain),
.EMIOSDIO1DATAOUT (emio_sdio1_dataout),
.EMIOSDIO1DATAENA (emio_sdio1_dataena_i),
.EMIOSDIO1CDN (emio_sdio1_cd_n),
.EMIOSDIO1WP (emio_sdio1_wp),
.EMIOSDIO1LEDCONTROL (emio_sdio1_ledcontrol),
.EMIOSDIO1BUSPOWER (emio_sdio1_buspower),
.EMIOSDIO1BUSVOLT (emio_sdio1_bus_volt),
.EMIOSPI0SCLKI (emio_spi0_sclk_i),
.EMIOSPI0SCLKO (emio_spi0_sclk_o),
.EMIOSPI0SCLKTN (emio_spi0_sclk_tri),
.EMIOSPI0MI (emio_spi0_m_i),
.EMIOSPI0MO (emio_spi0_m_o),
.EMIOSPI0MOTN (emio_spi0_mo_tri),
.EMIOSPI0SI (emio_spi0_s_i),
.EMIOSPI0SO (emio_spi0_s_o),
.EMIOSPI0STN (emio_spi0_so_tri),
.EMIOSPI0SSIN (emio_spi0_ss_i_n),
.EMIOSPI0SSON ({emio_spi0_ss2_o_n,emio_spi0_ss1_o_n,emio_spi0_ss_o_n}),
.EMIOSPI0SSNTN (emio_spi0_ss_n_tri),
.EMIOSPI1SCLKI (emio_spi1_sclk_i),
.EMIOSPI1SCLKO (emio_spi1_sclk_o),
.EMIOSPI1SCLKTN (emio_spi1_sclk_tri),
.EMIOSPI1MI (emio_spi1_m_i),
.EMIOSPI1MO (emio_spi1_m_o),
.EMIOSPI1MOTN (emio_spi1_mo_tri),
.EMIOSPI1SI (emio_spi1_s_i),
.EMIOSPI1SO (emio_spi1_s_o),
.EMIOSPI1STN (emio_spi1_so_tri),
.EMIOSPI1SSIN (emio_spi1_ss_i_n),
.EMIOSPI1SSON ({emio_spi1_ss2_o_n,emio_spi1_ss1_o_n,emio_spi1_ss_o_n}),
.EMIOSPI1SSNTN (emio_spi1_ss_n_tri),
.PLPSTRACECLK (pl_ps_trace_clk),
.PSPLTRACECTL (trace_ctl_i),
.PSPLTRACEDATA (trace_data_i),
.EMIOTTC0WAVEO (emio_ttc0_wave_o),
.EMIOTTC0CLKI (emio_ttc0_clk_i),
.EMIOTTC1WAVEO (emio_ttc1_wave_o),
.EMIOTTC1CLKI (emio_ttc1_clk_i),
.EMIOTTC2WAVEO (emio_ttc2_wave_o),
.EMIOTTC2CLKI (emio_ttc2_clk_i),
.EMIOTTC3WAVEO (emio_ttc3_wave_o),
.EMIOTTC3CLKI (emio_ttc3_clk_i),
.EMIOWDT0CLKI (emio_wdt0_clk_i),
.EMIOWDT0RSTO (emio_wdt0_rst_o),
.EMIOWDT1CLKI (emio_wdt1_clk_i),
.EMIOWDT1RSTO (emio_wdt1_rst_o),
.EMIOHUBPORTOVERCRNTUSB30 (emio_hub_port_overcrnt_usb3_0),
.EMIOHUBPORTOVERCRNTUSB31 (emio_hub_port_overcrnt_usb3_1),
.EMIOHUBPORTOVERCRNTUSB20 (emio_hub_port_overcrnt_usb2_0),
.EMIOHUBPORTOVERCRNTUSB21 (emio_hub_port_overcrnt_usb2_1),
.EMIOU2DSPORTVBUSCTRLUSB30 (emio_u2dsport_vbus_ctrl_usb3_0),
.EMIOU2DSPORTVBUSCTRLUSB31 (emio_u2dsport_vbus_ctrl_usb3_1),
.EMIOU3DSPORTVBUSCTRLUSB30 (emio_u3dsport_vbus_ctrl_usb3_0),
.EMIOU3DSPORTVBUSCTRLUSB31 (emio_u3dsport_vbus_ctrl_usb3_1),
.ADMAFCICLK (adma_fci_clk),
.PL2ADMACVLD (pl2adma_cvld),
.PL2ADMATACK (pl2adma_tack),
.ADMA2PLCACK (adma2pl_cack),
.ADMA2PLTVLD (adma2pl_tvld),
.GDMAFCICLK (perif_gdma_clk),
.PL2GDMACVLD (perif_gdma_cvld),
.PL2GDMATACK (perif_gdma_tack),
.GDMA2PLCACK (gdma_perif_cack),
.GDMA2PLTVLD (gdma_perif_tvld),
.PLFPGASTOP (pl_clock_stop),
.PLLAUXREFCLKLPD (pll_aux_refclk_lpd),
.PLLAUXREFCLKFPD (pll_aux_refclk_fpd),
.DPSAXISAUDIOTDATA (dp_s_axis_audio_tdata),
.DPSAXISAUDIOTID (dp_s_axis_audio_tid),
.DPSAXISAUDIOTVALID (dp_s_axis_audio_tvalid),
.DPSAXISAUDIOTREADY (dp_s_axis_audio_tready),
.DPMAXISMIXEDAUDIOTDATA (dp_m_axis_mixed_audio_tdata),
.DPMAXISMIXEDAUDIOTID (dp_m_axis_mixed_audio_tid),
.DPMAXISMIXEDAUDIOTVALID (dp_m_axis_mixed_audio_tvalid),
.DPMAXISMIXEDAUDIOTREADY (dp_m_axis_mixed_audio_tready),
.DPSAXISAUDIOCLK (dp_s_axis_audio_clk),
.DPLIVEVIDEOINVSYNC (dp_live_video_in_vsync),
.DPLIVEVIDEOINHSYNC (dp_live_video_in_hsync),
.DPLIVEVIDEOINDE (dp_live_video_in_de),
.DPLIVEVIDEOINPIXEL1 (dp_live_video_in_pixel1),
.DPVIDEOINCLK (dp_video_in_clk),
.DPVIDEOOUTHSYNC (dp_video_out_hsync),
.DPVIDEOOUTVSYNC (dp_video_out_vsync),
.DPVIDEOOUTPIXEL1 (dp_video_out_pixel1),
.DPAUXDATAIN (dp_aux_data_in),
.DPAUXDATAOUT (dp_aux_data_out),
.DPAUXDATAOEN (dp_aux_data_oe_n),
.DPLIVEGFXALPHAIN (dp_live_gfx_alpha_in),
.DPLIVEGFXPIXEL1IN (dp_live_gfx_pixel1_in),
.DPHOTPLUGDETECT (dp_hot_plug_detect),
.DPEXTERNALCUSTOMEVENT1 (dp_external_custom_event1),
.DPEXTERNALCUSTOMEVENT2 (dp_external_custom_event2),
.DPEXTERNALVSYNCEVENT (dp_external_vsync_event),
.DPLIVEVIDEODEOUT (dp_live_video_de_out),
.PLPSEVENTI (pl_ps_eventi),
.PSPLEVENTO (ps_pl_evento),
.PSPLSTANDBYWFE (ps_pl_standbywfe),
.PSPLSTANDBYWFI (ps_pl_standbywfi),
.PLPSAPUGICIRQ (pl_ps_apugic_irq),
.PLPSAPUGICFIQ (pl_ps_apugic_fiq),
.RPUEVENTI0 (rpu_eventi0),
.RPUEVENTI1 (rpu_eventi1),
.RPUEVENTO0 (rpu_evento0),
.RPUEVENTO1 (rpu_evento1),
.NFIQ0LPDRPU (nfiq0_lpd_rpu),
.NFIQ1LPDRPU (nfiq1_lpd_rpu),
.NIRQ0LPDRPU (nirq0_lpd_rpu),
.NIRQ1LPDRPU (nirq1_lpd_rpu),
.STMEVENT (stm_event),
.PLPSTRIGACK ({pl_ps_trigack_3, pl_ps_trigack_2, pl_ps_trigack_1, pl_ps_trigack_0}),
.PLPSTRIGGER ({pl_ps_trigger_3, pl_ps_trigger_2, pl_ps_trigger_1, pl_ps_trigger_0}),
.PSPLTRIGACK ({ps_pl_trigack_3, ps_pl_trigack_2, ps_pl_trigack_1, ps_pl_trigack_0}),
.PSPLTRIGGER ({ps_pl_trigger_3, ps_pl_trigger_2, ps_pl_trigger_1, ps_pl_trigger_0}),
.FTMGPO (ftm_gpo),
.FTMGPI (ftm_gpi),
.PLPSIRQ0 (irq_f2p_0_i),
.PLPSIRQ1 (irq_f2p_1_i),
.PSPLIRQLPD ({ps_pl_irq_lpd_low[18:8], ps_pl_irq_xmpu_lpd, ps_pl_irq_efuse, ps_pl_irq_csu_dma, ps_pl_irq_csu, ps_pl_irq_adma_chan, ps_pl_irq_usb3_0_pmu_wakeup, ps_pl_irq_usb3_1_otg, ps_pl_irq_usb3_1_endpoint, ps_pl_irq_usb3_0_otg, ps_pl_irq_usb3_0_endpoint, ps_pl_irq_enet3_wake, ps_pl_irq_enet3, ps_pl_irq_enet2_wake, ps_pl_irq_enet2, ps_pl_irq_enet1_wake, ps_pl_irq_enet1, ps_pl_irq_enet0_wake, ps_pl_irq_enet0, ps_pl_irq_ams, ps_pl_irq_aib_axi, ps_pl_irq_atb_err_lpd, ps_pl_irq_csu_pmu_wdt, ps_pl_irq_lp_wdt, ps_pl_irq_sdio1_wake, ps_pl_irq_sdio0_wake, ps_pl_irq_sdio1, ps_pl_irq_sdio0, ps_pl_irq_ttc3_2, ps_pl_irq_ttc3_1, ps_pl_irq_ttc3_0, ps_pl_irq_ttc2_2, ps_pl_irq_ttc2_1, ps_pl_irq_ttc2_0, ps_pl_irq_ttc1_2, ps_pl_irq_ttc1_1, ps_pl_irq_ttc1_0, ps_pl_irq_ttc0_2, ps_pl_irq_ttc0_1, ps_pl_irq_ttc0_0, ps_pl_irq_ipi_channel0, ps_pl_irq_ipi_channel1, ps_pl_irq_ipi_channel2, ps_pl_irq_ipi_channel10, ps_pl_irq_ipi_channel9, ps_pl_irq_ipi_channel8, ps_pl_irq_ipi_channel7, ps_pl_irq_clkmon, ps_pl_irq_rtc_seconds, ps_pl_irq_rtc_alaram, ps_pl_irq_lpd_apm, ps_pl_irq_can1, ps_pl_irq_can0, ps_pl_irq_uart1, ps_pl_irq_uart0, ps_pl_irq_spi1, ps_pl_irq_spi0, ps_pl_irq_i2c1, ps_pl_irq_i2c0, ps_pl_irq_gpio, ps_pl_irq_qspi, ps_pl_irq_nand, ps_pl_irq_r5_core1_ecc_error, ps_pl_irq_r5_core0_ecc_error, ps_pl_irq_lpd_apb_intr, ps_pl_irq_ocm_error, ps_pl_irq_rpu_pm, ps_pl_irq_lpd_low[7:0]}),
.PSPLIRQFPD ({ps_pl_irq_fpd_low[19:12], ps_pl_irq_intf_fpd_smmu, ps_pl_irq_intf_ppd_cci, ps_pl_irq_apu_regs, ps_pl_irq_apu_exterr, ps_pl_irq_apu_l2err, ps_pl_irq_apu_comm, ps_pl_irq_apu_pmu, ps_pl_irq_apu_cti, ps_pl_irq_apu_cpumnt, ps_pl_irq_xmpu_fpd, ps_pl_irq_sata, ps_pl_irq_gpu, ps_pl_irq_gdma_chan, ps_pl_irq_apm_fpd, ps_pl_irq_dpdma, ps_pl_irq_fpd_atb_error, ps_pl_irq_fpd_apb_int, ps_pl_irq_dport, ps_pl_irq_pcie_msc, ps_pl_irq_pcie_dma, ps_pl_irq_pcie_legacy, ps_pl_irq_pcie_msi, ps_pl_irq_fp_wdt, ps_pl_irq_ddr_ss, ps_pl_irq_fpd_low[11:0]}),
.OSCRTCCLK (osc_rtc_clk),
.PLPMUGPI (pl_pmu_gpi),
.PMUPLGPO (pmu_pl_gpo),
.AIBPMUAFIFMFPDACK (aib_pmu_afifm_fpd_ack),
.AIBPMUAFIFMLPDACK (aib_pmu_afifm_lpd_ack),
.PMUAIBAFIFMFPDREQ (pmu_aib_afifm_fpd_req),
.PMUAIBAFIFMLPDREQ (pmu_aib_afifm_lpd_req),
.PMUERRORTOPL (pmu_error_to_pl),
.PMUERRORFROMPL (pmu_error_from_pl),
.DDRCEXTREFRESHRANK0REQ (ddrc_ext_refresh_rank0_req),
.DDRCEXTREFRESHRANK1REQ (ddrc_ext_refresh_rank1_req),
.DDRCREFRESHPLCLK (ddrc_refresh_pl_clk),
.PLACPINACT (pl_acpinact),
.PLCLK (pl_clk_unbuffered),
.DPVIDEOREFCLK(dp_video_ref_clk_i),
.DPAUDIOREFCLK(dp_audio_ref_clk_i)
);
assign test_db = 16'h0000;
assign test_adc_out = 20'h00000;
assign test_ams_osc = 8'h00;
assign test_mon_data = 16'h0000;
assign test_drdy = 1'b0;
assign test_do = 16'h0000;
assign pstp_pl_out = 32'h00000000;
assign fmio_test_io_char_scan_out = 1'b0;
assign fmio_char_afifslpd_test_output = 1'b0;
assign fmio_char_afifsfpd_test_output = 1'b0;
assign io_char_video_out_test_data = 1'b0;
assign io_char_audio_out_test_data = 1'b0;
assign fmio_sd0_dll_test_out = 8'h00;
assign fmio_sd1_dll_test_out = 8'h00;
assign test_pl_scan_chopper_so = 1'b0;
assign test_pl_scan_edt_out_apu = 1'b0;
assign test_pl_scan_edt_out_cpu0 = 1'b0;
assign test_pl_scan_edt_out_cpu1 = 1'b0;
assign test_pl_scan_edt_out_cpu2 = 1'b0;
assign test_pl_scan_edt_out_cpu3 = 1'b0;
assign test_pl_scan_edt_out_ddr = 4'h0;
assign test_pl_scan_edt_out_fp = 10'b0000000000;
assign test_pl_scan_edt_out_gpu = 4'h0;
assign test_pl_scan_edt_out_lp = 9'b000000000;
assign test_pl_scan_edt_out_usb3 = 2'b00;
assign test_pl_scan_spare_out0 = 1'b0;
assign test_pl_scan_spare_out1 = 1'b0;
assign test_pl_pll_lock_out = 5'b00000;
assign test_pl_scan_slcr_config_so = 1'b0;
assign tst_rtc_calibreg_out = 21'b000000000000000000000;
assign tst_rtc_osc_clk_out = 1'b0;
assign tst_rtc_sec_counter_out = 32'h00000000;
assign tst_rtc_seconds_raw_int = 1'b0;
assign tst_rtc_tick_counter_out = 16'h0000;
assign tst_rtc_timesetreg_out = 32'h00000000;
assign tst_rtc_osc_cntrl_out = 4'h0;
assign lpd_pll_test_out = 32'h00000000;
assign fpd_pll_test_out = 32'h00000000;
assign fmio_char_gem_test_output = 1'b0;
assign test_ddr2pl_dcd_skewout = 1'b0;
assign test_bscan_tdo = 1'b0;
assign fpd_pl_spare_0_out = 1'b0;
assign fpd_pl_spare_1_out = 1'b0;
assign fpd_pl_spare_2_out = 1'b0;
assign fpd_pl_spare_3_out = 1'b0;
assign fpd_pl_spare_4_out = 1'b0;
assign lpd_pl_spare_0_out = 1'b0;
assign lpd_pl_spare_1_out = 1'b0;
assign lpd_pl_spare_2_out = 1'b0;
assign lpd_pl_spare_3_out = 1'b0;
assign lpd_pl_spare_4_out = 1'b0;
assign o_dbg_l0_phystatus = 1'b0;
assign o_dbg_l0_rxdata = 20'h00000;
assign o_dbg_l0_rxdatak = 2'b00;
assign o_dbg_l0_rxvalid = 1'b0;
assign o_dbg_l0_rxstatus = 3'b000;
assign o_dbg_l0_rxelecidle = 1'b0;
assign o_dbg_l0_rstb = 1'b0;
assign o_dbg_l0_txdata = 20'h00000;
assign o_dbg_l0_txdatak = 2'b00;
assign o_dbg_l0_rate = 2'b00;
assign o_dbg_l0_powerdown = 2'b00;
assign o_dbg_l0_txelecidle = 1'b0;
assign o_dbg_l0_txdetrx_lpback = 1'b0;
assign o_dbg_l0_rxpolarity = 1'b0;
assign o_dbg_l0_tx_sgmii_ewrap = 1'b0;
assign o_dbg_l0_rx_sgmii_en_cdet = 1'b0;
assign o_dbg_l0_sata_corerxdata = 20'h00000;
assign o_dbg_l0_sata_corerxdatavalid = 2'b00;
assign o_dbg_l0_sata_coreready = 1'b0;
assign o_dbg_l0_sata_coreclockready = 1'b0;
assign o_dbg_l0_sata_corerxsignaldet = 1'b0;
assign o_dbg_l0_sata_phyctrltxdata = 20'h00000;
assign o_dbg_l0_sata_phyctrltxidle = 1'b0;
assign o_dbg_l0_sata_phyctrltxrate = 2'b00;
assign o_dbg_l0_sata_phyctrlrxrate = 2'b00;
assign o_dbg_l0_sata_phyctrltxrst = 1'b0;
assign o_dbg_l0_sata_phyctrlrxrst = 1'b0;
assign o_dbg_l0_sata_phyctrlreset = 1'b0;
assign o_dbg_l0_sata_phyctrlpartial = 1'b0;
assign o_dbg_l0_sata_phyctrlslumber = 1'b0;
assign o_dbg_l1_phystatus = 1'b0;
assign o_dbg_l1_rxdata = 20'h00000;
assign o_dbg_l1_rxdatak = 2'b00;
assign o_dbg_l1_rxvalid = 1'b0;
assign o_dbg_l1_rxstatus = 3'b000;
assign o_dbg_l1_rxelecidle = 1'b0;
assign o_dbg_l1_rstb = 1'b0;
assign o_dbg_l1_txdata = 20'h00000;
assign o_dbg_l1_txdatak = 2'b00;
assign o_dbg_l1_rate = 2'b00;
assign o_dbg_l1_powerdown = 2'b00;
assign o_dbg_l1_txelecidle = 1'b0;
assign o_dbg_l1_txdetrx_lpback = 1'b0;
assign o_dbg_l1_rxpolarity = 1'b0;
assign o_dbg_l1_tx_sgmii_ewrap = 1'b0;
assign o_dbg_l1_rx_sgmii_en_cdet = 1'b0;
assign o_dbg_l1_sata_corerxdata = 20'h00000;
assign o_dbg_l1_sata_corerxdatavalid = 2'b00;
assign o_dbg_l1_sata_coreready = 1'b0;
assign o_dbg_l1_sata_coreclockready = 1'b0;
assign o_dbg_l1_sata_corerxsignaldet = 1'b0;
assign o_dbg_l1_sata_phyctrltxdata = 20'h00000;
assign o_dbg_l1_sata_phyctrltxidle = 1'b0;
assign o_dbg_l1_sata_phyctrltxrate = 2'b00;
assign o_dbg_l1_sata_phyctrlrxrate = 2'b00;
assign o_dbg_l1_sata_phyctrltxrst = 1'b0;
assign o_dbg_l1_sata_phyctrlrxrst = 1'b0;
assign o_dbg_l1_sata_phyctrlreset = 1'b0;
assign o_dbg_l1_sata_phyctrlpartial = 1'b0;
assign o_dbg_l1_sata_phyctrlslumber = 1'b0;
assign o_dbg_l2_phystatus = 1'b0;
assign o_dbg_l2_rxdata = 20'h00000;
assign o_dbg_l2_rxdatak = 2'b00;
assign o_dbg_l2_rxvalid = 1'b0;
assign o_dbg_l2_rxstatus = 3'b000;
assign o_dbg_l2_rxelecidle = 1'b0;
assign o_dbg_l2_rstb = 1'b0;
assign o_dbg_l2_txdata = 20'h00000;
assign o_dbg_l2_txdatak = 2'b00;
assign o_dbg_l2_rate = 2'b00;
assign o_dbg_l2_powerdown = 2'b00;
assign o_dbg_l2_txelecidle = 1'b0;
assign o_dbg_l2_txdetrx_lpback = 1'b0;
assign o_dbg_l2_rxpolarity = 1'b0;
assign o_dbg_l2_tx_sgmii_ewrap = 1'b0;
assign o_dbg_l2_rx_sgmii_en_cdet = 1'b0;
assign o_dbg_l2_sata_corerxdata = 20'h00000;
assign o_dbg_l2_sata_corerxdatavalid = 2'b00;
assign o_dbg_l2_sata_coreready = 1'b0;
assign o_dbg_l2_sata_coreclockready = 1'b0;
assign o_dbg_l2_sata_corerxsignaldet = 1'b0;
assign o_dbg_l2_sata_phyctrltxdata = 20'h00000;
assign o_dbg_l2_sata_phyctrltxidle = 1'b0;
assign o_dbg_l2_sata_phyctrltxrate = 2'b00;
assign o_dbg_l2_sata_phyctrlrxrate = 2'b00;
assign o_dbg_l2_sata_phyctrltxrst = 1'b0;
assign o_dbg_l2_sata_phyctrlrxrst = 1'b0;
assign o_dbg_l2_sata_phyctrlreset = 1'b0;
assign o_dbg_l2_sata_phyctrlpartial = 1'b0;
assign o_dbg_l2_sata_phyctrlslumber = 1'b0;
assign o_dbg_l3_phystatus = 1'b0;
assign o_dbg_l3_rxdata = 20'h00000;
assign o_dbg_l3_rxdatak = 2'b00;
assign o_dbg_l3_rxvalid = 1'b0;
assign o_dbg_l3_rxstatus = 3'b000;
assign o_dbg_l3_rxelecidle = 1'b0;
assign o_dbg_l3_rstb = 1'b0;
assign o_dbg_l3_txdata = 20'h00000 ;
assign o_dbg_l3_txdatak = 2'b00;
assign o_dbg_l3_rate = 2'b00;
assign o_dbg_l3_powerdown = 2'b00;
assign o_dbg_l3_txelecidle = 1'b0;
assign o_dbg_l3_txdetrx_lpback = 1'b0;
assign o_dbg_l3_rxpolarity = 1'b0;
assign o_dbg_l3_tx_sgmii_ewrap = 1'b0;
assign o_dbg_l3_rx_sgmii_en_cdet = 1'b0;
assign o_dbg_l3_sata_corerxdata = 20'h00000;
assign o_dbg_l3_sata_corerxdatavalid = 2'b00;
assign o_dbg_l3_sata_coreready = 1'b0;
assign o_dbg_l3_sata_coreclockready = 1'b0;
assign o_dbg_l3_sata_corerxsignaldet = 1'b0;
assign o_dbg_l3_sata_phyctrltxdata = 20'h00000;
assign o_dbg_l3_sata_phyctrltxidle = 1'b0;
assign o_dbg_l3_sata_phyctrltxrate = 2'b00;
assign o_dbg_l3_sata_phyctrlrxrate = 2'b00;
assign o_dbg_l3_sata_phyctrltxrst = 1'b0;
assign o_dbg_l3_sata_phyctrlrxrst = 1'b0;
assign o_dbg_l3_sata_phyctrlreset = 1'b0;
assign o_dbg_l3_sata_phyctrlpartial = 1'b0;
assign o_dbg_l3_sata_phyctrlslumber = 1'b0;
assign dbg_path_fifo_bypass = 1'b0;
assign o_afe_cmn_calib_comp_out = 1'b0;
assign o_afe_pll_dco_count = 13'b0000000000000;
assign o_afe_pll_clk_sym_hs = 1'b0;
assign o_afe_pll_fbclk_frac = 1'b0;
assign o_afe_rx_pipe_lfpsbcn_rxelecidle = 1'b0;
assign o_afe_rx_pipe_sigdet = 1'b0;
assign o_afe_rx_symbol = 20'h00000;
assign o_afe_rx_symbol_clk_by_2 = 1'b0;
assign o_afe_rx_uphy_save_calcode = 1'b0;
assign o_afe_rx_uphy_startloop_buf = 1'b0;
assign o_afe_rx_uphy_rx_calib_done = 1'b0;
assign o_afe_rx_uphy_save_calcode_data = 8'h00;
assign o_afe_rx_hsrx_clock_stop_ack = 1'b0;
assign o_afe_pg_avddcr = 1'b0;
assign o_afe_pg_avddio = 1'b0;
assign o_afe_pg_dvddcr = 1'b0;
assign o_afe_pg_static_avddcr = 1'b0;
assign o_afe_pg_static_avddio = 1'b0;
assign o_afe_TX_dig_reset_rel_ack = 1'b0;
assign o_afe_TX_pipe_TX_dn_rxdet = 1'b0;
assign o_afe_TX_pipe_TX_dp_rxdet = 1'b0;
assign o_dbg_l0_txclk = 1'b0;
assign o_dbg_l0_rxclk = 1'b0;
assign o_dbg_l1_txclk = 1'b0;
assign o_dbg_l1_rxclk = 1'b0;
assign o_dbg_l2_txclk = 1'b0;
assign o_dbg_l2_rxclk = 1'b0;
assign o_dbg_l3_txclk = 1'b0;
assign o_dbg_l3_rxclk = 1'b0;
end
endgenerate
endmodule
9) Synthesis run script generated by Vivado in TCL
#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "/home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1/design2023_1_zynq_ultra_ps_e_0_0.tcl"
variable category "vivado_synth"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
OPTRACE "design2023_1_zynq_ultra_ps_e_0_0_synth_1" START { ROLLUP_AUTO }
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xczu3eg-sbva484-1-e
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir /home/ab/Videos/amd_xilinx/project_1/project_1.cache/wt [current_project]
set_property parent.project_path /home/ab/Videos/amd_xilinx/project_1/project_1.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_output_repo /home/ab/Videos/amd_xilinx/project_1/project_1.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_ip -quiet /home/ab/Videos/amd_xilinx/project_1/project_1.srcs/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0.xci
set_property used_in_implementation false [get_files -all /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
OPTRACE "Configure IP Cache" START { }
set cacheID [config_ip_cache -export -no_bom -dir /home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1 -new_name design2023_1_zynq_ultra_ps_e_0_0 -ip [get_ips design2023_1_zynq_ultra_ps_e_0_0]]
OPTRACE "Configure IP Cache" END { }
if { $cacheID == "" } {
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top design2023_1_zynq_ultra_ps_e_0_0 -part xczu3eg-sbva484-1-e -incremental_mode off -mode out_of_context
OPTRACE "synth_design" END { }
OPTRACE "Write IP Cache" START { }
#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
# disable binary constraint mode for IPCache checkpoints
set_param constraints.enableBinaryConstraints false
catch {
write_checkpoint -force -noxdef -rename_prefix design2023_1_zynq_ultra_ps_e_0_0_ design2023_1_zynq_ultra_ps_e_0_0.dcp
set ipCachedFiles {}
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design2023_1_zynq_ultra_ps_e_0_0_stub.v
lappend ipCachedFiles design2023_1_zynq_ultra_ps_e_0_0_stub.v
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl
lappend ipCachedFiles design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.v
lappend ipCachedFiles design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.v
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.vhdl
lappend ipCachedFiles design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.vhdl
set TIME_taken [expr [clock seconds] - $TIME_start]
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
config_ip_cache -add -dcp design2023_1_zynq_ultra_ps_e_0_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips design2023_1_zynq_ultra_ps_e_0_0]
}
OPTRACE "Write IP Cache" END { }
}
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}
rename_ref -prefix_all design2023_1_zynq_ultra_ps_e_0_0_
OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef design2023_1_zynq_ultra_ps_e_0_0.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "design2023_1_zynq_ultra_ps_e_0_0_synth_1_synth_report_utilization_0" "report_utilization -file design2023_1_zynq_ultra_ps_e_0_0_utilization_synth.rpt -pb design2023_1_zynq_ultra_ps_e_0_0_utilization_synth.pb"
OPTRACE "synth reports" END { }
if { [catch {
file copy -force /home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1/design2023_1_zynq_ultra_ps_e_0_0.dcp /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
} else {
if { [catch {
file copy -force /home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1/design2023_1_zynq_ultra_ps_e_0_0.dcp /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force /home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1/design2023_1_zynq_ultra_ps_e_0_0_stub.v /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1/design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1/design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.v /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/ab/Videos/amd_xilinx/project_1/design2023_1_zynq_ultra_ps_e_0_0_synth_1/design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.vhdl /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
close [open .end.used_ip_cache.rst w]
}; # end if cacheID
if {[file isdir /home/ab/Videos/amd_xilinx/project_1/project_1.ip_user_files/ip/design2023_1_zynq_ultra_ps_e_0_0]} {
catch {
file copy -force /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_stub.v /home/ab/Videos/amd_xilinx/project_1/project_1.ip_user_files/ip/design2023_1_zynq_ultra_ps_e_0_0
}
}
if {[file isdir /home/ab/Videos/amd_xilinx/project_1/project_1.ip_user_files/ip/design2023_1_zynq_ultra_ps_e_0_0]} {
catch {
file copy -force /home/ab/Videos/amd_xilinx/project_1/project_1.gen/sources_1/bd/design2023_1/ip/design2023_1_zynq_ultra_ps_e_0_0/design2023_1_zynq_ultra_ps_e_0_0_stub.vhdl /home/ab/Videos/amd_xilinx/project_1/project_1.ip_user_files/ip/design2023_1_zynq_ultra_ps_e_0_0
}
}
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "design2023_1_zynq_ultra_ps_e_0_0_synth_1" END { }
2. Lab2 : Experiment 4 - Vitis 2023.1, Platform name is HW_Lab2
platform create -name {HW_Lab2}\
-hw {/home/ab/Videos/amd_xilinx/project_1/design2023_1_wrapper.xsa}\
-proc {psu_cortexa53_0} -os {standalone} -arch {64-bit} -fsbl-target {psu_cortexa53_0} -out {/home/ab/Videos/amd_xilinx}
platform write
platform generate -domains
platform active {HW_Lab2}
bsp reload
bsp write
platform generate
domain active {zynqmp_fsbl}
bsp reload
domain active {zynqmp_pmufw}
bsp reload
Hello on GtkTerm and Minicom
Hello on GtkTerm
Hello on Minicom
3. Lab3
1) In Vivado 2023.1 , SD0, if slot type is 3.0, then data transfer is only 8 bit
if slot type is 2.0, then data transfer is only 4 bit
2) In Vivado 2023.1 , if I Enable and Map all PS Peripherals individually and saves, it allows.
But if I Set the PS Clocks, and try to save only 2 setting, it do not allow to save partial configurations even if they are not in 'red'.
3) Now when , DP_ video, DP_audio, dp_stc settings are changed, then only the fractional part gets enabled
4) After changing DP_STC to RPLL, enabling,
5) This is not shown in manual or may be this is due to vivado 2023.1
6)Manual shows green box on TOPSW_LSBUS IOPLL, may be error or may be due to vivado 2023.1
TOPSW_MAIN has to be changed to DPLL. Screenshot from manual
7)Got rid of red, only by changing TOPSW_MAIN to DPLL
8)You can see Clicks on peripherals
9)As I had deleted earlier lab, so there was no HDL wrapper and I got error
10)Now HDL Wrapper is again creating
11)HDL wrapper created
12) Now synthesis is able to get launched in bitstream
13) But Synthesis Failed . I tried this 7 times, deleting project etc but synthesis always failed.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_1_zynq_ultra_ps_e_0_1 IS PORT ); END design_1_zynq_ultra_ps_e_0_1;
14) You can see " );" error but it is read only file. This error didn't came if I do not set or map peripherals or if I do not do this particular lab.
15) I tried with sudo admin 5 times, but same error. Now downloading upgrade of June 2023 which is 25.84 GB.
16) I upgraded with Vivado ML Edition Update 1 - 2023.1 Product Update which is of Jun 21, 2023, but it didn't resolved error. I changed board's Speed grade to 2 instead -1 but this also didnt solved error.
17) i connected hardware and then tried all above, didnt solved
18) I uninstalled fully 2 times and reinstalled 2 times, it solved
19) In videos, i have explored synthesis implemented design and done memory and peripheral tests and named as output 1, output 2 and output 3
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 115200);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
}
Video has exploration of the implementation design.
4. Lab4 and Lab5
5. Lab5
1) In manual, it is written "9. Change the Support for AXI Narrow Bursts to Manual and set to Yes. Click OK." But in Vivado 2023.1, it was automatically set to Yes for 32 bit or 128 bit and there was no change option.
2) I disabled GPIO EMIO which I had done from my side (was not in the training), bitstream still failed but synthesis no error.
3) I recreated this lab from scratch as project_2. Now completed lab5
Video has exploration of Ultra96V2G Hardware Lab5 Output BRAM and explorations of reports, cells, LUT etc.
6. Lab6
1) As this lab again got stuck, I created again new HDL wrapper
2) The tcl of this wrapper is as per Instruction manual as till these attempts, either I added (added peripheral from my side or setting) or the instruction manual was not able to get followed due to errors occurring while following manual(so few minor options were not selected but skipped). Here is the complete as per manual that should be done either in clocking or peripherals. The TCL script is
################################################################
# This is a generated script based on design: design_p3_lab5o
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2023.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source design_p3_lab5o_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu3eg-sbva484-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_p3_lab5o
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:zynq_ultra_ps_e:3.5\
xilinx.com:ip:axi_bram_ctrl:4.1\
xilinx.com:ip:blk_mem_gen:8.4\
xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:proc_sys_reset:5.0\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
# Create instance: zynq_ultra_ps_e_0, and set properties
set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
set_property -dict [list \
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFF} \
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x10000000} \
CONFIG.PSU_MIO_12_POLARITY {Default} \
CONFIG.PSU_MIO_17_POLARITY {Default} \
CONFIG.PSU_MIO_18_POLARITY {Default} \
CONFIG.PSU_MIO_19_POLARITY {Default} \
CONFIG.PSU_MIO_20_POLARITY {Default} \
CONFIG.PSU_MIO_23_POLARITY {Default} \
CONFIG.PSU_MIO_25_POLARITY {Default} \
CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_27_SLEW {fast} \
CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_29_SLEW {fast} \
CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_31_POLARITY {Default} \
CONFIG.PSU_MIO_31_SLEW {fast} \
CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_35_POLARITY {Default} \
CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_36_POLARITY {Default} \
CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_37_POLARITY {Default} \
CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_39_POLARITY {Default} \
CONFIG.PSU_MIO_39_SLEW {fast} \
CONFIG.PSU_MIO_44_POLARITY {Default} \
CONFIG.PSU_MIO_45_POLARITY {Default} \
CONFIG.PSU_MIO_76_POLARITY {Default} \
CONFIG.PSU_MIO_77_POLARITY {Default} \
CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_7_POLARITY {Default} \
CONFIG.PSU_MIO_8_POLARITY {Default} \
CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0\
MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#SPI 0#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD\
1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]}\
\
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
CONFIG.PSU__ACT_DDR_FREQ_MHZ {479.995209} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {213.331207} \
CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {533.328003} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {9.362208} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {42} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {10.082377} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {39} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.026611} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {533.328003} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {533.328003} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.498123} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.498123} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.498123} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333000} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
CONFIG.PSU__DDRC__DEVICE_CAPACITY {2048 MBits} \
CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
CONFIG.PSU__DDRC__ECC {Disabled} \
CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {13} \
CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
CONFIG.PSU__DDRC__T_FAW {40.0} \
CONFIG.PSU__DDRC__T_RAS_MIN {42} \
CONFIG.PSU__DDRC__T_RC {63} \
CONFIG.PSU__DDRC__T_RCD {10} \
CONFIG.PSU__DDRC__T_RP {12} \
CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__DLL__ISUSED {1} \
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
CONFIG.PSU__DP__REF_CLK_FREQ {27} \
CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk2} \
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GT__LINK_SPEED {HBR} \
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
CONFIG.PSU__PMU_COHERENCY {0} \
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
CONFIG.PSU__PMU__GPI0__ENABLE {1} \
CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
CONFIG.PSU__PMU__GPO0__ENABLE {1} \
CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
CONFIG.PSU__PMU__GPO1__ENABLE {1} \
CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
CONFIG.PSU__PMU__GPO2__ENABLE {1} \
CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
CONFIG.PSU__PMU__GPO2__POLARITY {low} \
CONFIG.PSU__PMU__GPO3__ENABLE {0} \
CONFIG.PSU__PMU__GPO4__ENABLE {0} \
CONFIG.PSU__PMU__GPO5__ENABLE {0} \
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
\
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
\
CONFIG.PSU__SD0_COHERENCY {0} \
CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SD1_COHERENCY {0} \
CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \
CONFIG.PSU__SPI0__GRP_SS1__IO {MIO 40} \
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
CONFIG.PSU__UART0__BAUD_RATE {115200} \
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
CONFIG.PSU__UART1__BAUD_RATE {115200} \
CONFIG.PSU__UART1__MODEM__ENABLE {0} \
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
CONFIG.PSU__USB0_COHERENCY {0} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk3} \
CONFIG.PSU__USB1_COHERENCY {0} \
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk3} \
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
CONFIG.PSU__USE__M_AXI_GP0 {1} \
CONFIG.PSU__USE__M_AXI_GP2 {0} \
] $zynq_ultra_ps_e_0
# Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
# Create instance: axi_bram_ctrl_0_bram, and set properties
set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ]
set_property CONFIG.Memory_Type {True_Dual_Port_RAM} $axi_bram_ctrl_0_bram
# Create instance: axi_smc, and set properties
set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
set_property CONFIG.NUM_SI {1} $axi_smc
# Create instance: rst_ps8_0_99M, and set properties
set rst_ps8_0_99M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_99M ]
# Create interface connections
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB]
connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] [get_bd_intf_pins axi_smc/S00_AXI]
# Create port connections
connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins rst_ps8_0_99M/peripheral_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_smc/aresetn]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins rst_ps8_0_99M/slowest_sync_clk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins rst_ps8_0_99M/ext_reset_in]
# Create address segments
assign_bd_address -offset 0xA0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
7. Lab7
When AXI-full interface is selected with enabling of interrupts, following 3 PWM VHDL automatically get created
1) PWM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM_w_Int_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_ID_WIDTH : integer := 1;
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6;
C_S00_AXI_AWUSER_WIDTH : integer := 0;
C_S00_AXI_ARUSER_WIDTH : integer := 0;
C_S00_AXI_WUSER_WIDTH : integer := 0;
C_S00_AXI_RUSER_WIDTH : integer := 0;
C_S00_AXI_BUSER_WIDTH : integer := 0;
-- Parameters of Axi Slave Bus Interface S_AXI_INTR
C_S_AXI_INTR_DATA_WIDTH : integer := 32;
C_S_AXI_INTR_ADDR_WIDTH : integer := 5;
C_NUM_OF_INTR : integer := 1;
C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF";
C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF";
C_IRQ_SENSITIVITY : integer := 1;
C_IRQ_ACTIVE_STATE : integer := 1
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awlen : in std_logic_vector(7 downto 0);
s00_axi_awsize : in std_logic_vector(2 downto 0);
s00_axi_awburst : in std_logic_vector(1 downto 0);
s00_axi_awlock : in std_logic;
s00_axi_awcache : in std_logic_vector(3 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awqos : in std_logic_vector(3 downto 0);
s00_axi_awregion : in std_logic_vector(3 downto 0);
s00_axi_awuser : in std_logic_vector(C_S00_AXI_AWUSER_WIDTH-1 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wlast : in std_logic;
s00_axi_wuser : in std_logic_vector(C_S00_AXI_WUSER_WIDTH-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_buser : out std_logic_vector(C_S00_AXI_BUSER_WIDTH-1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_arid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arlen : in std_logic_vector(7 downto 0);
s00_axi_arsize : in std_logic_vector(2 downto 0);
s00_axi_arburst : in std_logic_vector(1 downto 0);
s00_axi_arlock : in std_logic;
s00_axi_arcache : in std_logic_vector(3 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arqos : in std_logic_vector(3 downto 0);
s00_axi_arregion : in std_logic_vector(3 downto 0);
s00_axi_aruser : in std_logic_vector(C_S00_AXI_ARUSER_WIDTH-1 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rlast : out std_logic;
s00_axi_ruser : out std_logic_vector(C_S00_AXI_RUSER_WIDTH-1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXI_INTR
s_axi_intr_aclk : in std_logic;
s_axi_intr_aresetn : in std_logic;
s_axi_intr_awaddr : in std_logic_vector(C_S_AXI_INTR_ADDR_WIDTH-1 downto 0);
s_axi_intr_awprot : in std_logic_vector(2 downto 0);
s_axi_intr_awvalid : in std_logic;
s_axi_intr_awready : out std_logic;
s_axi_intr_wdata : in std_logic_vector(C_S_AXI_INTR_DATA_WIDTH-1 downto 0);
s_axi_intr_wstrb : in std_logic_vector((C_S_AXI_INTR_DATA_WIDTH/8)-1 downto 0);
s_axi_intr_wvalid : in std_logic;
s_axi_intr_wready : out std_logic;
s_axi_intr_bresp : out std_logic_vector(1 downto 0);
s_axi_intr_bvalid : out std_logic;
s_axi_intr_bready : in std_logic;
s_axi_intr_araddr : in std_logic_vector(C_S_AXI_INTR_ADDR_WIDTH-1 downto 0);
s_axi_intr_arprot : in std_logic_vector(2 downto 0);
s_axi_intr_arvalid : in std_logic;
s_axi_intr_arready : out std_logic;
s_axi_intr_rdata : out std_logic_vector(C_S_AXI_INTR_DATA_WIDTH-1 downto 0);
s_axi_intr_rresp : out std_logic_vector(1 downto 0);
s_axi_intr_rvalid : out std_logic;
s_axi_intr_rready : in std_logic;
irq : out std_logic
);
end PWM_w_Int_v1_0;
architecture arch_imp of PWM_w_Int_v1_0 is
-- component declaration
component PWM_w_Int_v1_0_S00_AXI is
generic (
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6;
C_S_AXI_AWUSER_WIDTH : integer := 0;
C_S_AXI_ARUSER_WIDTH : integer := 0;
C_S_AXI_WUSER_WIDTH : integer := 0;
C_S_AXI_RUSER_WIDTH : integer := 0;
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWREGION : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARREGION : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component PWM_w_Int_v1_0_S00_AXI;
component PWM_w_Int_v1_0_S_AXI_INTR is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5;
C_NUM_OF_INTR : integer := 1;
C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF";
C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF";
C_IRQ_SENSITIVITY : integer := 1;
C_IRQ_ACTIVE_STATE : integer := 1
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
irq : out std_logic
);
end component PWM_w_Int_v1_0_S_AXI_INTR;
begin
-- Instantiation of Axi Bus Interface S00_AXI
PWM_w_Int_v1_0_S00_AXI_inst : PWM_w_Int_v1_0_S00_AXI
generic map (
C_S_AXI_ID_WIDTH => C_S00_AXI_ID_WIDTH,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH,
C_S_AXI_AWUSER_WIDTH => C_S00_AXI_AWUSER_WIDTH,
C_S_AXI_ARUSER_WIDTH => C_S00_AXI_ARUSER_WIDTH,
C_S_AXI_WUSER_WIDTH => C_S00_AXI_WUSER_WIDTH,
C_S_AXI_RUSER_WIDTH => C_S00_AXI_RUSER_WIDTH,
C_S_AXI_BUSER_WIDTH => C_S00_AXI_BUSER_WIDTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWID => s00_axi_awid,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWLEN => s00_axi_awlen,
S_AXI_AWSIZE => s00_axi_awsize,
S_AXI_AWBURST => s00_axi_awburst,
S_AXI_AWLOCK => s00_axi_awlock,
S_AXI_AWCACHE => s00_axi_awcache,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWQOS => s00_axi_awqos,
S_AXI_AWREGION => s00_axi_awregion,
S_AXI_AWUSER => s00_axi_awuser,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WLAST => s00_axi_wlast,
S_AXI_WUSER => s00_axi_wuser,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BID => s00_axi_bid,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BUSER => s00_axi_buser,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARID => s00_axi_arid,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARLEN => s00_axi_arlen,
S_AXI_ARSIZE => s00_axi_arsize,
S_AXI_ARBURST => s00_axi_arburst,
S_AXI_ARLOCK => s00_axi_arlock,
S_AXI_ARCACHE => s00_axi_arcache,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARQOS => s00_axi_arqos,
S_AXI_ARREGION => s00_axi_arregion,
S_AXI_ARUSER => s00_axi_aruser,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RID => s00_axi_rid,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RLAST => s00_axi_rlast,
S_AXI_RUSER => s00_axi_ruser,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Instantiation of Axi Bus Interface S_AXI_INTR
PWM_w_Int_v1_0_S_AXI_INTR_inst : PWM_w_Int_v1_0_S_AXI_INTR
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_INTR_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_INTR_ADDR_WIDTH,
C_NUM_OF_INTR => C_NUM_OF_INTR,
C_INTR_SENSITIVITY => C_INTR_SENSITIVITY,
C_INTR_ACTIVE_STATE => C_INTR_ACTIVE_STATE,
C_IRQ_SENSITIVITY => C_IRQ_SENSITIVITY,
C_IRQ_ACTIVE_STATE => C_IRQ_ACTIVE_STATE
)
port map (
S_AXI_ACLK => s_axi_intr_aclk,
S_AXI_ARESETN => s_axi_intr_aresetn,
S_AXI_AWADDR => s_axi_intr_awaddr,
S_AXI_AWPROT => s_axi_intr_awprot,
S_AXI_AWVALID => s_axi_intr_awvalid,
S_AXI_AWREADY => s_axi_intr_awready,
S_AXI_WDATA => s_axi_intr_wdata,
S_AXI_WSTRB => s_axi_intr_wstrb,
S_AXI_WVALID => s_axi_intr_wvalid,
S_AXI_WREADY => s_axi_intr_wready,
S_AXI_BRESP => s_axi_intr_bresp,
S_AXI_BVALID => s_axi_intr_bvalid,
S_AXI_BREADY => s_axi_intr_bready,
S_AXI_ARADDR => s_axi_intr_araddr,
S_AXI_ARPROT => s_axi_intr_arprot,
S_AXI_ARVALID => s_axi_intr_arvalid,
S_AXI_ARREADY => s_axi_intr_arready,
S_AXI_RDATA => s_axi_intr_rdata,
S_AXI_RRESP => s_axi_intr_rresp,
S_AXI_RVALID => s_axi_intr_rvalid,
S_AXI_RREADY => s_axi_intr_rready,
irq => irq
);
-- Add user logic here
-- User logic ends
end arch_imp;
2) PWM S00 AXI
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM_w_Int_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6;
-- Width of optional user defined signal in write address channel
C_S_AXI_AWUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read address channel
C_S_AXI_ARUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write data channel
C_S_AXI_WUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read data channel
C_S_AXI_RUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write response channel
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_AWLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- write transaction.
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_AWREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the write address channel.
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Optional User-defined signal in the write data channel.
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Optional User-defined signal in the write response channel.
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_ARLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- read transaction.
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_ARREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the read address channel.
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and
-- control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Optional User-defined signal in the read address channel.
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end PWM_w_Int_v1_0_S00_AXI;
architecture arch_imp of PWM_w_Int_v1_0_S00_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_buser : std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rlast : std_logic;
signal axi_ruser : std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := "000000";
------------------------------------------------
---- Signals for user logic memory space example
--------------------------------------------------
signal mem_address : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal mem_select : std_logic_vector(USER_NUM_MEM-1 downto 0);
type word_array is array (0 to USER_NUM_MEM-1) of std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal mem_data_out : word_array;
signal i : integer;
signal j : integer;
signal mem_byte_index : integer;
type BYTE_RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BUSER <= axi_buser;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RLAST <= axi_rlast;
S_AXI_RUSER <= axi_ruser;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
axi_buser <= (others => '0');
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_ruser <= (others => '0');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- ------------------------------------------
-- -- Example code to access user logic memory region
-- ------------------------------------------
gen_mem_sel: if (USER_NUM_MEM >= 1) generate
begin
mem_select <= "1";
mem_address <= axi_araddr(ADDR_LSB+OPT_MEM_ADDR_BITS downto ADDR_LSB) when axi_arv_arr_flag = '1' else
axi_awaddr(ADDR_LSB+OPT_MEM_ADDR_BITS downto ADDR_LSB) when axi_awv_awr_flag = '1' else
(others => '0');
end generate gen_mem_sel;
-- implement Block RAM(s)
BRAM_GEN : for i in 0 to USER_NUM_MEM-1 generate
signal mem_rden : std_logic;
signal mem_wren : std_logic;
begin
mem_wren <= axi_wready and S_AXI_WVALID ;
mem_rden <= axi_arv_arr_flag ;
BYTE_BRAM_GEN : for mem_byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) generate
signal byte_ram : BYTE_RAM_TYPE;
signal data_in : std_logic_vector(8-1 downto 0);
signal data_out : std_logic_vector(8-1 downto 0);
begin
--assigning 8 bit data
data_in <= S_AXI_WDATA((mem_byte_index*8+7) downto mem_byte_index*8);
data_out <= byte_ram(to_integer(unsigned(mem_address)));
BYTE_RAM_PROC : process( S_AXI_ACLK ) is
begin
if ( rising_edge (S_AXI_ACLK) ) then
if ( mem_wren = '1' and S_AXI_WSTRB(mem_byte_index) = '1' ) then
byte_ram(to_integer(unsigned(mem_address))) <= data_in;
end if;
end if;
end process BYTE_RAM_PROC;
process( S_AXI_ACLK ) is
begin
if ( rising_edge (S_AXI_ACLK) ) then
if ( mem_rden = '1') then
mem_data_out(i)((mem_byte_index*8+7) downto mem_byte_index*8) <= data_out;
end if;
end if;
end process;
end generate BYTE_BRAM_GEN;
end generate BRAM_GEN;
--Output register or memory read data
process(mem_data_out, axi_rvalid ) is
begin
if (axi_rvalid = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
axi_rdata <= mem_data_out(0); -- memory range 0 read data
else
axi_rdata <= (others => '0');
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
3) PWM S00 AXI interrupt
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM_w_Int_v1_0_S_AXI_INTR is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5;
-- Number of Interrupts
C_NUM_OF_INTR : integer := 1;
-- Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL
C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF";
-- Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]
C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF";
-- Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL
C_IRQ_SENSITIVITY : integer := 1;
-- Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]
C_IRQ_ACTIVE_STATE : integer := 1
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic;
-- interrupt out port
irq : out std_logic
);
end PWM_w_Int_v1_0_S_AXI_INTR;
architecture arch_imp of PWM_w_Int_v1_0_S_AXI_INTR is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
--------------------------------------------------
---- Signals for Interrupt register space
--------------------------------------------------
---- Number of Slave Registers 5
signal reg_global_intr_en :std_logic_vector(0 downto 0);
signal reg_intr_en :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_sts :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_ack :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_pending :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal intr :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal det_intr :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal intr_reg_rden :std_logic;
signal intr_reg_wren :std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal intr_counter :std_logic_vector(3 downto 0);
signal intr_all : std_logic;
signal intr_ack_all : std_logic;
signal s_irq : std_logic;
signal intr_all_ff : std_logic;
signal intr_ack_all_ff: std_logic;
signal aw_en : std_logic;
function or_reduction (vec : in std_logic_vector) return std_logic is
variable res_v : std_logic := '0'; -- Null vec vector will also return '1'
begin
for i in vec'range loop
res_v := res_v or vec(i);
end loop;
return res_v;
end function;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
aw_en <= '0';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
intr_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
gen_intr_reg : for i in 0 to (C_NUM_OF_INTR - 1) generate
begin
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_global_intr_en <= (others => '0');
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "000") then
reg_global_intr_en(0) <= S_AXI_WDATA(0);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_intr_en(i) <= '0';
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "001") then
reg_intr_en(i) <= S_AXI_WDATA(i);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_sts(i) <= '0';
else
reg_intr_sts(i) <= det_intr(i);
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_ack(i) <= '0';
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "011") then
reg_intr_ack(i) <= S_AXI_WDATA(i);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_pending(i) <= '0';
else
reg_intr_pending(i) <= reg_intr_sts(i) and reg_intr_en(i);
end if;
end if;
end process;
end generate gen_intr_reg;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
intr_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
RDATA_INTR_NUM_32: if (C_NUM_OF_INTR=32) generate
begin
process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
variable loc_addr :std_logic_vector(2 downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '0');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(4 downto 2);
case loc_addr is
when "000" =>
reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
when "001" =>
reg_data_out <= reg_intr_en;
when "010" =>
reg_data_out <= reg_intr_sts;
when "011" =>
reg_data_out <= reg_intr_ack;
when "100" =>
reg_data_out <= reg_intr_pending;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
end generate RDATA_INTR_NUM_32;
RDATA_INTR_NUM_LESS_32: if (C_NUM_OF_INTR/=32) generate
begin
process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
variable loc_addr :std_logic_vector(2 downto 0);
variable zero : std_logic_vector (C_S_AXI_DATA_WIDTH-C_NUM_OF_INTR-1 downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '0');
zero := (others=>'0');
else
zero := (others=>'0');
-- Address decoding for reading registers
loc_addr := axi_araddr(4 downto 2);
case loc_addr is
when "000" =>
reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
when "001" =>
reg_data_out <= zero & reg_intr_en;
when "010" =>
reg_data_out <= zero & reg_intr_sts;
when "011" =>
reg_data_out <= zero & reg_intr_ack;
when "100" =>
reg_data_out <= zero & reg_intr_pending;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
end generate RDATA_INTR_NUM_LESS_32;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (intr_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
------------------------------------------------------
--Example code to generate user logic interrupts
--Note: The example code presented here is to show you one way of generating
-- interrupts from the user logic. This code snippet generates a level
-- triggered interrupt when the intr_counter_reg counts down to zero.
-- while intr_control_reg[0] is asserted. Deasserting the intr_control_reg[0]
-- disables the counter and clears the interrupt signal.
------------------------------------------------------
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0') then
intr_counter <= (others => '1');
elsif (intr_counter /= x"0") then
intr_counter <= std_logic_vector (unsigned(intr_counter) - 1);
end if;
end if;
end process;
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0') then
intr <= (others => '0');
else
if (intr_counter = x"a") then
intr <= (others => '1');
else
intr <= (others => '0');
end if;
end if;
end if;
end process;
-- detects interrupt in any intr input
process (S_AXI_ACLK)
variable temp : std_logic;
begin
if (rising_edge (S_AXI_ACLK)) then
if( S_AXI_ARESETN = '0' or intr_ack_all_ff = '1') then
intr_all <= '0';
else
intr_all <= or_reduction(reg_intr_pending);
end if;
end if;
end process;
-- detects intr ack in any reg_intr_ack reg bits
process (S_AXI_ACLK)
variable temp : std_logic;
begin
if (rising_edge (S_AXI_ACLK)) then
if( S_AXI_ARESETN = '0' or intr_ack_all_ff = '1') then
intr_ack_all <= '0';
else
intr_ack_all <= or_reduction(reg_intr_ack);
end if;
end if;
end process;
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0') then
intr_all_ff <= '0';
intr_ack_all_ff <= '0';
else
intr_all_ff <= intr_all;
intr_ack_all_ff <= intr_ack_all;
end if;
end if;
end process;
gen_intr_detection : for i in 0 to (C_NUM_OF_INTR - 1) generate
signal s_irq_lvl: std_logic;
begin
gen_intr_level_detect: if (C_INTR_SENSITIVITY(i) = '1') generate
begin
gen_intr_active_high_detect: if (C_INTR_ACTIVE_STATE(i) = '1') generate
begin
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
det_intr(i) <= '0';
else
if (intr(i) = '1') then
det_intr(i) <= '1';
end if;
end if;
end if;
end process;
end generate gen_intr_active_high_detect;
gen_intr_active_low_detect: if (C_INTR_ACTIVE_STATE(i) = '0') generate
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
det_intr(i) <= '0';
else
if (intr(i) = '0') then
det_intr(i) <= '1';
end if;
end if;
end if;
end process;
end generate gen_intr_active_low_detect;
end generate gen_intr_level_detect;
gen_intr_edge_detect: if (C_INTR_SENSITIVITY(i) = '0') generate
signal intr_edge : std_logic_vector (C_NUM_OF_INTR-1 downto 0);
signal intr_ff : std_logic_vector (C_NUM_OF_INTR-1 downto 0);
signal intr_ff2 : std_logic_vector (C_NUM_OF_INTR-1 downto 0);
begin
gen_intr_rising_edge_detect: if (C_INTR_ACTIVE_STATE(i) = '1') generate
begin
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
intr_ff(i) <= '0';
intr_ff2(i) <= '0';
else
intr_ff(i) <= intr(i);
intr_ff2(i) <= intr_ff(i);
end if;
end if;
end process;
intr_edge(i) <= intr_ff(i) and (not intr_ff2(i));
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
det_intr(i) <= '0';
elsif (intr_edge(i) = '1') then
det_intr(i) <= '1';
end if;
end if;
end process;
end generate gen_intr_rising_edge_detect;
gen_intr_falling_edge_detect: if (C_INTR_ACTIVE_STATE(i) = '0') generate
begin
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
intr_ff(i) <= '0';
intr_ff2(i) <= '0';
else
intr_ff(i) <= intr(i);
intr_ff2(i) <= intr_ff(i);
end if;
end if;
end process;
intr_edge(i) <= intr_ff2(i) and (not intr_ff(i));
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
det_intr(i) <= '0';
elsif (intr_edge(i) = '1') then
det_intr(i) <= '1';
end if;
end if;
end process;
end generate gen_intr_falling_edge_detect;
end generate gen_intr_edge_detect;
-- IRQ generation logic
gen_irq_level: if (C_IRQ_SENSITIVITY = 1) generate
begin
irq_level_high: if (C_IRQ_ACTIVE_STATE = 1) generate
begin
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
s_irq_lvl <= '0';
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
s_irq_lvl <= '1';
end if;
end if;
end process;
s_irq <= s_irq_lvl;
end generate irq_level_high;
irq_level_low: if (C_IRQ_ACTIVE_STATE = 0) generate
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
s_irq_lvl <= '1';
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
s_irq_lvl <= '0';
end if;
end if;
end process;
s_irq <= s_irq_lvl;
end generate irq_level_low;
end generate gen_irq_level;
gen_irq_edge: if (C_IRQ_SENSITIVITY = 0) generate
signal s_irq_lvl_ff:std_logic;
begin
irq_rising_edge: if (C_IRQ_ACTIVE_STATE = 1) generate
begin
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
s_irq_lvl <= '0';
s_irq_lvl_ff <= '0';
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
s_irq_lvl <= '1';
s_irq_lvl_ff <= s_irq_lvl;
end if;
end if;
end process;
s_irq <= s_irq_lvl and (not s_irq_lvl_ff);
end generate irq_rising_edge;
irq_falling_edge: if (C_IRQ_ACTIVE_STATE = 0) generate
begin
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
s_irq_lvl <= '1';
s_irq_lvl_ff <= '1';
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
s_irq_lvl <= '0';
s_irq_lvl_ff <= s_irq_lvl;
end if;
end if;
end process;
s_irq <= not (s_irq_lvl_ff and (not s_irq_lvl));
end generate irq_falling_edge;
end generate gen_irq_edge;
irq <= s_irq;
end generate gen_intr_detection;
-- Add user logic here
-- User logic ends
end arch_imp;
4) All these files and interrupt files are instantiated with component declaration PWM_Controller_Int and changes are made in user logic section.
5) Now errors here
When AXI-Lite interface is selected, following 2 PWM VHDL automatically get created
1) PWM_w_Int_v1_0
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity PWM_w_Int_v1_0 is generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S00_AXI C_S00_AXI_DATA_WIDTH : integer := 32; C_S00_AXI_ADDR_WIDTH : integer := 4 ); port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S00_AXI s00_axi_aclk : in std_logic; s00_axi_aresetn : in std_logic; s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_awprot : in std_logic_vector(2 downto 0); s00_axi_awvalid : in std_logic; s00_axi_awready : out std_logic; s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); s00_axi_wvalid : in std_logic; s00_axi_wready : out std_logic; s00_axi_bresp : out std_logic_vector(1 downto 0); s00_axi_bvalid : out std_logic; s00_axi_bready : in std_logic; s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_arprot : in std_logic_vector(2 downto 0); s00_axi_arvalid : in std_logic; s00_axi_arready : out std_logic; s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_rresp : out std_logic_vector(1 downto 0); s00_axi_rvalid : out std_logic; s00_axi_rready : in std_logic ); end PWM_w_Int_v1_0; architecture arch_imp of PWM_w_Int_v1_0 is -- component declaration component PWM_w_Int_v1_0_S00_AXI is generic ( C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 4 ); port ( S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic ); end component PWM_w_Int_v1_0_S00_AXI; begin -- Instantiation of Axi Bus Interface S00_AXI PWM_w_Int_v1_0_S00_AXI_inst : PWM_w_Int_v1_0_S00_AXI generic map ( C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH ) port map ( S_AXI_ACLK => s00_axi_aclk, S_AXI_ARESETN => s00_axi_aresetn, S_AXI_AWADDR => s00_axi_awaddr, S_AXI_AWPROT => s00_axi_awprot, S_AXI_AWVALID => s00_axi_awvalid, S_AXI_AWREADY => s00_axi_awready, S_AXI_WDATA => s00_axi_wdata, S_AXI_WSTRB => s00_axi_wstrb, S_AXI_WVALID => s00_axi_wvalid, S_AXI_WREADY => s00_axi_wready, S_AXI_BRESP => s00_axi_bresp, S_AXI_BVALID => s00_axi_bvalid, S_AXI_BREADY => s00_axi_bready, S_AXI_ARADDR => s00_axi_araddr, S_AXI_ARPROT => s00_axi_arprot, S_AXI_ARVALID => s00_axi_arvalid, S_AXI_ARREADY => s00_axi_arready, S_AXI_RDATA => s00_axi_rdata, S_AXI_RRESP => s00_axi_rresp, S_AXI_RVALID => s00_axi_rvalid, S_AXI_RREADY => s00_axi_rready ); -- Add user logic here -- User logic ends end arch_imp;
2) PWM_w_Int_v1_0_S00_AXI
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM_w_Int_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end PWM_w_Int_v1_0_S00_AXI;
architecture arch_imp of PWM_w_Int_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal aw_en : std_logic;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
aw_en <= '0';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
Those who want to see differences in code of 2021.2 and 2023.1, I have copied paste code from Vivado 2023.1
1) Now, component declaration is done
component PWM_Controller_Int is
generic(
period : integer := 20
);
port(
Clk : in std_logic;
DutyCycle : in std_logic_vector(31 downto 0);
Reset : in std_logic;
PWM_out : out std_logic_vector(0 downto 0);
Interrupt : out std_logic;
count : out std_logic_vector(period-1 downto 0)
);
end component PWM_Controller_Int;
2) user logic section modification
PWM_Controller_Int_Inst : PWM_Controller_Int
generic map(
period => PWM_PERIOD
)
port map(
Clk => s00_axi_aclk,
DutyCycle => DutyCycle_int,
Reset => s00_axi_aresetn,
PWM_out => LED,
Interrupt => Interrupt_out,
count => PWM_Counter
);
3) associations between the Controller signal and the Slave AXI can be seen in 'user logic section modification'
Clk => s00_axi_aclk
Reset => s00_axi_aresetn,
4) following line of Slave is missing in I/O Connections assignment, given in instruction manual.This is missing in solution (cut paste run )file.
begin
-- I/O Connections assignments
slave_reg0 <= slv_reg0;
but slave is added
slave_reg0: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
The TCL of pwm
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to validate C_S00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to validate C_S00_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to validate C_S00_AXI_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
}
proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
} } } } }
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
} } }} }
MDD (Microprocessor Driver Definition)
OPTION psf_version = 2.1;
BEGIN DRIVER PWM_w_Int
OPTION supported_peripherals = (PWM_w_Int);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = PWM_w_Int;
END DRIVER
TCL of block diagram of PWM
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "PWM_w_Int" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
}
Define
#define PWM_W_INT_S00_AXI_SLV_REG0_OFFSET 0
#define PWM_W_INT_S00_AXI_SLV_REG1_OFFSET 4
#define PWM_W_INT_S00_AXI_SLV_REG2_OFFSET 8
#define PWM_W_INT_S00_AXI_SLV_REG3_OFFSET 12
#define PWM_W_INT_mWriteReg(BaseAddress, RegOffset, Data) Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
#define PWM_W_INT_mReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))
The excel sheet file is
Synthesis here took 1 hr 30 min or lesser time, a single mistake again 1 hr 30 min. I able to move to next lab after around 9-10 hrs, just because synthesis, generating output, bitstream...
8. Lab8
9. Lab9
Instead of copying paste of typed content, I uploaded pics/images which are proof that I worked on all labs on 2023.1.
I shared my lab learning journey, errors, problems faced and how I solved. None of the labs achieved in 1 attempt but took 3-12 attempts! If such problems would have come in paid project, most of them would had fired , taunted, humiliated and disrespected but now I have as such left r&d.
I completed Ultra96 Training Courses 2021.2 (Path to Programmable III) - Hardware labs on latest Vitis 2023.1/Vivado 2023.1 instead Training version 2021.2.
This is Blog3.
Abhishek Bansal
( Not representing anyone else. Category:Individual,Solo)
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