The Digilent Arty S7: An Unexpected Journey

When I read: 

Step 1 - Clock setup

Add the DDR Clock and System Reset by selecting them from the "Board" tab, right-click on the selected item, and click on "Auto Connect". Customise the Clock block by double-clicking on it, and in Board tab select "Reset" for "EXT_RESET_IN", and

in"Output Clock" tab, select "clock_out2" and set 200MHz as frequency,

then select "Reset Active Low" for Reset Type. Run the Connection Automation wizard, and accept all the defaults.

I dont know what to do!

Have you installed Vivado, Vitis, and Digilent Board Files?

Are you following the tutorials here?

https://digilent.com/reference/programmable-logic/arty-s7/start

I made Synthese but after next Step I got [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.and [DRC UTLZ-1] Resource utilization: LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 15045 of such cell types but only 14600 compatible sites are available in the target device. So I stop this learning because this is not my target. My target: I need a fast controller for the ignition control of my car, a 500SL from 1991, to replace the rotating distributor. My first question is, are there interrupts in the FPGA or do I use Microblaze? My input signals are 2 square wave voltages, the XDAC analog-digital converters also react very quickly, but I haven't yet learned how the FPGA reacts to interrupts.

Ma first problem was because I did not use my ArtyS7 Board I used only the FPGA ...but I learnd it nw

In FPGA, every signal happens "immediately", and you can react on its state change. You don't need to interrupt other activities (unless you want that).

In FPGA, every signal happens "immediately", and you can react on its state change. You don't need to interrupt other activities (unless you want that).

So its possible to use A0-A5 Single-Ended Analog Input to convert Square wave voltages very fast, super! When the rising and falling edges of the square wave voltage have been processed, the FPGA has "nothing" to do and waits and waits, which is what software developers call polling. So that's faster than any interrupt?