Via to pad clearance design rule

Question

Placing a via over the top of a SMT pad with the same net does not create a design rule error. Is there a way to add a rule prohibiting this?

I tried creating a clearance rule for "same net only" with all the clearance matrix values set to zero except Via-to-SMD Pad and Via-to-TH Pad. Unfortunately, this generates a Via-to-track clearance violation on all vias. I'm assuming zero is not sufficient to disable the matrix connection (e.g., setting Via-to-Track == 0, doesn't disable this clearance check).

Seems like there should be a way to prevent vias over the top of SMD pads. Am I missing something?

adamwebber · Accepted Answer

So I've never had an issue with this but suddenly I am questioning all of my previous work. I have used Altium extensively and it is so easy to create simple rules to avoid placing vias on pads. CircuitStudio is not quite as simple. You can still use all of the functionality from Altium by exporting the rules and then writing them as a text file then importing them back in. Sometimes it's necessary but it sucks. I did try this and I was able to successfully create a via on pad rule by using the built-in PCB Rules and Constraints Editor. Right-Click on your screen and select "Design" and then "Rules" and perform the following steps: 1-Duplicate your clearance rules. 2-Rename it to something smug. 3-Change the priority so that it is higher than standard clearance. 4-Select your first and second object matching if you wish. I kept them both as "All". 5-Select "Same Net Only" as your constraints. 6-Select the Minimum Clearance and change it to -1. THIS IS YOUR VITAL STEP. You cannot change each individual clearance to -1. You must do it as a whole. 7-Change your clearance for Vias to whatever spacing you want. 8-Press OK.

Via to pad clearance design rule

Top Replies