RoadTest: Summer of FPGAs -- OrangeCrab Dev Bd
Author: dramoz
Creation date:
Evaluation Type: Development Boards & Tools
Did you receive all parts the manufacturer stated would be included in the package?: True
What other parts do you consider comparable to this product?: Cmod A7-35T, Arty A7-35T, TinyFPGA EX, LiteFury (for more information see section below)
What were the biggest problems encountered?: Lack of documentation in the form of tutorials or guides
Detailed Review:
Summer of FPGAs!!!
FPGAs (Field Programmable Gate Arrays) have been around for a while now, since the '80s. But I think, that finally, we have reached that moment in time, where technology has become accessible to everyone. Thanks, in part for a "new/old" FPGA open-source movement that keeps a continuous work in free EDA tools and FPGA manufacturers, that are making it "easier" for new players to go into FPGAs by offering free EDA SW and "free" community support through forums.
I started with FPGAs back in 1998 in my bachelor's degree, and since then I have been a huge fan of FPGAs. Today, I work as an RTL verification engineer - and my involvement with FPGAs has been with Intel/Altera and AMD/Xilinx since my beginnings. I have coded both in VHDL and Verilog, but my work nowadays is in Verilog/SystemVerilog with Xilinx devices.
"The OrangeCrab is an electronics development board. It is FPGA based, featuring an ECP5 from Lattice". I have never used an FPGA from Lattice, which was one of my principal reasons to apply to this road test. The OrangeCrab board is an open-source hardware and all files are available on GitHub. The repo is currently active and the author is constantly checking the issues or comments left. The current revision is r0.2.1 (which is the one used in this road test, previous revision releases are r0.1 and r0.2)
The goal is to test the main advertised features and compare it to other available options. During this road test, I will try to be as KISS as possible, but interesting enough to any level. I do not enjoy that much the "google it" approach, so I tried to put as much information as I think is unknown for the reader - therefore if you feel that something was missing or need further clarification, just let me know.
A Field Programmable Gate Array (FPGA) is an integrated circuit composed of very basic digital building blocks. Today, FPGAs internally have:
Other blocks that have become common are:
FPGAs design and implementation process usually involve:
Why use FPGAs? My two favorites reasons are:
In an oversimplification, you have ASICs and FPGAs. ASICs are fixed, you cannot add more hardware to them like more PWM ports, a new arithmetic function, and go on. Of course, you can use a general I/O to implement in firmware (FW) an extra or new communication protocol. Would it be efficient? It would depend on your application, but there is always a price to pay and a limit. FPGAs stay between FW and ASIC, so if you need faster functions or extra PWMs, UARTs, these are your possible options:
And the extras are:
And the disadvantages used to be:
OrangeCrab Dev Bd r0.2.1 top and bottom view
The OrangeCrab is an ECP5 Lattice FPGA development board. There are two different boards available. They differ in the ECP5 characteristics 25F vs 85F (#of thousands of LUTs), and DRAM 128MiB vs 512MiB (MiB-mebibyte: measure in powers of 2 vs MB-megabyte: measure in powers of 10)
The OrangeCrab board form factor is based on the Adafruit feather board specification. It was designed by Greg Davill and prototyped by GroupGets. It is currently in revision 0.2.1. The first revision was out two years ago with the latest revision being probably more than a year old.
The FPGA is compatible with all open source toolchains and is perfect for experimenting with RISC-V cores.
The board comes pre-loaded with a USB DFU bootloader (Open source), so users can load new FPGA code (bitstreams aka gateware) or RISC-V firmware directly into the FLASH without the need of an external programmer. A JTAG port is available to reprogram the FPGA directly (untested in this road-test).
Note: in the current documentation and information available about the OrangeCrab, most if not all of it, shows a picture of the revision r0.2.0 instead of the latest one r0.2.1 - nevertheless the pinout and the documentation still holds true and the only noticeable change is the JTAG connector.
Inside the ECP5, one can find the typical blocks of modern FPGAs:
A detailed summary review can be read at Lattice ECP5 FPGA architecture overview. Overall, I was impressed by the amount of features Lattice was able to pack in such a small footprint at a low cost.
I did a quick search at Digi-Key, and it seems that by specs, the ECP5 is the clear winner in cost/logic. Comparing FPGAs is a complicated task, and I did not look into power, speed or other features. Given or taken a single ECP5 cost between $8~ $18.5USD for the 25F, with the price difference in number of I/O, temperature range and speed. (https://www.digikey.ca/, Aug.26, 2021)
Here is a summary of the two ECP5 options available for the OrangeCrab. This road test was done with the 25F model.
| Device | 25F | 85F |
|---|---|---|
| LUTs | 24K | 84K |
| Embedded Memory (Kbits) | 1008 | 3744 |
| Distributed RAM Bits (Kbits) | 194 | 669 |
| 18 x 18 Multipliers | 28 | 156 |
| PLLs/DLLs | 2 / 2 | 4 / 4 |
The OrangeCrab official site is located in GitHub. As an open-source project, all the required PCB files are available. The PCB was designed using KiCad EDA. There are also STL files for a 3D printable case which I found pretty nice, and they printed without any issues.
There are links to the official OrangeCrab Web site, a set of basic examples, and a Discord group on the 1BitSquared channel for community chat and support. I did not find a forum or wiki-style website, which in my personal opinion is a better place to store the generated knowledge from a community of users rather than a chat-like discord.
The OrangeCrab Web site has a Getting Started section for the open-source toolchain. The board pinout is provided (although the picture is of the r0.2, the author confirmed that the pinout is the same and "The docs are identical to the r0.2 board, except for a connector change for the USB/JTAG, and some changes to the DC/DC circuits.")
Note: Unfortunately, at the moment the link to the OrangeCrab Web site is broken, and there is no access to further documentation. After googling around, I found the correct link to be https://orangecrab-fpga.github.io/orangecrab-hardware/. A ticket was opened and it was solved the same day, and now the GitHub points to the right URL OrangeCrab Web site.
Another nice official page is the OrangeCrab by Good Stuff Department, where there are links to some media coverage reviews and more information about the open-source code tools and IP cores. Among the several reviews, this one in hackster.io from Tom Fleet was the one worth sharing: OrangeCrab: A Formidable Feature-Packed FPGA Feather.
Interestingly, I did not find direct links to the ECP5 FPGA official Lattice documentation or the Lattice's Diamond IDE or any guide on how to use the Diamond IDE to program the OrangeCrab (Greg later confirmed that the Diamond flow has not been tested) Lattice Diamond Compatibility #41
In conclusion, the current OrangeCrab official documentation still needs work. It has not been updated to the latest revision r0.2.1(Issue #39 - Documentation for r0.2.1) as of Aug.13, 2021 (a comment was given in an open ticket in GitHub). The set of examples although useful fell short and basic. The discord channel, although active, as any online chat, tends to be messy.
As a plus, the Getting Started and a YouTube video OrangeCrab FPGA Getting Started following the guide are easy to follow.
Overall, the documentation provided by Lattice is easily accessible, complete, and easy to follow and recall - it uses a good engineering writing style.
The following table provides the links for the most relevant documentation for the ECP5 FPGA
Given the nature of the OrangeCrab board, open-source + FPGA, small community support was expected. Furthermore, although there are several players doing some work with the OrangeCrab, they are currently sharing the results but without documenting the process. For someone already familiar with the open-source FPGA-toolchain, it should be relatively easy to start working with the OrangeCrab. The FPGA-toolchain is well supported and has a bigger and wider community.
A good point is that Lattice seems happy with the OrangeCrab, referencing the board in their website and contemplating the option of incorporating the board in their tools flow (I asked this in an element14 webinar from Lattice)
Before getting the board, I did a quick google search and went over some reviews and videos. I have to confess that I was amused with what I found. After I got the board, the small size plus all the listed futures it has, make it a pretty amazing and interesting development board to play with.
It came in an electrostatic bag in a box from Newark like a regular IC or component without any further information. The board came as expected, without pinheads or any other accessories. From a point of view of a regular buyer, this is OK. However from a point of view of a tester, I got the filling of missing parts. As the board is advertised as a dev. board, I personally think that pinheads should be provided as an option at checkout - however this is a common problem with sellers - the lack of suggestions when purchasing any board or components. It would be nice to have a list of other items to purchase beforehand.
Out of the box, the board came pre-installed with a RGB blink running example, which worked as expected.
The official documentation provides an easy setup guide Getting started. There is also a YouTube video OrangeCrab FPGA Getting Started which basically follows the guide and the examples. The guide make use of the Open Source FPGA toolchain. I tested the toolchain on first on WSL-Windows10 and later in an Ubuntu 20.04 Virtualbox Machine. There are options to different OS (MacOS, Windows, other Linux distros).
I started using WSL as the latest release of the toolchain for Windows10 was on March 18, 2021. I still used the fpga-toolchain-progtools-windows* to program the FPGA. Everything worked fine in this flow, however, I decided to switch to an Ubuntu 20.04 VM with Windows 10 as host. Some comments to follow in section Testing the Tool-chain on Ubuntu as a VM on Windows 10.
The first step was to download the Open Source FPGA-toolchain, which is a collection of the required tools. Note that the FPGA-toolchain is updated nightly, but there is no need to keep it up-to-date on a daily basis. The installation went straightforward and without any issues. After installation, the toolchain worked without any issues.
I will recommend, when possible, running the FPGA-toolchain in Linux. It is possible to run up to the generation of the bitstream in WSL and then program the board using the fpga-toolchain-progtools, but it requires some extra steps that can be avoided using a Linux distribution. It should be possible to use the latest available FPGA-toolchain release, but this was untested.
# Download and install the Toolchain
cd ~
mkdir tools
cd tools
# Get the latest at https://github.com/YosysHQ/fpga-toolchain/releases
wget https://github.com/YosysHQ/fpga-toolchain/releases/download/nightly-20210915/fpga-toolchain-linux_x86_64-nightly-20210915.tar.gz
tar -xvzf fpga-toolchain-linux_x86_64-nightly-20210915.tar.gz
# Set PATH (add to .bashrc to make it permanent)
export PATH="${HOME}/tools/fpga-toolchain/bin:$PATH"
# Test installation
yosys -V
nextpnr-ecp5 -V
# Udev rule to access the OrangeCrab in Linux based systems
sudo touch /etc/udev/rules.d/99-orangecrab.rules
sudo vim /etc/udev/rules.d/99-orangecrab.rules
# copy/paste rule:
ATTRS{idVendor}=="1209", ATTRS{idProduct}=="5af0", MODE="0666", GROUP="plugdev", TAG+="uaccess"After following the Getting started guide, running all the Verilog examples was straightforward. I recommend running all of them in order while taking a look at each file to get a better understanding of the flow and the how-to to develop with the OrangeCrab.
To run the examples using WSL, the progtools are required to program the FPGA.
makeduf-bitstream file (*.duf) file to a windows directory accessible from the command prompt (cmd)cmd terminal and program the OrangeCrab:makeE:\dev\fpga-toolchain-progtools\bin\dfu-util.exe -D example.bit(set the proper path for the location of the tools)# Clone repository cd ~ mkdir repos cd repos git clone https://github.com/orangecrab-fpga/orangecrab-examples.git # Run example cd ~/repos/orangecrab-examples/verilog/pwm_rainbow/ # generate bitstream make #download bitstream # cylce power the OrangeCrab: # - disconnect the USB-C cable # - while holding the user button re-connect the USB-C cable # => The LED should be smoothly fading through different colours. make dfu # LED smoothly fades through different colours, but different from BOOT mode. Press button to view the differences
OrangeCrab - compilation, elaboration, and download of the blink example
OrangeCrab - PWM example + go into boot mode with button demo
As for the RISC-V examples, they required a different setup that was not specified in the official documentation. While trying to run the blink example, after
make all
I got the error
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -Wl,-Bstatic,-T,sections.ld,--strip-debug -ffreestanding -nostdlib -I. -o blink_fw.elf start.s main.c make: riscv64-unknown-elf-gcc: Command not found make: *** [Makefile:12: blink_fw.elf] Error 127
Before doing any RISC-V work, the required toolchain must be installed. Although the process was not documented in the Getting started guide, I was able to find the instructions on the GitHub repository Linux-on-Litex-VexRiscv, under Installing a RISC-V toolchain section.
The latest RISC-V toolchain can be downloaded at SiFive
wget https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz tar -xvzmv riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz export PATH=$PATH:$PWD/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/
Note: to preserve the PATH location to the riscv-tools, add it to your system path (~/.bashrc in my case)
export PATH=$PATH:${HOME}/tools/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/The provided examples ran without any issues.
After watching the Getting started video from FPGA Zealot, I decided to give it a try with Ubuntu 20.04 as a guest OS under VirtualBox 6.1 on Windows 10. After the VM installation process and FPGA tool-chain setup, everything went smoothly.
cd verilog_example/ make # Un-plug OrangeCrab, plug while pressing button # or if running blink_reset, blink_reset_module or pwm_rainbow simple press button # to go into programming mode make dfu
Do not forget to create the udev rule, this is a required step:
sudo touch /etc/udev/rules.d/99-orangecrab.rules
sudo vim /etc/udev/rules.d/99-orangecrab.rules
# copy/paste rule:
ATTRS{idVendor}=="1209", ATTRS{idProduct}=="5af0", MODE="0666", GROUP="plugdev", TAG+="uaccess"It is possible to program and connect directly to the OrangeCrab from the VM as a passthrough device. You have to do it twice, one for the DFU programmer and one if your gateware uses a UART (serial port).
When you run the RISC-V examples, you will notice that it is only necessary to compile the firmware. The DFU image that comes pre-loaded in the OrangeCrab contains a RISC-V 32bits implementation (VexRiscv) that is loaded in the FPGA before running the examples.
I did not find too much information of the OrangeCrab-DFU VexRiscv implementation. After some googling around I found that:
"When loading RISCV code directly as the examples illustrate, what is actually running this code is the SoC loaded into the FPGA by the bootloader. This processor is a bit limited, it currently only runs at 12MHz and does not contain a DDR3 memory controller." Greg
https://githubmemory.com/repo/gregdavill/OrangeCrab-examples/issues
I did not find an example on how to run VexRiscv with a Verilog block. Issue#35 - RISC-V with custom gateware
The first impression of the OrangeCrab was positive. The ECP5 FPGA characteristics, plus the small form factor of the board are interesting, and solely in terms of hardware and compute power is impressive.
But the lack of documentation for the OrangeCrab is hard to pass. The FPGA-toolchain is well documented, and for someone without any experience in this open-source flow, there is a learning curve but it is doable.
However, for the OrangeCrab although there are a few interesting resources and examples, a lot of information is missing. As an example, I did not find any documentation on how to integrate the VexRiscv with a Verilog design (which is a must-have for an FPGA-SoC). Therese is no documentation on how the DFU was implemented for the OrangeCrab, no API or similar.
After following the "Getting Started" Verilog examples both in Windows10-WSL and Ubuntu.20.04-VM, I decided to continue the road-test using the VirtualBox VM as the development flow was faster with fewer steps and more continuous. The flow-on other Linux OS should be similar.
The open-source FPGA_toolchain is done with YosysHQ/fpga-toolchain, which provides a full open-source flow for the ECP5, using:
It is possible to get the FPGA resources utilization from the Yosys synthesis tool when generating the bitstream. The block below shows the FPGA resources used in the Verilog - PWM rainbow example FPGA:
Info: constraining clock net 'clk48' to 48.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 265/24288 1% Info: logic LUTs: 165/24288 0% Info: carry LUTs: 100/24288 0% Info: RAM LUTs: 0/12144 0% Info: RAMW LUTs: 0/ 6072 0% Info: Total DFFs: 154/24288 0%
I decided not to go deeper into the FPGA-toolchain at the moment. Although I went a little further out of curiosity, I think there is no point for the regular user to go deeper through the rabbit hole. The open-source tools are stable, actively updated, and used/supported by different developers. And they work!
Note: The current FPGA-toolchain supports Verilog-2005 and a small subset of SystemVerilog. I am a SV developer, but so far I have been OK with the supported SV subset in the tools.
The provided examples should suffice to learn how to use the tools by looking at the Makefile(s) Both FPGA and RISC-V flows Makefile is clear enough for someone familiar with make. For RTL (Verilog) projects, I will say that the examples are enough. You will only need to update an existing Makefile with your files, generate the bitstream, and re-program the ECP5 with DFU.
However, trying to do a RISC-V SoC does require extra effort. I see two options here:
As a side note, the OrangeCrab is also fully compatible with Lattice's Diamond IDE. Note that most (or all) of the OrangeCrab available documentation float around the open-source toolchain. At the moment, the Diamond flow is untested, but in theory, it should work without issues. Issue #41 Lattice Diamond Compatibility
RISC-V (pronounced "risk-five"[1]) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains. https://en.wikipedia.org/wiki/RISC-V
The RISC-V is only an ISA, and there are several close or open-source implementations in different HDLs. One advantage of the RISC-V is that has a modular design, with alternative base parts and optional modules. The tool-chain is in continuous development, maintained by a big community, and is mature enough to provide adequate commercial and industrial solutions. These characteristics make RISC-V an interesting alternative for a soft-FPGA processor.
The VexRiscv is an open-source implementation (MIT License) available for the OrangeCrab (and other FPGA boards). Another RISC-V that I am aware of that can be used for FPGA is Vectorblox ORCA. I decided to perform the road-test with the VexRiscv as it has already been ported to the OrangeCrab board, plus there is also a Linux implementation working out of the shelf.
There are OrangeCrab fully operational VexRiscv (RISC-V 32bits) implementations, even one capable of running a basic Linux OS (Linux-on-Litex-VexRiscv)
All the open-source resources are well documented. However, again, the lack of documentation in the form of tutorials is a wall that would require some time to overcome. OrangeCrab examples run fine and are easy to implement, but they do not provide the needed information to go beyond them, especially in terms of having an SoC implementation with FPGA accelerators. If using a soft RISC-V is a requirement for a project, it would be necessary to learn Litex to get the best out of the OrangeCrab board (or get a different RISC-V/FPGA SoC flow)
As mentioned earlier, there are bitstream and Linux files that can be downloaded into the OrangeCrab and an SD card. On the 25F board version, the RISC-V runs at 64MHz.
As only the DFU (bitstream) file is provided, there is no way to do some extra FPGA accelerators integration. More detailed information of the test I did can be found at OrangeCrab: Linux on Litex-VexRiscv
Although my initial intention was to get an Adafruit FeatherWing board to do some basic tests, I did not find a justification to get one. The available boards are similar in characteristics to Arduino Shield or Raspberry Pi HAT. These ecosystems provide an easy way of stacking extra electronics (daughterboards) on top of the main board.
They would differ in size, pinout, and most important in electric voltage levels. Most of the time I do not search for daughterboards based on any form factor, but rather on functionality and electrical compatibility.
Get to know better the board I decided to code and run a simple basic example. I used the open-source FPGA-toolchain and the open-source verification tools I use at work. You can check the verification tools installation here (Open-source verification tools )
| Step | Description |
|---|---|
| Required repository | mkdir repos cd repos git clone https://github.com/orangecrab-fpga/orangecrab-examples.git |
| Create working directories | cd ~ mkdir orangcrab cd orangecrab mkdir simple_io_test cd simple_io_test |
| Copy files | cp ~/repos/orangecrab-examples/verilog/blink_reset_module/blink_reset_module.v top.sv cp ~/repos/orangecrab-examples/verilog/pwm_rainbow/Makefile ./ cp ~/repos/orangecrab-examples/verilog/pwm_rainbow/orangecrab_reset.v orangecrab_reset.sv |
| Visual Code |
|
| top.sv | `default_nettype none
module top (
input wire clk48,
// RGB LED
output wire rgb_led0_r,
output wire rgb_led0_g,
output wire rgb_led0_b,
// UART
input wire uart_rx,
output wire uart_tx,
// reset->boot
output wire rst_n,
input wire usr_btn
);
// Create a 27 bit register
logic [26:0] counter = 0;
// Every positive edge increment register by 1
always @(posedge clk48) begin
counter <= counter + 1;
end
// Output inverted values of counter onto LEDs
assign rgb_led0_r = ~counter[24];
assign rgb_led0_g = ~counter[25];
assign rgb_led0_b = 1;
// UART
assign uart_tx = (uart_rx==1'b1)?(counter[9]):(counter[19]);
// reset to boot
orangecrab_reset reset_instance(
.clk(clk48),
.do_reset(~usr_btn),
.nreset_out(rst_n)
);
endmodule |
| Makefile | PROJ=simple_project
TOP_MODULE=top
# optionally set the name of a module used for simulation, and number of cycles to simulate.
TOP_SIMULATION_MODULE=sim
# with a 48 MHz clock, this would be one ms of simulation.
SIMULATION_CYCLES=48000
# Specify hardware revision of your OrangeCrab: `r0.1` or `r0.2`
VERSION:=r0.2
# By default, we will read all verilog files (.v) in this directory.
SV_FILES=$(wildcard *.sv)
# Add Windows and Unix support
RM = rm -rf
COPY = cp -a
PATH_SEP = /
ifeq ($(OS),Windows_NT)
# When SHELL=sh.exe and this actually exists, make will silently
# switch to using that instead of cmd.exe. Unfortunately, there's
# no way to tell which environment we're running under without either
# (1) printing out an error message, or (2) finding something that
# works everywhere.
# As a result, we force the shell to be cmd.exe, so it works both
# under cygwin and normal Windows.
SHELL = cmd.exe
COPY = copy
RM = del
PATH_SEP = \\
endif
all: $(PROJ).dfu
dfu: $(PROJ).dfu
dfu-util -D $<
# We don't actually need to do anything to verilog files.
# This explicitly empty recipe is merely referenced from
# the %.ys recipe below. Since it depends on those files,
# make will check them for modifications to know if it needs to rebuild.
%.v: ;
# Build the yosys script.
# This recipe depends on the actual verilog files (defined in $(SV_FILES))
# Also, this recipe will generate the whole script as an intermediate file.
# The script will call read_verilog for each file listed in $(SV_FILES),
# Then, the script will execute synth_ecp5, looking for the top module named $(TOP_MODULE)
# Lastly, it will write the json output for nextpnr-ecp5 to use as input.
%.ys: $(SV_FILES)
$(file >$@)
$(foreach V,$(SV_FILES),$(file >>$@,read_verilog -sv $V))
$(if $(DO_SIMULATION), \
$(file >>$@,prep -top $(TOP_SIMULATION_MODULE)) \
$(file >>$@,sim -clock clk -n $(SIMULATION_CYCLES) -vcd $(basename $@).vcd) \
, \
$(file >>$@,synth_ecp5 -top $(TOP_MODULE)) \
$(file >>$@,write_json "$(basename $@).json") \
)
# Run the yosys script to synthasize the logic and netlist (in json format)
# to provide for nextpnr-ecp5.
%.json: %.ys
yosys -s "$<"
# Run nextpnr-ecp5 to place the logic components and route the nets to pins.
%_out.config: %.json
nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf .$(PATH_SEP)orangecrab_${VERSION}.pcf
# Generate the final bitstream from the pnr output.
%.bit: %_out.config
ecppack --compress --freq 38.8 --input $< --bit $@
# Add OrangeCrab's USB VID/PID to the bitstream, so it's ready for DFU xfer to the bootloader.
%.dfu : %.bit
$(COPY) $< $@
dfu-suffix -v 1209 -p 5af0 -a $@
# For the %.vcd target, set DO_SIMULATION, so the sim lines will be used in generating the .ys
# Then, run yosys with that script.
%.vcd: DO_SIMULATION=yes
%.vcd: %.ys
yosys -s "$<"
# Run the simulation to create the .vcd file, then view it with gtkwave.
# If you don't have gtkwave, you can get it from http://gtkwave.sourceforge.net/
sim: $(PROJ).vcd
gtkwave "$(PROJ).vcd"
clean:
$(RM) -f $(PROJ).svf $(PROJ).bit $(PROJ)_out.config $(PROJ).json $(PROJ).dfu $(PROJ).vcd
.PHONY: sim clean |
| orangecrab_r0.2.pcf | LOCATE COMP "clk48" SITE "A9"; IOBUF PORT "clk48" IO_TYPE=LVCMOS33; FREQUENCY PORT "clk48" 48.0 MHz; LOCATE COMP "ddram_a[0]" SITE "C4"; IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[1]" SITE "D2"; IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[2]" SITE "D3"; IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[3]" SITE "A3"; IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[4]" SITE "A4"; IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[5]" SITE "D4"; IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[6]" SITE "C3"; IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[7]" SITE "B2"; IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[8]" SITE "B1"; IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[9]" SITE "D1"; IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[10]" SITE "A7"; IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[11]" SITE "C2"; IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[12]" SITE "B6"; IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[13]" SITE "C1"; IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[14]" SITE "A2"; IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_a[15]" SITE "C7"; IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_ba[0]" SITE "D6"; IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_ba[1]" SITE "B7"; IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_ba[2]" SITE "A6"; IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_ras_n" SITE "C12"; IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_cas_n" SITE "D13"; IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_we_n" SITE "B12"; IOBUF PORT "ddram_we_n" SLEWRATE=FAST; IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_cs_n" SITE "A12"; IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_dm[0]" SITE "D16"; IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_dm[1]" SITE "G16"; IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_dq[0]" SITE "C17"; IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; LOCATE COMP "ddram_dq[1]" SITE "D15"; IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; LOCATE COMP "ddram_dq[2]" SITE "B17"; IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; LOCATE COMP "ddram_dq[3]" SITE "C16"; IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; LOCATE COMP "ddram_dq[4]" SITE "A15"; IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; LOCATE COMP "ddram_dq[5]" SITE "B13"; IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; LOCATE COMP "ddram_dq[6]" SITE "A17"; IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; LOCATE COMP "ddram_dq[7]" SITE "A13"; IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; LOCATE COMP "ddram_dq[8]" SITE "F17"; IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; LOCATE COMP "ddram_dq[9]" SITE "F16"; IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; LOCATE COMP "ddram_dq[10]" SITE "G15"; IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; LOCATE COMP "ddram_dq[11]" SITE "F15"; IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; LOCATE COMP "ddram_dq[12]" SITE "J16"; IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; LOCATE COMP "ddram_dq[13]" SITE "C18"; IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; LOCATE COMP "ddram_dq[14]" SITE "H16"; IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; LOCATE COMP "ddram_dq[15]" SITE "F18"; IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; LOCATE COMP "ddram_clk_p" SITE "J18"; IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; LOCATE COMP "ddram_cke" SITE "D18"; IOBUF PORT "ddram_cke" SLEWRATE=FAST; IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_odt" SITE "C13"; IOBUF PORT "ddram_odt" SLEWRATE=FAST; IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_reset_n" SITE "L18"; IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; LOCATE COMP "ddram_vccio[0]" SITE "K16"; IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; LOCATE COMP "ddram_vccio[1]" SITE "D17"; IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; LOCATE COMP "ddram_vccio[2]" SITE "K15"; IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; LOCATE COMP "ddram_vccio[3]" SITE "K17"; IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; LOCATE COMP "ddram_vccio[4]" SITE "B18"; IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; LOCATE COMP "ddram_vccio[5]" SITE "C6"; IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; LOCATE COMP "ddram_gnd[0]" SITE "L15"; IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; LOCATE COMP "ddram_gnd[1]" SITE "L16"; IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; LOCATE COMP "rgb_led0_r" SITE "K4"; IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; LOCATE COMP "rgb_led0_g" SITE "M3"; IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; LOCATE COMP "rgb_led0_b" SITE "J3"; IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; LOCATE COMP "uart_rx" SITE "N17"; IOBUF PORT "uart_rx" IO_TYPE=LVCMOS33; IOBUF PORT "uart_rx" PULLMODE=DOWN; LOCATE COMP "uart_tx" SITE "M18"; IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33; IOBUF PORT "uart_tx" PULLMODE=DOWN; LOCATE COMP "gpio_5" SITE "B10"; IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_5" PULLMODE=DOWN; LOCATE COMP "gpio_6" SITE "B9"; IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_6" PULLMODE=DOWN; LOCATE COMP "gpio_9" SITE "C8"; IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_9" PULLMODE=DOWN; LOCATE COMP "gpio_10" SITE "B8"; IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_10" PULLMODE=DOWN; LOCATE COMP "gpio_11" SITE "A8"; IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_11" PULLMODE=DOWN; LOCATE COMP "gpio_12" SITE "H2"; IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_12" PULLMODE=DOWN; LOCATE COMP "gpio_13" SITE "J2"; IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_13" PULLMODE=DOWN; LOCATE COMP "gpio_a0" SITE "L4"; IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_a0" PULLMODE=DOWN; LOCATE COMP "gpio_a1" SITE "N3"; IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_a1" PULLMODE=DOWN; LOCATE COMP "gpio_a2" SITE "N4"; IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_a2" PULLMODE=DOWN; LOCATE COMP "gpio_a3" SITE "H4"; IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; IOBUF PORT "gpio_a3" PULLMODE=DOWN; LOCATE COMP "usr_btn" SITE "J17"; IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; LOCATE COMP "rst_n" SITE "V17"; IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; LOCATE COMP "spiflash4x_cs_n" SITE "U17"; IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; LOCATE COMP "usb_d_p" SITE "N1"; IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; LOCATE COMP "usb_d_n" SITE "M2"; IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; LOCATE COMP "usb_pullup" SITE "N2"; IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; |
| bitstream generation | verilator --lint-only *.sv make # Set Orangecrab in DFU mode (un-plug, plug board while pressing user button) make dfu |
Adding Verilog or SV RTL to the board and doing IO connections looks like a simple task. After this road test, I am planning to add more examples and work on some basic tutorials.
For the riad test, I wanted to give it a try to the USB direct FPGA connection, but it ended being a complex project out of the scope of this road test. As a side note, I learned that for a USB peripheral, you need a unique combination of USB Vendor-ID/Product-ID (PID) - which costs USD$6000. Fortunately, there are some open hardware options (PID-codes or OpenMoko).
I wanted to do an SoC project with Litex on the OrangeCrab for this road test. But given the complexity and the time that it would be required, I decided that such an endeavor was out of the scope of this road test. I think it would be better to spend the required time and blog the results later rather than rush and present something incomplete or with the proper due diligence.
Today, they are a myriad of embedded boards where to choose from. After googling around and going through some datasheets, I think that the OrangeCrab is an excellent option. The main characteristics that stand out are:
| Name | USD$ | FPGA (LUT4 / RAM) | Form factor | MEM | URL |
|---|---|---|---|---|---|
| OrangeCrab (for reference) | $115 | Lattice ECP5-25F (24K, 1Mb) | Adafruit Feather (0.9" x 2.0") | 128MB DDR 16MB Flash | https://groupgets.com/manufacturers/good-stuff-department/products/orangecrab |
| Cmod A7-35T | $89 | Xilinx Artix7-35T (33K, 1.8Mb) | 48-pin DIP (0.7" x 2.75") | 512KB SRAM 4MB Flash | https://digilent.com/reference/programmable-logic/cmod-a7/start |
| Arty A7-35T | $129 | Xilinx Artix7-35T (33K, 1.8Mb) | 4.3" x 3.4" | 256MB DDR 16MB Flash | https://digilent.com/reference/programmable-logic/arty-a7/start |
| TinyFPGA EX | (Not Available) | Lattice ECP5-25F (24K, 1Mb) | 44-DIP (0.7" x 2.4") | 8 MB HyperRAM 16MB Flash | https://tinyfpga.com/ https://www.crowdsupply.com/tinyfpga/tinyfpga-ex |
| LiteFury | $99 | Xilinx Artix7-100T (100K, 13.1Mb) | M.2 | 256MB DDR 16MB Flash | https://github.com/RHSResearchLLC/NiteFury-and-LiteFury https://www.crowdsupply.com/rhs-research/nitefury |
The OrangeCrab is a great example of how far open-source FPGA and EDA have come through. It is a great FPGA development board. The FeatherWing form factor is small and modern. The OrangeCrab has a lot of resources, it can be used as an auxiliary accelerator/interface, or an SoC with RISC-V running Linux, which is no small feat. This board is ready for some real-world applications. Although it lacks some wireless connectivity like Wi-Fi, I can envision some nice machine learning applications or robotics among a myriad of possible applications.
However, I would not recommend this board for someone who wants to start with FPGAs. The open-source FPGA-toolchain is nice and well documented. But the current examples and tutorials available on the OrangeCrab are not rich enough to have a continuous learning curve into something that by nature is complex.
You may use it as a starting point into the realm of FPGAs and open-source hardware / open source FPGAs but it will require some time to get to know the flow before you can start a simple SoC or acceleration project.
I found interesting the USB to FPGA direct connection which simplifies the hardware. However, to be able to really use this feature, you will have to learn the LiteX flow and/or get a good understanding of the USB interface. And something similar applies to the DDR or the microSD interfaces / IP blocks.
Again, the lack of documentation and tutorials is frustrating, especially as the OrangeCrab is advertised as a development board with RISC-V and Linux capabilities.
I was already familiar with open source tools for verification, and getting to know the synthesis/elaboration tools was a plus. During this journey, I found a lot of interesting open-source FPGA EDA tools. Take a look at LiteX.
As a final comment, if your interest is to start learning about FPGAs in-depth, there are more suitable options available. Like the Basys 3 Artix-7: Xilinx FPGA, with a teach/learn design approach with free Xilinx Tools (Vivado) and videos/tutorials on YouTube and the web it would be great for beginners.
But if you already have an FPGA background and do not mind learning about LiteX/Migen or are already familiar with them, go ahead, the OrangeCrab will not disappoint. The OragenCrab is a great piece of hardware. Greg did an excellent job. I think that what you get for what you pay will meet anyone's expectations.
I hope that with time, there would be more tutorials and guides coming not only from Greg but others that have been tackling the board with some projects. Or if you are up to a challenge and want to learn about FPGA-DDR/USB/MicroSD join the team, working on any of these components while writing a tutorial should give you an excellent understanding of how any of these standards interface work.
After this road test, I want to keep learning more about the open-source FPGA-toolchain, Litex, and Migen. I will keep blogging my finding and post some tutorials in the form of step-by-step guides, which I think could benefit everyone.
I want to test the LiPo battery charging characteristics while looking more into the power requirements of the OrangeCrab.
Also, one of the biggest concerns of the open-source FPGA community, is that FPGA vendors are in a constant conflict of interest while providing free EDA tools and trying to sell the more costly FPGAs with more logic resources. Although there are out there some examples, I would like to validate this by myself.
I am planning to document these next steps here: Working with the Orangecrab Dev. Board
| Title | Comments | URL |
|---|---|---|
| element14 Road-test | - | https://www.element14.com/community/roadTests/2327/l/summer-of-fpgas-orangecrab-dev-bd |
| OrangeCrab-Hardware repository | GitHub | https://github.com/orangecrab-fpga/orangecrab-hardware |
| OrangeCrab Web site | Overview, Getting Started Guide and Pinout | https://orangecrab-fpga.github.io/orangecrab-hardware/ |
| OrangeCrab FPGA Getting Started | YouTube video | https://www.youtube.com/watch?v=tXiL-PRa628 |
| Discord OrangeCrab Support Chat | Discord group on the 1BitSquared channel | https://discord.gg/c4Dnr3b |
| ECP5 FPGA | Lattice ECP5 FPGA website | https://www.latticesemi.com/Products/FPGAandCPLD/ECP5 |
| Diamond IDE | Lattice FPGA IDE | http://www.latticesemi.com/latticediamond |
| Newark | OrangeCrab seller | https://www.newark.com/search?st=orangecrab |
| GroupGets | Crowdfunding and group buying platform OragenCrab basic info and store | https://groupgets.com/manufacturers/good-stuff-department/products/orangecrab |
| Title | Comments | URL |
|---|---|---|
| Open source FPGA resource | A list of resources in GitHub related to the open-source FPGA projects | https://github.com/os-fpga/open-source-fpga-resource |
| Open source HW Verification Tools | A List of Free and Open Source Hardware Verification Tools and Frameworks in GitHub | https://github.com/ben-marshall/awesome-open-hardware-verification |
| OpenCores | The reference community for Free and Open Source gateware IP cores (since 1999) | https://opencores.org/ |
| Freecores | More open cores | https://github.com/freecores |
| YosysHQ/fpga-toolchain | Open source FPGA-toolchain | https://github.com/YosysHQ/fpga-toolchain |
| VexRiscv | 32-bits Linux Capable RISC-V CPU written in Spinal HDL (Scala based HDL) | https://github.com/SpinalHDL/VexRiscv |
| Linux-on-Litex-VexRiscv | implementation of Linux using LiteX as the SoC builder | https://github.com/enjoy-digital/linux-on-litex-vexriscv |
| Foboot | The Bootloader for Fomu (another FPGA board) | https://github.com/gregdavill/foboot/tree/OrangeCrab |
| Title | Comments | URL |
|---|---|---|
| element14 FPGA Group | Lot of resources with a great community | https://www.element14.com/community/groups/fpga-group |
| fpga4fun | One of the oldest cool FPGAs site with some basic to advanced projects (free) | https://www.fpga4fun.com/ |
| FPGAwars | FPGAs tutorials and projects | https://fpgawars.github.io/ |
| Hack-a-day | A lot of projects in anything electronics related | https://hackaday.io/ |
| Hackster | More projects | https://www.hackster.io/ |
| nanland | YouTube channels with nice easy to follow tutorials on FPGAs | https://www.youtube.com/c/Nandland/featured |
| FPGA designs with Verilog | Verilog HDL guide | https://verilogguide.readthedocs.io/en/latest/index.html |
| Title | Comments | URL |
|---|---|---|
| Adafruit feather board specification | OrangeCrab is an Adafruit feather board | https://learn.adafruit.com/adafruit-feather/feather-specification |
