LPC4357-EVB: unable to program

Former Member over 11 years ago

I have programmed my software into LPC4357-EVB board and it became totally unusable - can't use JTAG at all.

I suspect that PLL1 initialisation was incorrect so the micro simply locks up.

The question is: How can I reprogram the board?

According to NXP spec, in order to get access to ISP I need to use USART0 or USART3.

However, on this board USART0 is hardwired to RAM and USART3 is connected to USB power protection chip.

Is it possible to reprogram the board without hardware modifications apart from soldering UART TX/RX pins?

0 aghogho over 11 years ago in reply to michaelkellett

I am using an LPC-LINK2 and a J-LINK. Both of these cannot connect to the processor core and enable jtag debugging. I don't know if ULINK will work as well as a number of people have asserted that the only solution will be to put the processor core in ISP mode.

There is a complete schematic available from element14 at http://www.element14.com/community/docs/DOC-51065/l/multimedia-evaluation-board-with-lpc4357?isRedirect=true#documents
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 michaelkellett over 11 years ago in reply to aghogho

I've never used the LPC processor but with an STM32 and a ULINK I would be able to recover by setting the ULINK to use serial wire mode debugging (not JTAG ) and to connect under reset. Just go though all the options in the Keil MDK debug setup for how the JLINK connects and see if any work. It may be that with this processor you really are stuck but it's worth a try.

MK
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 aghogho over 11 years ago in reply to michaelkellett

Unfortunately, the LPC4357-EVB only exposes a JTAG interface. Just as you mentioned, I never had any troubles using the STM32, or the KINETIS M4s. I was only attracted to the LPC4357 because it is a dual core Cortex-M4 and M0. At this point, I will tryout the suggestions from "The Rookie" above.

Thanks,
-Obi
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 michaelkellett over 11 years ago in reply to aghogho

Had a bit of a look at the data sheet - they seem to have totally stuffed the use of the SW debug in the way they have arranged the debug access to the two cores. I think you'll need to hack your way in to a USART. It's a pity the board designers didn't make this a bit easier - a couple of jumpers would do it.

MK
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 aghogho over 11 years ago in reply to michaelkellett

After much tinkering, I have been able to recovery the processor with the use of the SWD from the LPC-link2 probe. I thought the board only supported JTAG. It turns out that it does support SWD as well. Using LPCXpresso IDE, I configure the lunch configuration to use SWD instead of JTAG and voila!!.

From my observation, it looks like SWD can recovery from a bad flash image unlike JTAG. This is very useful as I was unable to configure the processor to enter ISP mode because the necessary pins were not exposed. I now have the ability to recovery from a bad flash without the use of the ISP mode.

-Obi
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 aghogho over 11 years ago

Using LPCXpresso IDE, configure the lunch configuration to use SWD instead of JTAG and voila!!.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 michaelkellett over 11 years ago in reply to aghogho

Glad you got there - thanks for sharing the solution.

MK
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel