Has anyone tried to leave the vector table of the cm0+ in flash and configure an interrupt?
By default it is copied into SRAM. No doubt about it's faster to fetch the addresses of the IRQ handlers at runtime, but I need to check if the access to SRAM by both cores causes jitter in fetching the IRQ handlers.
I tried to customize the startup file of the cm0+, but something must be inherited by the PDL such as the ram_table_address.
Thanks
