Create Project in Modus Toolbox
1. After installation of Modus Toolbox, create project is easy. First, start Project-creator in Tool Directory, choose the sample project and import into project directory.
One important setting shall be made before build process, in system parameters,CY_TOOLS_PATHS
CY_TOOLS_PATHS D:/ProgramData/ModusToolbox/tools_2.1
The backslash shall be revised accordingly in Linux-like format,or the Modus Toolbox still can not find the Tools.
2. Use PDM-PCM_Audio as example, the output shows full information in cluding memory allocation.
3. The whole UI is familiar to most Eclipse Users. Most Vendor-specific toolset use Eclipse, CCS for TI, MCUexpress IDE for NXT, and CubeIDE for ST. Therefore, quick-getting-start makes developers focus on the codes.
The code structure shall be includes LLD/HAL, BSP, and Middleware,
BSPs are aligned with Cypress kits; they provide files for basic device functionality. A BSP typically has a design.modus file that configures clocks and other board-specific capabilities. That file is used by the ModusToolbox configurators.A BSP uses low-level resources to add functionality.
Typically adds the following libraries,
- core-lib – to implement return types and generic functionality useful for any kit
- psoc6hal – to implement the ModusToolbox hardware abstraction layer
- psoc6cm0p – to add a predefined CM0+ application
- psoc6make – to implement the build system
- capsense – if appropriate for the kit
Middleware includes libraries that implement an API for a particular domain, for example capacitive sensing or an http server. A middleware library may be created by Cypress or come from a third party. Cypress-created middleware may use the Cypress HAL or an LLD directly. In that case, you need the corresponding driver library or BSP for the middleware to work.
low-level driver (LLD) contains the API and source code to configure and use a feature or peripheral on a device. ModusToolbox provides the Peripheral Driver Library (PDL) for PSoC 6 devices, or the Wi-Fi Host Driver (WHD) for CYW43xx connectivity devices. Device-specific source code and header files are included in the LLD.
In addition, Cypress provides a hardware abstraction layer (HAL). You can use the HAL for most hardware configuration.
Such combination may perplex programmer. In all, they both need finally access r/w registers bitwise, there is no difference for free choice. But not mix, except one is really master all.
There is one library missing. The access to DSP core within CM4, this is important in deeplearning engine like CMSIS-NN. This would be challenge if tensorflow-lite shall be used.