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Experimenting with Single Pair Ethernet
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  • Author Author: wolfgangfriedrich
  • Date Created: 27 Feb 2026 2:05 AM Date Created
  • Views 272 views
  • Likes 9 likes
  • Comments 13 comments
  • single pair ethernet
  • podl
  • DP83TD510E
  • spe
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SPE face-off

wolfgangfriedrich
wolfgangfriedrich
27 Feb 2026

Even before the Single Pair Ethernet design challenge started, I was pondering about making a SPE solution available for whoever is interested. Looking at the feature list, the cable length of 10baseT1L stood out more than e.g. 1Gbit over 40 meter on a single pair. So I started researching chip sets and landed on the TI solutions instead of ADI. And the chip of choice is the TI DP83TD510E.

This is not a competitive entry into the design challenge, I just want to share my work in progress. My idea is to build a simple board that works as an Ethernet extension: plug it into a network hub on one end and have 10Mb of Ethernet data rate at the other end which can be really far away. This is plenty for sensor data or even streaming audio, not so much for a NAS or other high speed data connections. 
The first step is going to be a one-board design that can be used on both ends as a media converter from regular Ethernet to SPE. As a compliant interface it would also be possible to replace the far end with a ADI or Microchip device. Low power is a design goal but there will be lower power options available, I am thinking of the SPE to SPI chip ADIN1110. Also the selected microcontroller is not famous for its low power, but something I am comfortable working with, the RP2040.

The board is equipped with an expansion connector breaking out a set of signals that might be sufficient for a Power over Dataline (PoDL) add on board, but this is just a concept for now without a design yet. Another thought I had during a shower recently, power input for the PoDL section could be done as a USB-C PD sink device. Or even better, in the meantime there are chips available that can act as a sink or source, so I could extend the single board for both ends to a PD source to power the SPE far end device and provide additional power output. But that is step 42, I am at step 3 right now. 

 The schematic is finished enough to share and I have started putting components on a board. Layout progress will be shared when I have something to show for.
 
 Please enjoy and I am very open to suggestions or even better, to pointing out any blatant mistakes I have made. 

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Top Comments

  • wolfgangfriedrich
    wolfgangfriedrich 16 days ago in reply to JWx +1
    They are mostly series termination and debug friendliness. And if I remove some of them I should be able to run this interface as RMII. They eval board is wired for RMII, which makes it a good resource…
  • kmikemoo
    kmikemoo 15 days ago +1
    Nice!!! I love the vision. I do like the PoDL thought. That would make this setup amazing. Great work.
  • BigG
    BigG 15 days ago +1
    As you have included an RP2040 in your design, I am not sure if you are aware there's a rmii library available. It's something I came across last time I looked at SPE. I believe it uses PIO. https:/…
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  • BigG
    BigG 17 days ago

    Thanks for sharing. 

    Last year I was tinkering at best but then lost interest as I don't really have a problem to solve. I had started with LAN8651 10BASE-T1S daisy chain. I even did up a design (a learn-by-doing exercise) and had some PCB's made, which I've still to populate and are now just gathering dust... then Arduino finally launched their SPE offering, which I think is much better and cleaner than mine. Maybe I'll get back to this.

    image

    In fact, since the start of this design challenge I too started looking at SPE again and in particular the 10BASE-T1L protocol (there's been some really interesting posts of late). I also started looking at that very same component, re DP83TD510E.

    I was looking at your schematic. I am curious to know why you placed those 22R resistors on the TX/RX lines (page 3). Is this a case of old habits or something in particular that you discovered here. It's not in the reference design (for DP83TD510E-EVM). It's just something I see every now and then (e.g. of SD card interfaces too). Just curious to know reasons.

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  • JWx
    JWx 17 days ago in reply to BigG

    maybe for 5V tolerance? BTW - why MII not RMII? 

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  • wolfgangfriedrich
    wolfgangfriedrich 16 days ago in reply to JWx

    They are mostly series termination and debug friendliness. And if I remove some of them I should be able to run this interface as RMII. They eval board is wired for RMII, which makes it a good resource to double-check my approach. 
    I think this is my first MII interface, so I have the option to experiment with different solutions, including the bug fix in my other response.  

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  • wolfgangfriedrich
    wolfgangfriedrich 16 days ago in reply to JWx

    They are mostly series termination and debug friendliness. And if I remove some of them I should be able to run this interface as RMII. They eval board is wired for RMII, which makes it a good resource to double-check my approach. 
    I think this is my first MII interface, so I have the option to experiment with different solutions, including the bug fix in my other response.  

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