Mirror input freq

You need to explain in  a LOT more detail what you are trying to do. I can guess but to offer some ideas I need details. This is a job not unlike one I have pending  - I expect it to take at least 200 hours of work so don't expect anyone to hand over some VHDL or Verilog that does your work for you.

You have an incoming clock at frequency A and you make an output signal B - if you just copy A to B then B stops when A stops. If you don't care much about the frequency of B and you don't care about glitches then you could just switch B to a local source when A fails.  If you need B to be phase locked to A and suffer no glitch when A fails you need to make a local clock at about the right frequency and use A to force it (by some  sort of PLL (probably digital)). If you can't accept  a glitch when A returns it gets much more exciting - because when A is absent B must drift away from lock and when A returns you'll need to slowly bring B back into sync.

So now you know why you need to specify frequency of A, drift of A, error in A, time A might be missing, frequency and drift of the local FPGA clock, are you allowed glitches, how much jitter is allowed on B and probably a few more things as well.

If you want any more help - post here again with the details, a reason you want to do it  (if it's for military stuff I won't help) and your ideas about how to approach it.

MK

Hi Michael,

Thanks for your support.

Lemme me explain what i am trying to do.

suppose we have 3 systems,  1 master: A and  2 slaves: B,C

A transmit signal over a fixed period, let say 100 Hz, and the other systems receive that signal. in the mean time before transmission it gives a reference signal to B and C so they get sync with A. this reference signal ensure that all systems have same times in their timers.

First i try this without having reference signal and i found that there is always time drift between the TX and the RX  signal due to this i could not receive properly.

then i tired with the reference signal idea it works but till B and C have reference pulse from A as soon as i disconnect the A again drift problem occur.

so i decide to generate  a copy of reference signal in my slaves. and additional question: how much DCM can support to generate low frequency below 100?

I suspect that you are going about this the wrong way - if all you need is for the slaves to be able to receive messages from the master you only need to use some kind of data encoding that can cope with the drift between the master and slave clocks.

If you answer the questions I asked it will be possible to help:

what is the drift in the master clock

what is the drift in the slave clocks

how much jitter and relative drift is acceptable

what kind of data are you transmitting (speed, amount etc) from the master to the slaves and what protocol/signals are you using ?

You haven't told me what your project is for (eg school, uni, hobby, work etc)

MK