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Help needed with VHDL program

joshua_s

Hi friends,

I have been trying to compile and synthesize the vhdl program by myself. If i checked syntax one by one, there's no problem (no error). But, when i try to synthesize, the result always not successful because there's no syntax in frame buffer module.

image

image

 

Then i went to my friends for help and  adding an "IP Core" to my project for the frame buffer is what they asked me to do. In addition, they also asked me to go back to the nuts and bolts of the basic concept like Basic Introduction and Design flow of Programmable Logic Device FPGA (If you are also need to pick up this, you can check it out here: http://www.apogeeweb.net/article/67.html)

Fortunately, things are going up like i see, i have succeed generate ip block memory and also succeed compiling the program.

image

I've tried to connect all the components with hamster code, but the result at monitor lcd tv is "format invalid" or "no signal", then when i compiled the code, there are many warnings. So, i am looking for help about how to fix this problem. Then, i also want to know about what is "IP Block Memory Generator".

image

I am using OV7670 camera module and Nexys 4 FPGA Board. And i don’t know how to connect OV7670 to Nexys 4 board.

 

 

Thanks in advance,

Joshua

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  • 0

    Your pictures of code on screens are too low a resolution to be readable so I can't read them.

     

    Generally the way to do this stuff is:

    1) get data sheets of everything and work out how to connect together.

    2) work out the signal processing

    3) draw some kind of block diagram and write the 'code' for each block in VHDL or Verilog.

    4) test the blocks independently in a simulator

    5) put all the blocks together into a complete design and simulate that

    6) only when the simulation is working correctly then synthesise the design and load it onto real hardware

     

    Step 5 is pretty much essential - if you are very experienced or doing really simple stuff you might get away without but in your case you will NEVER get this to work without simulation.

     

    Most people confronted with a Nexys4 board start with a simpler problem try making a stopwatch on the 7 segment display as a starter project

     

    Which version of Viavado are you running ?

     

    MK

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  • 0

    Your pictures of code on screens are too low a resolution to be readable so I can't read them.

     

    Generally the way to do this stuff is:

    1) get data sheets of everything and work out how to connect together.

    2) work out the signal processing

    3) draw some kind of block diagram and write the 'code' for each block in VHDL or Verilog.

    4) test the blocks independently in a simulator

    5) put all the blocks together into a complete design and simulate that

    6) only when the simulation is working correctly then synthesise the design and load it onto real hardware

     

    Step 5 is pretty much essential - if you are very experienced or doing really simple stuff you might get away without but in your case you will NEVER get this to work without simulation.

     

    Most people confronted with a Nexys4 board start with a simpler problem try making a stopwatch on the 7 segment display as a starter project

     

    Which version of Viavado are you running ?

     

    MK

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