Lab 1 is very simple and helps you get familiar Zynq MPSoC hardware platform. Avnet uses a pre-built archived hardware platform to show you the ropes. They use an HDF file, which I have never seen before. The file is written out from Vivado. It contains the information needed to develop software application with SDK. A couple the files in the archive included an html used by Xilinx that acts as a datasheet for the HW platform and hwh file in XML format that contains information the SDK uses to build the board support package. Least I forget they SDK uses a tcl script in the to ultimately build the bsp.
Contents of the HDF archive
drivers (folder)
This folder contains TCL file for generating parameters for the custom PWM IP driver
design_1.hwh
Hardware Hand-off file consists of XML code that will be used by SDK to create a BSP.
design_1 _bd.tcl
TCL file to re-create the ZU+ MPSoC Block Design
design_1_wrapper.bit (<project>_wrapper.bit)
This is the PL configuration bitstream. This file is used to configure the PL, which gives the PL its function and identity. ‘design_1_wrapper’ is the name of the top-level HDL file that the hardware designer used.
psu_init.c
C code file defining all the register settings to properly initialize the ARM processing system. Used to create the First Stage Boot Loader (FSBL) executable.
psu_init.h
Header file used with psu_init.c which is also used in the creation of the FSBL.
psu_init.html
Information file that describes how the ARM processing system is configured in this hardware platform and what all the register settings are. This is the best file for a software engineer to first examine as it is the ‘datasheet’ for the hardware platform.
psu_init.tcl
This is the equivalent of psu_init.c, but in TCL format. This file performs the ARM initialization when using SDK in JTAG mode, such as when debugging.
psu_init_gpl.c
Identical to psu_init.c, with the exception of the header which highlights the GNU General Public License
psu_init_gpl.h
Identical to psu_init.h, with the exception of the header which highlights the GNU General Public License
sysdef.xml
System Definition XML, containing parameter definitions for each file contained within the archive
2. How to import a pre-built Zynq Ultrascale+ MPSoc hardware platform.
The hardware platform s the equivalent of a datasheet for a processor. It gives you information about the peripherals, address map, datasheets to peripherals and system block diagram.
Lab 3 taught me:
1. How to generate the standalone BSP. A board support package (BSP) is a collection of libraries and drivers that will form the lowest layer of your application software stack. Your software applications must link against or run on top of a given software platform using the application programming interfaces that it provides. Therefore, before you can create and use software applications in SDK, you must create a board support package.
2. Where to find device drive datasheets
3. Where to find example code
Lab 4 taught me how to:
1. Add new software applications to SDK
2. Use example code to target the UART in a Hello World application
3. Apply example project templates such as memory tests and peripheral tests
4. Identify application code size and location
5. Modify linker scripts to change the target memory location
I use the Intel Quartus FPGA design tool at work and must say I am thoroughly impressed with Vivado so far. I will go on to say that Vivado was well thought out and seemed to be designed with "dummies" in mind. There is huge amount of documentation and examples that assists the average user to get up and running quickly with the tool. I know I have an advantage since I do this for a living but will say that compared with Intel's Quartus an engineer or hobbyist with some FPGA background will be able to get up to speed quickly with Vivado using their simple layout and documentation.
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