In this lab I expanded the block design by extending the memory space with a PL-based Block RAM (BRAM). The BRAM was used to buffer data going between the PS and PL. I learnt how to:
• Add a BRAM from the IP Catalog
• Connect AXI peripherals to the Zynq MPSoC PS.
You add IP using the + or ADD IP option from the menu.
The IP is called an AXi BRAM. It was configured for the Ultra96-V2 hardware.
One of the good things about Vivado is that it has a alot of automation. When you add IP to the block design you can have the tool auto- connect the IP in the block diagram. The care is taken in configuring your IP as the tools seems to connect you IP based on the configuration settings of each. Vivado is also intuitive enough to add IP you may have left out when you have it do auto-connect. For example, the BRAM needs a controller which the tool added and connected correctly.