IP created is tested via simulation as well as in hardware. Embedded designs like Zynq MPSoC requires software to be written to test IP. The LogiCORE IP JTAG-AXI core was added in a previous last lab and the core was customized. It can generate AXI transactions and drive AXI signals internal to the MPSoC at run-time. It was used to test the IP. The JTAG-AXI core uses the Vivado Logic Analyzer and pre-built software was used to validate our test. The software application included an Interrupt Service Routine (ISR) that processes interrupts from the custom PWM IP.
In this lab I learnt how to:
• Perform run-time interactions with IP cores
• Run software that handles PL-generated interrupts and utilizes an ISR
The Vivado Logic Analyzer proved to be a valuable tool. When debugging and FPGA in hardware you are left with two choices. You can route signals to test points outside of the FPGA or you can use the internal Logic Analyzer (LA). While both methods are not perfect they do have their advantages. However, I prefer the LA as a larger number of signals can be monitored.
