Path II Programmable - An Introduction
Continuing from where Path to Programmable left us with Zynq-7000 training, it's time to explore Zynq UltraScale+ MPSoC with Path II Programmable!
Zynq UltraScale+ MPSoC follows in the footsteps of Zynq-7000 with a more powerful PS, and a larger & faster PL - learning how to use it is going to be very interesting.
The Training Material
The course content that Randall shared seems to be the same as the 3 introductory Ultra96 Technical Training Courses by Avnet:
- Introduction to Zynq UltraScale+ MPSoC Hardware
- Developing Zynq UltraScale+ MPSoC Software with Xilinx SDK
- Integrating Sensors on Ultra96 with PetaLinux
Each of the courses comes with video lectures, lab instructions, supporting documents and solutions (project files).
The total download (all 3 courses) was close to 9GB. Add this to the size of the virtual disk of the VM (150+ GB), and people (like me) with 256GB SSDs need to start moving files around!
| {gallery} Introduction to Zynq UltraScale+ MPSoc Hardware |
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| {gallery} Developing Zynq UltraScale+ MPSoC Software with Xilinx SDK |
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| {gallery} Integrating Sensors on Ultra96 with PetaLinux |
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The Hardware
Element14 (and Xilinx & Avnet) sent over the hardware and accessories needed for the course
- Avnet Ultra96v2 development board
- Ultra96 USB-JTAG/UART Pod
- Power Supply
| {gallery} Ultra96v2 |
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Path II Programmable Training Hardware |
Ultra96v2 teardown |
Booting the Ultra96v2
I flashed the microSD with the Avnet's Ultra96v2 OOB image, plugged in the JTAG/UART pod, the power & hit the power button.
The Ultra96 started its boot process - a couple of LEDs and the fan (a bit too noisy!) turned on.
Connecting the Ultra96 to my WiFi network took a couple of attempts and required some troubleshooting. Once I was connected, I navigated to the IP address of the Ultra96 and was greeted by the home page (this can also be done by connecting to the hotspot of the Ultra96). The homepage has a couple of demos - one of which lets you control the LEDs.
I downloaded the board definition files & constraint file for the board and created an empty project in Vivado.
Vivado's hardware manager detected the JTAG dongle and the Zynq MPSoC:
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