This week has been more productive than the last since much of the first week was spent configuring the development infrastructure. I have completed the 10 HW videos (lectures) and the 9 HW labs and the 12 SW videos and 11 SW labs. I use the term "completed" somewhat loosely because a couple of the labs (HW 8 and SW 11) use the mezzanine board kit which we did not receive so I went through all the steps but could not verify the results on the hardware other than through the debugger. And I had a couple of other problems that I'll elaborate later. With 10 of us taking this course I think there will be lots of illustration of the course material, so I think that I'll focus on what I'm getting out of the course and the issues that I've encountered.
The objectives for the introductory Hardware course are:
Use the Xilinx Vivado and SDK tools to
- Design a Zynq UltraScale+ MPSoC system (Ultra96-V2)
- Add Xilinx IP as well as custom IP
- Run software applications to test IP
- Debug an embedded system
The first 3 lectures provided an overview of the hardware - the Zynq MPSoC Processor and its peripherals. Other lectures cover the memory system and the interconnect between the Processing System (PS) and the Programmable Logic (PL) and the peripherals using the Advanced eXtensible Interface (AXI). I have to admit that after a couple of weeks that my head feels like it is about to explode with all these acronyms 
. After a while I guess it will just seem natural. The array of hardware options is amazing. One of the main issues is making sure that you can utilize a given set of hardware options without violating any interconnect or memory constraints. A simple example is that there are a fixed set of external IO pins and they are divided into high performance and low performance categories and there are pins dedicated to the PS (Muxed IO - MIO) and to the PL (Extended Muxed IO - EMIO).
Here is a slide showing restrictions on low speed IO connectivity. Certain peripherals can only connect to MIO and in some cases only on specific pins.
The good news the design tools will prevent you from making errors, the bad news is that until you get familiar with the constraints you could end up planning unworkable designs.
There were a couple of lectures on using TCL (Tool Control Language). TCL is and interactive and interpreted language that has been extended by Vivado to allow you to do all of the GUI functions on the command line. It also allows you to create scripts so that you can build and deploy projects without the GUI by using batch mode or an interactive shell very much like Python. As a matter of fact when you execute commands through the GUI you can see them execute in the TCL Console window. It's been a long time since I've been exposed to TCL. Good to see that it is still being used and extended.
There was a lecture about using Xilinx IP or even your own custom IP (Intellectual Property refers to preconfigured logic functions that can be used in your PL design). In the lab a custom IP was built and deployed to the hardware. It is nice that this process is reasonably straightforward. It allows the ability to conveniently reuse your own designs. This was a lab that caused me an issue when I was trying to generate the bitstream for the design with the included IP.
This error happened after the synthesis step when the implementation was being optimized. It appears that this error is caused by a version mismatch between the version of Ubuntu that I was using and the 2018_3 versions of the Xilinx tools. Adam Taylor told me that the 2018_3 tools are compatible with Ubuntu 16.04.3 and 16.04.4. I am using Ubuntu 16.04.6. I have seen complaints in the forum with the same issue using 16.04.5. Somewhat amusing because I took care to use 16.04 and 2018_3 rather than 18.04/10 and 2019_1 to insure that I wouldn't have problems with this course. I did not realize that I needed to watch for the minor version also.
The hardware course was a great introduction to Vivado and SDK and the MPSoC hardware. I thought it was very thorough although there were a few minor glitches in the lab documentation. I hope that all this knowledge will stick. I'm sure I'll be back looking at this material when I'm trying to figure out a design on my own. I'll cover my thoughts on the SW course in another post.
One general issue worth mentioning - the Xilinx tools place a large resource demand on the computer they are installed on. Not sure if this is a lot worse because of using an Ubuntu Virtual Machine on Windows 10 rather than just running on a Linux computer. For various reasons I ended up using a somewhat under-powered computer - an I3 with 8GB of memory with a 1TB disk. I expected that things would run slow (which they do), but I am also having some functional issues. I initially allocated 4GB of memory to the Virtual Machine but I would intermittently get "out of memory" errors that would crash Vivado. I upped the allocation to 6GB which only left 2GB for Windows. That seems to help but I still get occasional Vivado "out of memory" errors and occasional Linux errors. And I've noticed that every now and then the SDK will hang when it is starting. So, make sure you have sufficiently robust compute power and they also recommend at least 300GB of disk space for the VM.
Next week I'm going to try moving to another computer, an I7 with 16GB of memory. Unfortunately this wasn't available when I started. I am also going install Ubuntu 16.04.4. I hope that switching the Xilinx tools license to the new box won't be too painful. Haven't tried to request that yet.
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