Introduction

First of all, thank our sponsors Xilinx and  Avnet for offering this Path II Programmable training opportunity. Also thank rscasny for selecting me as one of the trainees.

In general, the training material is great. It contains 29 video lectures, 26 lab instructions and reference solutions for three course modules: Zynq UltraScale+ MPSoC hardware, software and PetaLinux. Personally, I think it would be perfect if the lectures could dig a little bit deeper. In addition, it would be great if the transcripts of lectures are provided. Maybe just personal preference, I find listening to the lectures doesn't give me much time to digest the content. Transcripts could be a good supplement for deep diving into the content (I guess one can watch the video lecture over and over to deep dive too).

Lab 0 - Pr-requisite

Lab 0 is a pre-lab for each course. Basically it guides the trainee on how to install the development environment. It takes a quite lot of effort to install the virtual machine, Ubuntu and Xilinx tools and software. However, with the help of the lab instruction and the document titled Oracle VM VirtualBox Installation Instructions for Windows and Linux Virtual Machine Creation Targeting Avnet Development Boards, the process went pretty smoothly. After you've done all installation, you should see something similar to the following screenshot.

Another thought about VM vs Linux host: even though the pre-lab instructs using Linux guest OS in a VirtualBox VM, I think people should be able to use a Linux host OS for this training too.

Problem of Xilinx JTAG + Serial [0700]

Please note that the Digilent USB Device [0900] mentioned in Oracle VM VirtualBox Installation Instructions for Windows and Linux Virtual Machine Creation Targeting Avnet Development Boards doesn't apply to Ultra96 USB-to-JTAG/UART Pod we are using for this training. It should show as Xilinx JTAG + Serial [0700] instead. I did encounter one problem during this pre-lab: I couldn't shift the device from the host to the VM. It turned out that I have to remove an PC application called Wireshark.

HW Lab 1 - Inconsistent Folder Format

As mentioned in Lab 0, we use Linux OS, but in page 5, Experiment 1 General Instruction: Launch Vivado 2018.3. Create a New project in the Avnet Technical Training Course directory. C:\Avnet Technical Training Course\ZynqHW\2018_3\

This is a Windows folder structure which doesn't make much sense. Maybe just a copy and paste typo.

HW Lab 2 - Tip for Mapping I/O Pins

Here's a tip I learned

When designing a new board and mapping out the I/O, a designer should start with this peripheral selection and I/O configuration to see what reasonably works. Start with your boot device (under Low Speed Memory Interfaces) and then add in your High Speed interfaces that cannot be connected to EMIO like USB (EMIO refers to mapping the processor’s Peripheral I/O through the PL).

Another thing found: the following screenshot is a little bit confusing:

HW Lab 3 - Probably Missing a Step

There's one thing didn't work as per the lab instruction ( Lab 3, Experiment 3, Step 11):

After click Run

I got the following error message:

I retried a couple of times and it always gave me the same error message. Then I reset the board by pressing Reset button on board which didn't solve the problem.

I had to unplug USB cable then plug back in. It solved the problem and got the correct output.

HW Lab 6 - Slightly Different Conclusion

I have slightly different opinion about following statement excerpted from page 13 (Lab 6, Experiment 1, Step 22)

You observed that DMA is considerably improved for blockRAM compared to DDR because the transactions to blockRAM are across the AXI interconnect and blockRAM is operating at a slower speed.

In my opinion, DMA improved DDR data transfer (173x) even more than it does for blockRAM (164x) based on the measurement results shown in the following screenshot. I do agree the blockRAM is operating at a slightly slower speed than DDR4 does.

Summary

So far, I have watched all HW and SW lecture videos once, but I think I will watch a few more times. This training is great and I've learned so much from it. I really enjoyed the videos as well as labs. I haven't really encountered big obstacles during my training so far. If any other trainee needs help for HW lab 1 to 6, I am more than happy to help. Just drop a line in the comment area.