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Path II Programmable
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Path II Programmable
Documents Path II Programmable: Trainees Announcement
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  • Author Author: kabhari
  • Date Created: 3 Oct 2019 4:10 PM Date Created
  • Last Updated Last Updated: 22 Nov 2019 3:34 PM
  • Views 307 views
  • Likes 14 likes
  • Comments 27 comments
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Path II Programmable: Trainees Announcement

Path II Programmable

About Training Project | Mentors | Terms & Conditions | Trainees Announcement

 

Welcome to the Path II Programmable Trainees Page!

The Path II Programmable training project will train ten element14 members by providing them with free FPGA/SoC training modules with lab exercises. Once the training has been completed, the trainees will build a project with the Avnet Ultra96-V2Ultra96-V2 development board. In return for both the FREE training and the Ultra96-V2Ultra96-V2 development board, the five trainees will blog weekly to report on their progress, covering both the high points and the challenges of learning the Ultra96-V2Ultra96-V2.

Due to receiving so many high quality applications, element14 has decided to increase the number of trainees from 5 to 10.

Please join us in congratulating the 10 Trainees!  We look forward to reading all of their initial blogs and seeing their projects after the training.


Philip Kasavan | Antonio Rios | Avner Fernandes | Cary Smith | Charles Mao  | Ian Johnston |  James O'Gorman | Ralph Yamamoto | Vladislav Rumiantsev


gasinthevan

USA

Design Engineer - Mechanical / Electrical Focus

Bio: Philip Kasavan is an design engineer - mechanical / electrical focus.

Interest in the training: "I have experience working with FPGAs and microcontrollers/processors separately, but I haven't had many opportunities to work on projects which combine both on one device."

Philip Kasavan's project blogs


jarios86

Spain

Computer Engineer

Bio: Antonio Rios is a computer engineer.

Interest in the training: "I am working on a deep learning accelerator for CNN and DeltaRNN, in order to develop a custom hardware to parallelize the computation of the deep learning algorithms to achieve a high computing throughput, low latency, high efficiency, and low power consumption."

Antonio Rios's project blogs


avnrdf

India

Student

Bio: Avner is a student.  His Community participation has included: Design Challenges, RoadTests, blogs, discussions, and videos.

Interest in the training: "I've been interested in trying out the Ultra96 platform & the PYNQ framework, as the PYNQ overlays allow the FPGAs configuration to be swapped out on the fly using partial reconfiguration, which is great for prototyping."

Avner Fernandes's project blogs


buffteethr

USA

Electrical Engineer

Bio: Cary is an Electrical Engineer with over 20 years experience designing Analog and High-Speed Digital electronics. He has experience with FPGA design and verification, C/C++, DSPs, and Arm processors.

Interest in the training: "A training program like this with deadlines will be the perfect motivation I need to get back into designing with Xilinx and getting familiar with the Vivado design tools."

Cary Smith's project blogs


cmelement14

USA

Engineer - Research & Development

Bio: Charles Mao is an engineer - research & development.

Interest in the training: "I think this training program is a perfect opportunity for me to overcome some challenges and make me comfortable with Zynq MPSoC Systems for my future job projects, such as autonomous driving, etc."

Charles Mao's project blogs


ianrj

UK

Electrical Engineer

Bio: Ian Johnston is an electrical engineer.

Interest in the training: "I enjoyed FPGA related work while I was at university but, as my company is small and lacking in FPGA expertise I haven't had much chance to use or expand on these skills since I left university."

Ian Johnston's project blogs


aspork42

USA

Engineer - Research & Development

Bio: James is an engineer in Research & Development. His Community participation has included: being a Design Challenge winner, posting discussions, and blogs.

Interest in the training: "Path to Programmable 1 was my first time around with these devices. I hope to dive deeper this time. I have programmed FPGAs and PLDs at work; but just downloading the official software releases and not doing my own coding and creating IP."

James O'Gorman's project blogs


ralphjy

USA

Electrical Engineer

Bio: Ralph is an electrical engineer.

Interest in the training: "I would like to learn the lower level hardware programming flow using Vivado, and I think this course would be the ideal vehicle for that.  I'd like to get more experience developing custom overlays for FPGAs."

Ralph Yamamoto's project blogs


vladrumyan

UK

Electrical Engineer

Bio: Vladislav is an electrical engineer.

Interest in the training: "I am very keen to gain more knowledge and experience in working with systems that include both PL and PS. Until now, I have mostly worked with them separately."

Vladislav Rumiantsev's project blogs


Interested in following along with the Trainees? Here's how:

Follow their posts to learn more about the FPGA/SoC. You can purchase the Ultra96-V2Ultra96-V2 to recreate the projects of the trainees and feel free to comment.

 

Good Luck Everyone!

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Top Comments

  • gecoz
    gecoz over 2 years ago +5

    Congratulations everyone! Looking forward to read about your learning experiences.

  • 14rhb
    14rhb over 2 years ago in reply to fstuff +5

    Perhaps there will be a Third Path to Programmable in the future.

     

    The chosen members will over the coming months be blogging their progress and I encourage you to read through those as there will be ten…

  • buffteethr
    buffteethr over 2 years ago +5

    Congratulations to my fellow trainees. I am looking forward to working on this with everyone.

  • dieseltech69
    dieseltech69 over 2 years ago

    Congratulations all! Good luck in your training, and build some cool projects!

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  • yosoufe
    yosoufe over 2 years ago

    I am feeling jealous

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  • dcsoutherner
    dcsoutherner over 2 years ago

    My hardware just arrived.

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  • dcsoutherner
    dcsoutherner over 2 years ago in reply to buffteethr

    I'm not trying to promote myself (truthfully), but here is a link to the Road Test I did with this board's predecessor.  It has pictures, step-by-step instructions, boring commentary and opinion, but it will help with an introduction to the toolset.

    Avnet Ultra96 Dev Board - Review

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  • weiwei2
    weiwei2 over 2 years ago

    congratulations

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  • prashanth.nagendrappa
    prashanth.nagendrappa over 2 years ago

    Congratulations to the Trainees Path II Programmable is a great path to explore Zynq MPSoC.

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  • dougw
    dougw over 2 years ago

    Congratulations. Its back to school time...

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  • buffteethr
    buffteethr over 2 years ago in reply to ralphjy

    I am a FPGA designer but I use Intel devices and their Quartus Prime software. I used The Zynq Book Tutorials to learn the Xilinx/Vivado tool flow; which buttons to press and their design methodology. However, you are right if someone does not have a lot of experience with FPGA design and the tools it may be helpful to wait on the training modules as they match the board they would use.

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  • ralphjy
    ralphjy over 2 years ago in reply to buffteethr

    I'm going to wait for access to the training modules.  Sometimes getting a headstart can be counterproductive unless the material that you use matches the hardware and software versions used in the training.  Just my experience.  I'm not familiar with the "The Zynq Book Tutorials for the Zedboard".  I'd be interested in how you useful you find it.

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  • buffteethr
    buffteethr over 2 years ago in reply to ralphjy

    Thanks. I am doing the The Zynq Book Tutorials for the Zedboard so that I can get familiar with Vivado. I figured we wouldn't get the board for another week after we go through the training modules first before even attempting the labs on the board.

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