Here I am with my first blog post for the Path to Programmable III challenge. First, I would like to thank Element 14 for selecting me to be part of this design challenge.
I am looking forward to exploring the training materials and to building a project. My background is primarily in analog design with some experience in embedded design. In the past I have built projects on SoC FPGAs, but only implemented in the programmable logic (PL), none of the projects have used the processing system (PS). So I am looking forward to the training part of this challenge not for the goal of winning the design contest but primarily with the goal of gaining technical skills for building projects that use both the programmable logic and the processing system of FPGAs. (winning will be among the experienced FPGA designers in this competition; I am only a beginner in the FPGA design so I am looking for the learning part)
The first exciting event was the acceptance email from Element 14. Following this, the next exciting moment was the receiving of the MiniZed kit. I wanted to capture the event in some pictures, and here they are showing the package content:
With a lot of enthusiasm, I started the training. I felt like a great opportunity in this design challenge to participate in the training first and then to apply the knowledge and skills to the design challenge project. Though, soon my enthusiasm started to cool down as I more and more realized that I am actually “road testing” the training course instead of participating in it.
I have some experience in teaching from my work as part time instructor and UCLA Extension. I have developed a few courses and I am currently teaching them.
In my view of teaching courses build-up knowledge and skills on top of a foundation similarly to how construction buildings are created. In my opinion, a successful course development should be aware of the foundation knowledge level of the participants and then it should add knowledge and skills “brick-by-brick” until the entire building is complete.
Well, I have seen none of this in these three training courses. The material is presented all at once overwhelming the student and then there is a lot of jumping around here and there in the features of the Xilinx tools with skipping some of the items and stopping at others. Examples are preloaded and most of the time the training steps “magically” fall into place; however, if I try doing something different, I feel back at the “square one” learning level.
I hoped this training would take me step by step to create a working project "from scratch" even a very simple one like for example to just toggle an LED, but it didn’t happen that way. I believe the course has been developed by an experienced designer who may have forgotten the first steps that he or she has taken at the beginning of the career.
So, if these training courses are meant for beginners, then I think they need to be completely redeveloped from the perspective of a novice person who starts with a very simple project “blank page” and learns “layer by layer” without skipping any step until the project is ready to be loaded in the FPGA board and then it is tested. These are my overall thoughts as I started to write this blog.
Let’s go back now and follow the training sequence:
The training consists of three parts: software training, hardware training, and PetaLinux training. The software training covers using the Xilinx Vitis tool to program the processing system (PS) of a system on chip (SoC) FPGA, the hardware training teaches how to use the Xilinx Vivado tool to create a hardware project in the programmable logic (PL) part of an SoC FPGA, and the PetaLinux training teaches building embedded Linux projects for the MiniZed board. The training courses are recommended to be taken in this order: software, hardware, and then PetaLinux, so I started first with the software training.
First lab, Lab 0, has guided me to installing an Ubuntu Linux virtual machine on a Windows computer. I didn’t fully understand the reason but what I've got is that the tools work only on certain versions of Ubuntu, and this virtual machine would create a mode of operation for the windows computer that would function like the Ubuntu 18.04 version. Based on the lab instructions I have figured out that the process of installing this virtual machine is very complicated and with some risk since I would have to make some changes in the computer bios system.
Even the lab instructions mention that the virtual machine installation is complicated:
And the big problem that I see for myself, is that if the virtual machine messes up my computer there are no instructions on how to uninstall it. The un-installation I assume is quite complicated too since the memory allocation in the hard drive has to be un-done and the changes in the computer bios have to be undone.
So I took the decision to use a separate computer for the PetaLinux part of the training and design challenge, which I will setup up with a separate hard drive and on which I will install directly Ubuntu version 18.04. To get some confidence that this approach will be similar to the virtual machine, I have posted a question on the Element 14 bulletin board. As usually, a response came very quickly, and it confirmed that my proposed work around is a good approach and it has chances of success. Thanks to Element 14 prompt response of our members; this system is very beneficial to all of us.
Lab 0 instructions contain some useful references to technical support for Xilinx tools and for the MiniZed board, which I liked as they gave me confidence that I know where to go and ask questions if I need to.
Next, I moved to Lab 1. Lab 1 didn’t do anything special; only it took students through opening an existing project in Vitis tool and exploring the files' structure. I have spent some time in this activity, though the instructions are structured more like a reference document than a step-by-step teaching process. I was a bit disappointed, but I in the end I felt that I have benefited significantly from exploring the Vitis tool. The lab 1 instructions ended with a quiz, which I liked since it brought me closer to a teaching environment.
This was a short lab, so I moved to the Lab 2. This lab teaches how to setup a Vitis workspace and how to import a pre-built hardware platform. This was the most confusing training lab so far, as it has introduced the concepts of “workspace”, “hardware platform”, “platform project”, “hardware platform specifications”, “system project”, “board support package”, “peripheral set”, “address map”, and a few others in an ”amalgam” of everything mixed up "in a boiling pot" and jumping around to explore some of the items, skipping others, and while pointing to various external support documents. After this training lab I was totally confused, so I looked for external materials on the Internet. To clarify these concepts, I had to draw a diagram with my personal understanding of the project structure in Vitis. I went through a few iterations until I clarified the project workspace structure and all the concepts introduced in this lab. Part of this confusion was also that there was a Vitis tool already installed on my computer but after starting to use it I discovered that this is a different tool than the Vitis used in the training labs. Searching the Internet, I discovered that I am not the only one who was confused about the two versions of the Vitis tool:
While installing Vitis I noticed and selected the option “Vitis IP Cache (Enable faster on-boarding for new users)”. That was me so I was happy to see such a feature. Though, so far I haven’t noticed the benefit of it, but I am hopeful to see it later. I also don’t know how things would have been if I didn’t check the box for this feature.
So that was my experience with Lab2. I am looking forward to starting Lab 3. I will cover that lab and the following ones in my next blog post.
Until then, all best wishes to the readers and the rest of participants.
Cosmin
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