P2P3 Blog3 - Understanding Minized demonstration example hardware design

Understanding Minized Hardware Design
 
 
The Minized board was pre-configured with a demonstration project that showcase its capabilities and provide users with a starting point for their own projects. This example design demonstrated a fully working system that had Bluetooth, Wifi, gpios, leds, audio to control an led etc. The design also demonstrated how to use the key features of the board and often leverages the Zynq 7Z007S SoC's FPGA fabric and Arm Cortex-A9 processor. Eventhough the the example design got me going to test the board and its features, I wanted to delve deeper into the Minized example design and the hardware and software tools used to create it. Based on my reading and understanding, I can provide a general overview of how an example design typically works:

1. Project Setup:
The example design is created using FPGA design and embedded software development tools. AMD Vivado is commonly used for FPGA/SoC design, while Vitis and Petalinux are used for embedded software development targeting the Arm Cortex-A9 processor on the Zynq SoC.

2. Hardware Description:
The FPGA design portion of the example typically describes the hardware connections and functionality using a hardware description language like VHDL or Verilog. It sets up various components, peripherals, and interfaces within the FPGA fabric. Nowadays, there are higher level abstraction in terms of blocks and the blocks can be interconnected using tcl scripts. Vivado is then used to synthesis, implement, place and route, generate bitstream and export the xsa file that is given to software developers.

3. FPGA Configuration:
The FPGA configuration file, often referred to as a "bitstream," is generated based on the hardware description. This bitstream is used to program the FPGA fabric with the desired design, effectively defining how the FPGA logic will behave.

4. Processor Software:
The Arm Cortex-A9 processor on the Zynq SoC requires software to run and control various functionalities. The example design includes this software, which is typically written in C/C++ or other compatible programming languages.

5. Firmware Loading:
When the Minized board is powered on or reset, the Zynq SoC's internal boot process takes place. Refer to my previous blog about the Boot modes to understand futher about this topic. The boot process can be configured to load the FPGA bitstream and the processor software into memory.

6. FPGA Initialization:
After configuration, the FPGA fabric is initialized according to the loaded bitstream, configuring the hardware to perform the required functions.

7. Embedded Software Execution:
Once the FPGA is configured, the embedded software running on the Arm Cortex-A9 processor takes control. It can interact with the FPGA fabric through memory-mapped registers and other communication mechanisms.

8. Example Functionality:
The example design may demonstrate various functionalities, such as driving LEDs, reading buttons, communicating over UART, accessing external memory via the micro SD card slot, or performing audio processing etc.

9. User Interaction:
The Minized example design often includes code for user interaction, allowing users to observe the board's behavior through different interfaces, such as led changing colour based on audio intensity (in Minized) or UART communication.

The one thing that certainly interested me was to understand how the micrphone was interfaced to the LED's and the wireless (WiFi and Bluetooth) interfaces.
So I looked further into the design and see if I can find futher information.

I am trying to take a top-down approach into understanding how the design works.

Below are the steps I followed:

1. Find the design files to generate the design:

As I was reading through other blogs, I came across other participants who were on similar path to find the source file.
And came across Avnet github repository that hosts all the code base. I generated the example design for minized.

anushyab@vm_test:/work/avnet-git/hdl/scripts$ vivado -mode batch -source make_minized_sbc_base.tcl -notrace -tclargs minized_sbc base -nolog -nojournal

****** Vivado v2021.2 (64-bit)
  **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source make_minized_sbc_base.tcl -notrace

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-                                                     -*
*-        Welcome to the Avnet Project Builder         -*
*-                                                     -*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Selected 
 BDF path /work/avnet-git/bdf
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


Creating projects Folder

+------------------+------------------------------------+
| Setting          |     Configuration                  |
+------------------+------------------------------------+
| Board            |     minized_sbc                    |
+------------------+------------------------------------+
| Project          |     base                           |
+------------------+------------------------------------+
| SDK              |     no                             |
+------------------+------------------------------------+
| No Close Project |     yes                            |
+------------------+------------------------------------+
| Device           |     zynq                           |
+------------------+------------------------------------+



*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Vivado version 2021.2 acceptable, 
continuing...
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*




*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Selected Board and Project as:
 minized_sbc and base
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*




*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Not Requesting Tag
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


 Setting Up Project minized_sbc_base...

***** Creating Vivado project...
create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2721.602 ; gain = 8.961 ; free physical = 9017 ; free virtual = 14846

***** Setting synthesis language for project to VHDL...

***** Importing constraints file(s)...

***** Assigning Vivado project board_part property to minized...

***** Generating IP...

***** Updating Vivado to include IP folder
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/work/avnet-git/hdl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/xilinx/Vivado/2021.2/Vivado/2021.2/data/ip'.

***** Creating block design...
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
INFO: [BD 41-2613] The output directory /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base for minized_sbc_base cannot be found.
***** Adding RTL source Files to design...

***** Adding custom RTL IP blocks to block design...
Making wireless_mgr instance wireless_mgr_0 ...
INFO: [IP_Flow 19-5107] Inferred bus interface 'SDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'WL_SDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-5661] Bus Interface 'SDIO_CLK' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-5661] Bus Interface 'WL_SDIO_CLK' does not have any bus interfaces associated with it.
CRITICAL WARNING: [IP_Flow 19-4751] Bus Interface 'WL_SDIO_CLK': FREQ_HZ bus parameter is missing for output clock interface.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/work/avnet-git/hdl/ip'.
Making led_mgr instance led_mgr_0 ...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/work/avnet-git/hdl/ip'.
Making microphone_mgr instance microphone_mgr_0 ...
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_in' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_in' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn_in' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn_in' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AUDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AUDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-4728] Bus Interface 'clk_in': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn_in'.
INFO: [IP_Flow 19-4728] Bus Interface 'clk_in': Added interface parameter 'FREQ_HZ' with value '160000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'AUDIO_CLK': Added interface parameter 'FREQ_HZ' with value '2500000'.
INFO: [IP_Flow 19-7067] Note that bus interface 'clk_in' has a fixed FREQ_HZ of '160000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'clk_in' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-7067] Note that bus interface 'AUDIO_CLK' has a fixed FREQ_HZ of '2500000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'AUDIO_CLK' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/work/avnet-git/hdl/ip'.

***** Adding processing system presets from board definition...
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 

***** Adding defined IP blocks to block design...
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Device 21-403] Loading part xc7z007sclg225-1
create_bd_cell: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2798.391 ; gain = 0.000 ; free physical = 8550 ; free virtual = 14422
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKFBOUT_MULT_F' from '10.000' to '20.000' has been ignored for IP 'clk_wiz_0'
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/xin> is being overridden by the user with net <ps7_FCLK_CLK1>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_0/gpio_io_o> is being overridden by the user with net <axi_gpio_0_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_0/gpio2_io_o> is being overridden by the user with net <axi_gpio_0_gpio2_io_o>. This pin will not be connected as a part of interface connection <GPIO2>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_2/gpio_io_t> is being overridden by the user with net <axi_gpio_2_gpio_io_t>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_2/gpio_io_o> is being overridden by the user with net <axi_gpio_2_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_2/gpio_io_i> is being overridden by the user with net <led_mgr_0_GPIO_to_Zynq>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO1_CDN> is being overridden by the user with net <xlconstant_1_dout>. This pin will not be connected as a part of interface connection <SDIO_1>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO1_WP> is being overridden by the user with net <xlconstant_1_dout>. This pin will not be connected as a part of interface connection <SDIO_1>.
WARNING: [BD 41-1306] The connection to interface pin </axi_intc_0/irq> is being overridden by the user with net <axi_intc_0_irq>. This pin will not be connected as a part of interface connection <interrupt>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CLK> is being overridden by the user with net <ps7_SDIO0_CLK>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CLK_FB> is being overridden by the user with net <wireless_mgr_0_SDIO_CLK_FB>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CMD_O> is being overridden by the user with net <ps7_SDIO0_CMD_O>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CMD_I> is being overridden by the user with net <wireless_mgr_0_SDIO_CMD_to_Zynq>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CMD_T> is being overridden by the user with net <ps7_SDIO0_CMD_T>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_DATA_O> is being overridden by the user with net <ps7_SDIO0_DATA_O>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_DATA_I> is being overridden by the user with net <wireless_mgr_0_SDIO_DATA_to_Zynq>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_DATA_T> is being overridden by the user with net <ps7_SDIO0_DATA_T>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_WP> is being overridden by the user with net <wireless_mgr_0_SDIO_WP>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CDN> is being overridden by the user with net <wireless_mgr_0_SDIO_CDN>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/GPIO_O> is being overridden by the user with net <ps7_GPIO_O>. This pin will not be connected as a part of interface connection <GPIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/GPIO_I> is being overridden by the user with net <wireless_mgr_0_GPIO_to_Zynq>. This pin will not be connected as a part of interface connection <GPIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/GPIO_T> is being overridden by the user with net <ps7_GPIO_T>. This pin will not be connected as a part of interface connection <GPIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/sout> is being overridden by the user with net <bluetooth_uart_sout>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/sin> is being overridden by the user with net <wireless_mgr_0_ZYNQ_UART_RX>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/rtsn> is being overridden by the user with net <bluetooth_uart_rtsn>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/ctsn> is being overridden by the user with net <wireless_mgr_0_ZYNQ_UART_CTS>. This pin will not be connected as a part of interface connection <UART>.
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 

***** Assigning peripheral addresses...
Slave segment '/axi_gpio_0/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4120_0000 [ 64K ]>.
Slave segment '/axi_gpio_1/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4121_0000 [ 64K ]>.
Slave segment '/axi_gpio_2/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4122_0000 [ 64K ]>.
Slave segment '/axi_iic_0/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4160_0000 [ 64K ]>.
Slave segment '/axi_intc_0/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4180_0000 [ 64K ]>.
Slave segment '/bluetooth_uart/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x43C0_0000 [ 64K ]>.
Slave segment '/xadc_wiz_0/s_axi_lite/Reg' is being assigned into address space '/ps7/Data' at <0x43C1_0000 [ 64K ]>.

***** Validating the block design...
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-1348] Reset pin /microphone_mgr_0/resetn_in (associated clock /microphone_mgr_0/clk_in) is connected to asynchronous reset source /ps7/FCLK_RESET2_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ps7/FCLK_CLK2.
WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/axi_intc_0/intr


***** Validating IP licenses...
License Validation = Successful

***** Creating top level HDL wrapper for design and adding to project...
INFO: [BD 41-1662] The design 'minized_sbc_base.bd' is already validated. Therefore parameter propagation will not be re-run.
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/axi_intc_0/intr

Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/synth/minized_sbc_base.vhd
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/sim/minized_sbc_base.vhd
VHDL Output written to : /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd
INFO: [Project 1-1716] Could not find the wrapper file /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd, checking in project .gen location instead.
INFO: [Vivado 12-12390] Found file /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd, adding it to Project

***** Adding Vitis directves to design...
update_compile_order: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2894.434 ; gain = 96.043 ; free physical = 8469 ; free virtual = 14367
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'

***** Building binary...
update_compile_order: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2934.449 ; gain = 0.000 ; free physical = 8469 ; free virtual = 14367
Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-1348] Reset pin /microphone_mgr_0/resetn_in (associated clock /microphone_mgr_0/clk_in) is connected to asynchronous reset source /ps7/FCLK_RESET2_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ps7/FCLK_CLK2.
WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/axi_intc_0/intr

Wrote  : </work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/synth/minized_sbc_base.vhd
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/sim/minized_sbc_base.vhd
VHDL Output written to : /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block wireless_mgr_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block led_mgr_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block microphone_mgr_0 .
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block bluetooth_uart .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconstant_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc_0 .
false
INFO: [IP_Flow 19-3422] Upgraded pdm_filt_fir_compiler_v7_2_i0 (FIR Compiler 7.2) from revision 8 to revision 17
false
INFO: [IP_Flow 19-3422] Upgraded pdm_filt_fir_compiler_v7_2_i1 (FIR Compiler 7.2) from revision 8 to revision 17
INFO: [BD 41-1029] Generation completed for the IP Integrator block pdm_filt_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_100MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_142MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_166MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_200MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_41MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_50MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_auto_pc_0/minized_sbc_base_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_axi_periph/s00_couplers/auto_pc .
Exporting to file /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hw_handoff/minized_sbc_base.hwh
Generated Hardware Definition File /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/synth/minized_sbc_base.hwdef
[Wed Jul 26 14:23:52 2023] Launched minized_sbc_base_xbar_0_synth_1, minized_sbc_base_ps7_0_synth_1, minized_sbc_base_microphone_mgr_0_0_synth_1, minized_sbc_base_led_mgr_0_0_synth_1, minized_sbc_base_wireless_mgr_0_0_synth_1, minized_sbc_base_xadc_wiz_0_0_synth_1, minized_sbc_base_pdm_filt_0_0_synth_1, minized_sbc_base_axi_intc_0_0_synth_1, minized_sbc_base_axi_gpio_0_0_synth_1, minized_sbc_base_axi_gpio_1_0_synth_1, minized_sbc_base_axi_gpio_2_0_synth_1, minized_sbc_base_axi_iic_0_0_synth_1, minized_sbc_base_axi_uart16550_0_0_synth_1, minized_sbc_base_auto_pc_0_synth_1, minized_sbc_base_proc_sys_reset_100MHz_0_synth_1, minized_sbc_base_proc_sys_reset_142MHz_0_synth_1, minized_sbc_base_proc_sys_reset_166MHz_0_synth_1, minized_sbc_base_proc_sys_reset_200MHz_0_synth_1, minized_sbc_base_proc_sys_reset_41MHz_0_synth_1, minized_sbc_base_proc_sys_reset_50MHz_0_synth_1, minized_sbc_base_clk_wiz_0_0_synth_1, synth_1...
Run output will be captured here:
minized_sbc_base_xbar_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_xbar_0_synth_1/runme.log
minized_sbc_base_ps7_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_ps7_0_synth_1/runme.log
minized_sbc_base_microphone_mgr_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_microphone_mgr_0_0_synth_1/runme.log
minized_sbc_base_led_mgr_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_led_mgr_0_0_synth_1/runme.log
minized_sbc_base_wireless_mgr_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_wireless_mgr_0_0_synth_1/runme.log
minized_sbc_base_xadc_wiz_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_xadc_wiz_0_0_synth_1/runme.log
minized_sbc_base_pdm_filt_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_pdm_filt_0_0_synth_1/runme.log
minized_sbc_base_axi_intc_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_axi_intc_0_0_synth_1/runme.log
minized_sbc_base_axi_gpio_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_axi_gpio_0_0_synth_1/runme.log
minized_sbc_base_axi_gpio_1_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_axi_gpio_1_0_synth_1/runme.log
minized_sbc_base_axi_gpio_2_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_axi_gpio_2_0_synth_1/runme.log
minized_sbc_base_axi_iic_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_axi_iic_0_0_synth_1/runme.log
minized_sbc_base_axi_uart16550_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_axi_uart16550_0_0_synth_1/runme.log
minized_sbc_base_auto_pc_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_auto_pc_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_100MHz_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_100MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_142MHz_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_142MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_166MHz_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_166MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_200MHz_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_200MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_41MHz_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_41MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_50MHz_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_50MHz_0_synth_1/runme.log
minized_sbc_base_clk_wiz_0_0_synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/minized_sbc_base_clk_wiz_0_0_synth_1/runme.log
synth_1: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/synth_1/runme.log
[Wed Jul 26 14:23:52 2023] Launched impl_1...
Run output will be captured here: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:01:13 ; elapsed = 00:01:05 . Memory (MB): peak = 3046.512 ; gain = 112.062 ; free physical = 8291 ; free virtual = 14279

***** Wait for bitstream to be written...
[Wed Jul 26 14:23:52 2023] Waiting for impl_1 to finish...

*** Running vivado
    with args -log minized_sbc_base_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source minized_sbc_base_wrapper.tcl -notrace


****** Vivado v2021.2 (64-bit)
  **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source minized_sbc_base_wrapper.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2721.574 ; gain = 7.961 ; free physical = 11853 ; free virtual = 14618
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/work/avnet-git/hdl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/xilinx/Vivado/2021.2/Vivado/2021.2/data/ip'.
add_files: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2905.656 ; gain = 184.082 ; free physical = 11781 ; free virtual = 14546
Command: link_design -top minized_sbc_base_wrapper -part xc7z007sclg225-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z007sclg225-1
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0.dcp' for cell 'minized_sbc_base_i/axi_gpio_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0.dcp' for cell 'minized_sbc_base_i/axi_gpio_1'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0.dcp' for cell 'minized_sbc_base_i/axi_gpio_2'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_iic_0_0/minized_sbc_base_axi_iic_0_0.dcp' for cell 'minized_sbc_base_i/axi_iic_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0.dcp' for cell 'minized_sbc_base_i/axi_intc_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0.dcp' for cell 'minized_sbc_base_i/bluetooth_uart'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.dcp' for cell 'minized_sbc_base_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_led_mgr_0_0/minized_sbc_base_led_mgr_0_0.dcp' for cell 'minized_sbc_base_i/led_mgr_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_microphone_mgr_0_0/minized_sbc_base_microphone_mgr_0_0.dcp' for cell 'minized_sbc_base_i/microphone_mgr_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/minized_sbc_base_pdm_filt_0_0.dcp' for cell 'minized_sbc_base_i/pdm_filt_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_100MHz'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_142MHz'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_166MHz'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_200MHz'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_41MHz'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_50MHz'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.dcp' for cell 'minized_sbc_base_i/ps7'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_wireless_mgr_0_0/minized_sbc_base_wireless_mgr_0_0.dcp' for cell 'minized_sbc_base_i/wireless_mgr_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xadc_wiz_0_0/minized_sbc_base_xadc_wiz_0_0.dcp' for cell 'minized_sbc_base_i/xadc_wiz_0'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xbar_0/minized_sbc_base_xbar_0.dcp' for cell 'minized_sbc_base_i/ps7_axi_periph/xbar'
INFO: [Project 1-454] Reading design checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_auto_pc_0/minized_sbc_base_auto_pc_0.dcp' for cell 'minized_sbc_base_i/ps7_axi_periph/s00_couplers/auto_pc'
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2905.656 ; gain = 0.000 ; free physical = 11463 ; free virtual = 14229
INFO: [Netlist 29-17] Analyzing 90 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.2
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. minized_sbc_base_i/clk_wiz_0/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xadc_wiz_0_0/minized_sbc_base_xadc_wiz_0_0.xdc] for cell 'minized_sbc_base_i/xadc_wiz_0/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xadc_wiz_0_0/minized_sbc_base_xadc_wiz_0_0.xdc] for cell 'minized_sbc_base_i/xadc_wiz_0/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc:57]
get_clocks: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2908.441 ; gain = 2.785 ; free physical = 10954 ; free virtual = 13740
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0_board.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0_board.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc] for cell 'minized_sbc_base_i/ps7/inst'
WARNING: [Vivado 12-2489] -input_jitter contains time 0.618750 which will be rounded to 0.619 to ensure it is an integer multiple of 1 picosecond [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc:24]
WARNING: [Vivado 12-2489] -input_jitter contains time 0.187500 which will be rounded to 0.188 to ensure it is an integer multiple of 1 picosecond [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc:27]
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc] for cell 'minized_sbc_base_i/ps7/inst'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/constrs/pdm_filt.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/constrs/pdm_filt.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i0/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2/pdm_filt_fir_compiler_v7_2_i0_instance/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i0/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2/pdm_filt_fir_compiler_v7_2_i0_instance/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i1/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2_1/pdm_filt_fir_compiler_v7_2_i1_instance/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i1/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2_1/pdm_filt_fir_compiler_v7_2_i1_instance/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0_board.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0_board.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_iic_0_0/minized_sbc_base_axi_iic_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_iic_0/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_iic_0_0/minized_sbc_base_axi_iic_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_iic_0/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc]
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT0'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:70]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:70]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT0'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:71]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:71]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT1'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:74]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:74]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT1'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:75]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:75]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT2'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:78]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:78]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT2'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:79]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:79]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT3'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:82]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:82]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT3'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:83]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:83]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT4'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:86]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:86]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT4'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT5'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:90]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:90]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT5'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:91]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:91]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT6'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:94]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:94]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT6'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:95]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:95]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT7'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:98]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:98]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT7'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:99]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:99]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT8'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:105]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:105]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT8'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:106]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:106]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT9'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:109]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:109]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT9'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:110]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:110]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT10'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:113]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:113]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT10'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:114]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:114]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT11'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:117]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:117]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT11'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:118]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:118]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT12'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:121]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:121]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT12'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:122]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:122]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT13'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT13'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR0'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:132]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:132]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR0'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:133]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:133]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR1'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:136]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:136]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR1'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:137]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:137]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR2'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:140]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:140]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR2'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:141]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:141]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_sda_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:179]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:179]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_sda_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:180]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:180]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_scl_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:182]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:182]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_scl_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:183]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:183]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_sda_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:186]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:186]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_sda_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:187]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:187]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_scl_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:189]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:189]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_scl_io'. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:190]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:190]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc]
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/bitstream_compression_enable.xdc]
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/constrs_1/imports/base/bitstream_compression_enable.xdc]
Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0_clocks.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
Finished Parsing XDC File [/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0_clocks.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3092.527 ; gain = 0.000 ; free physical = 10951 ; free virtual = 13739
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 11 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 7 instances
  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances

33 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 3092.527 ; gain = 186.871 ; free physical = 10951 ; free virtual = 13739
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3092.527 ; gain = 0.000 ; free physical = 10940 ; free virtual = 13727

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1968b9ea4

Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3092.527 ; gain = 0.000 ; free physical = 10939 ; free virtual = 13727

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-1287] Pulled Inverter minized_sbc_base_i/bluetooth_uart/U0/XUART_I_1/UART16550_I_1/rx16550_1/sin_d1_i_1 into driver instance minized_sbc_base_i/bluetooth_uart/U0/XUART_I_1/UART16550_I_1/rx16550_1/baudoutn_INST_0, which resulted in an inversion of 20 pins
INFO: [Opt 31-1287] Pulled Inverter minized_sbc_base_i/wireless_mgr_0/BT_REG_ON_INST_0_i_1 into driver instance minized_sbc_base_i/ps7/inst/GPIO_T[0]_INST_0, which resulted in an inversion of 1 pins
INFO: [Opt 31-1287] Pulled Inverter minized_sbc_base_i/wireless_mgr_0/WL_REG_ON_INST_0_i_1 into driver instance minized_sbc_base_i/ps7/inst/GPIO_T[2]_INST_0, which resulted in an inversion of 1 pins
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 15981e565

Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3188.410 ; gain = 0.004 ; free physical = 10708 ; free virtual = 13496
INFO: [Opt 31-389] Phase Retarget created 109 cells and removed 181 cells
INFO: [Opt 31-1021] In phase Retarget, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 181a9467e

Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3188.410 ; gain = 0.004 ; free physical = 10708 ; free virtual = 13496
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 14 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 21e9c3249

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3188.410 ; gain = 0.004 ; free physical = 10706 ; free virtual = 13494
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1508 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 21e9c3249

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3188.410 ; gain = 0.004 ; free physical = 10706 ; free virtual = 13494
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 21e9c3249

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3188.410 ; gain = 0.004 ; free physical = 10706 ; free virtual = 13494
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 21e9c3249

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3188.410 ; gain = 0.004 ; free physical = 10706 ; free virtual = 13494
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |             109  |             181  |                                              2  |
|  Constant propagation         |               0  |              14  |                                              0  |
|  Sweep                        |               0  |            1508  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3188.410 ; gain = 0.000 ; free physical = 10706 ; free virtual = 13494
Ending Logic Optimization Task | Checksum: 176da9e27

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3188.410 ; gain = 0.004 ; free physical = 10706 ; free virtual = 13494

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 4 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 8
Ending PowerOpt Patch Enables Task | Checksum: 176da9e27

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10691 ; free virtual = 13481
Ending Power Optimization Task | Checksum: 176da9e27

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3513.609 ; gain = 325.199 ; free physical = 10697 ; free virtual = 13487

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 176da9e27

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10697 ; free virtual = 13487

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10697 ; free virtual = 13487
Ending Netlist Obfuscation Task | Checksum: 176da9e27

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10697 ; free virtual = 13487
INFO: [Common 17-83] Releasing license: Implementation
59 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3513.609 ; gain = 421.082 ; free physical = 10698 ; free virtual = 13487
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10691 ; free virtual = 13484
INFO: [Common 17-1381] The checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file minized_sbc_base_wrapper_drc_opted.rpt -pb minized_sbc_base_wrapper_drc_opted.pb -rpx minized_sbc_base_wrapper_drc_opted.rpx
Command: report_drc -file minized_sbc_base_wrapper_drc_opted.rpt -pb minized_sbc_base_wrapper_drc_opted.pb -rpx minized_sbc_base_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13447
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 90abcb8f

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13447
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13447

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15b6ae6af

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10667 ; free virtual = 13459

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1ebebc1a0

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10670 ; free virtual = 13462

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1ebebc1a0

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10670 ; free virtual = 13462
Phase 1 Placer Initialization | Checksum: 1ebebc1a0

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10670 ; free virtual = 13462

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 218340519

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10666 ; free virtual = 13458

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e0ca8e27

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10668 ; free virtual = 13461

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e0ca8e27

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10668 ; free virtual = 13461

Phase 2.4 Global Placement Core

Phase 2.4.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 143 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 57 nets or LUTs. Breaked 0 LUT, combined 57 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10657 ; free virtual = 13449

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             57  |                    57  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             57  |                    57  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.1 Physical Synthesis In Placer | Checksum: 184aea007

Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10656 ; free virtual = 13448
Phase 2.4 Global Placement Core | Checksum: 13c158dfb

Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13448
Phase 2 Global Placement | Checksum: 13c158dfb

Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10656 ; free virtual = 13448

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 10a39f931

Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10656 ; free virtual = 13449

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 215711dad

Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13447

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2617320a5

Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13447

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1991b734d

Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13447

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 10fd78f2a

Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10654 ; free virtual = 13447

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 148d859df

Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10654 ; free virtual = 13447

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1b8856812

Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10654 ; free virtual = 13447
Phase 3 Detail Placement | Checksum: 1b8856812

Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10654 ; free virtual = 13447

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 14871c52f

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=3.043 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 191ac000d

Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10652 ; free virtual = 13445
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 1ae42d33c

Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.26 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10652 ; free virtual = 13445
Phase 4.1.1.1 BUFG Insertion | Checksum: 14871c52f

Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10652 ; free virtual = 13445

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=3.043. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1403d895c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10652 ; free virtual = 13445

Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10652 ; free virtual = 13445
Phase 4.1 Post Commit Optimization | Checksum: 1403d895c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10652 ; free virtual = 13445

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1403d895c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10653 ; free virtual = 13446

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                1x1|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1403d895c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10653 ; free virtual = 13445
Phase 4.3 Placer Reporting | Checksum: 1403d895c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10653 ; free virtual = 13445

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10653 ; free virtual = 13445

Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10653 ; free virtual = 13445
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1257b8a09

Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10653 ; free virtual = 13445
Ending Placer Task | Checksum: ad520151

Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10653 ; free virtual = 13445
INFO: [Common 17-83] Releasing license: Implementation
94 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:12 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10658 ; free virtual = 13451
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10642 ; free virtual = 13442
INFO: [Common 17-1381] The checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file minized_sbc_base_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10649 ; free virtual = 13445
INFO: [runtcl-4] Executing : report_utilization -file minized_sbc_base_wrapper_utilization_placed.rpt -pb minized_sbc_base_wrapper_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file minized_sbc_base_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10655 ; free virtual = 13450
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
104 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10623 ; free virtual = 13426
INFO: [Common 17-1381] The checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 9cf497ba ConstDB: 0 ShapeSum: 105d6997 RouteDB: 0
Post Restoration Checksum: NetGraph: d10f3957 NumContArr: 560b13a7 Constraints: 0 Timing: 0
Phase 1 Build RT Design | Checksum: 1271a4cfe

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10568 ; free virtual = 13366

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 1271a4cfe

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10568 ; free virtual = 13367

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 1271a4cfe

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10536 ; free virtual = 13334

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 1271a4cfe

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10536 ; free virtual = 13334
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1253f3d51

Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10526 ; free virtual = 13324
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.943  | TNS=0.000  | WHS=-0.356 | THS=-78.220|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00337838 %
  Global Horizontal Routing Utilization  = 0.00689338 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 3898
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3897
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 811a6612

Time (s): cpu = 00:00:20 ; elapsed = 00:00:13 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10523 ; free virtual = 13321

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 811a6612

Time (s): cpu = 00:00:20 ; elapsed = 00:00:13 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10523 ; free virtual = 13321
Phase 3 Initial Routing | Checksum: 1813dec2e

Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10524 ; free virtual = 13322

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 331
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.313  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 22efc2ab8

Time (s): cpu = 00:00:26 ; elapsed = 00:00:16 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10519 ; free virtual = 13318

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.313  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 17f712526

Time (s): cpu = 00:00:26 ; elapsed = 00:00:16 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317
Phase 4 Rip-up And Reroute | Checksum: 17f712526

Time (s): cpu = 00:00:26 ; elapsed = 00:00:16 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 17f712526

Time (s): cpu = 00:00:27 ; elapsed = 00:00:16 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 17f712526

Time (s): cpu = 00:00:27 ; elapsed = 00:00:16 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317
Phase 5 Delay and Skew Optimization | Checksum: 17f712526

Time (s): cpu = 00:00:27 ; elapsed = 00:00:16 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1e34c79a0

Time (s): cpu = 00:00:28 ; elapsed = 00:00:17 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.428  | TNS=0.000  | WHS=0.025  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1bdb50fff

Time (s): cpu = 00:00:28 ; elapsed = 00:00:17 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317
Phase 6 Post Hold Fix | Checksum: 1bdb50fff

Time (s): cpu = 00:00:28 ; elapsed = 00:00:17 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.64062 %
  Global Horizontal Routing Utilization  = 2.19118 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 1e376318e

Time (s): cpu = 00:00:28 ; elapsed = 00:00:17 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13317

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1e376318e

Time (s): cpu = 00:00:28 ; elapsed = 00:00:17 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10517 ; free virtual = 13316

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 205f1a73d

Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10518 ; free virtual = 13316

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.426  | TNS=0.000  | WHS=0.024  | THS=0.000  |

Phase 10 Post Router Timing | Checksum: 1f74cfdad

Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10517 ; free virtual = 13316
INFO: [Route 35-61] The design met the timing requirement.
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10583 ; free virtual = 13382

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
120 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:20 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10584 ; free virtual = 13382
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3513.609 ; gain = 0.000 ; free physical = 10569 ; free virtual = 13376
INFO: [Common 17-1381] The checkpoint '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file minized_sbc_base_wrapper_drc_routed.rpt -pb minized_sbc_base_wrapper_drc_routed.pb -rpx minized_sbc_base_wrapper_drc_routed.rpx
Command: report_drc -file minized_sbc_base_wrapper_drc_routed.rpt -pb minized_sbc_base_wrapper_drc_routed.pb -rpx minized_sbc_base_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file minized_sbc_base_wrapper_methodology_drc_routed.rpt -pb minized_sbc_base_wrapper_methodology_drc_routed.pb -rpx minized_sbc_base_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file minized_sbc_base_wrapper_methodology_drc_routed.rpt -pb minized_sbc_base_wrapper_methodology_drc_routed.pb -rpx minized_sbc_base_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 8 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file minized_sbc_base_wrapper_power_routed.rpt -pb minized_sbc_base_wrapper_power_summary_routed.pb -rpx minized_sbc_base_wrapper_power_routed.rpx
Command: report_power -file minized_sbc_base_wrapper_power_routed.rpt -pb minized_sbc_base_wrapper_power_summary_routed.pb -rpx minized_sbc_base_wrapper_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
132 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file minized_sbc_base_wrapper_route_status.rpt -pb minized_sbc_base_wrapper_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file minized_sbc_base_wrapper_timing_summary_routed.rpt -pb minized_sbc_base_wrapper_timing_summary_routed.pb -rpx minized_sbc_base_wrapper_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file minized_sbc_base_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file minized_sbc_base_wrapper_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file minized_sbc_base_wrapper_bus_skew_routed.rpt -pb minized_sbc_base_wrapper_bus_skew_routed.pb -rpx minized_sbc_base_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Command: write_bitstream -force minized_sbc_base_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 10167136 bits.
Writing bitstream ./minized_sbc_base_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 3659.105 ; gain = 145.496 ; free physical = 10544 ; free virtual = 13354
INFO: [Common 17-206] Exiting Vivado at Wed Jul 26 14:31:39 2023...
[Wed Jul 26 14:31:45 2023] impl_1 finished
wait_on_runs: Time (s): cpu = 00:24:45 ; elapsed = 00:07:53 . Memory (MB): peak = 3046.512 ; gain = 0.000 ; free physical = 12070 ; free virtual = 14899

***** Open the implemented design...
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3046.512 ; gain = 0.000 ; free physical = 11994 ; free virtual = 14865
INFO: [Netlist 29-17] Analyzing 90 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.2
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:01 . Memory (MB): peak = 3124.332 ; gain = 5.938 ; free physical = 11360 ; free virtual = 14341
Restored from archive | CPU: 0.820000 secs | Memory: 5.988350 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:01 . Memory (MB): peak = 3124.332 ; gain = 5.938 ; free physical = 11360 ; free virtual = 14341
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3340.473 ; gain = 0.000 ; free physical = 11353 ; free virtual = 14335
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 11 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 7 instances
  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances

open_run: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 3340.473 ; gain = 293.961 ; free physical = 11353 ; free virtual = 14336

***** Write and validate the design archive...
WARNING: [Project 1-971] Hardware Platform (Shell) metadata attributes vendor, board, name, version will be populated from project properties platform.vendor (em.avnet.com), platform.board_id (minized_sbc_base), platform.name (minized_sbc_base) and platform.version (1.0). The values from PFM_NAME property (em.avnet.com:av:minized_sbc_base:1.0) on the BD will be over-ridden.
INFO: [Vivado 12-4895] Creating Hardware Platform: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.xsa ...
WARNING: [BD 41-2589] Platform should have atleast one axi memory mapped master interface. Enable a master AXI interface as platform AXI_PORT.
INFO: [Project 1-1042] Successfully generated hpfm file
INFO: [Vivado 12-12466] The Hardware Platform can be used for Hardware and Hardware Emulation
INFO: [Vivado 12-4896] Successfully created Hardware Platform: /work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.xsa
write_hw_platform: Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 3340.473 ; gain = 0.000 ; free physical = 11119 ; free virtual = 14290
INFO: [Hsi 55-2053] elapsed time for repository (/eda/xilinx/Vivado/2021.2/Vivado/2021.2/data/embeddedsw) loading 0 seconds
INFO: [Vivado 12-12082] Found metadata file: xsa.json
INFO: [Vivado 12-6078] Validating platform properties...
INFO: [Vivado 12-6079] Validating unified platform...
INFO: [Vivado 12-6073] Validating 'pre_synth' platform state...
INFO: [Vivado 12-6077] Validating platform files...
INFO: [Vivado 12-6067] Found file 'minized_sbc_base.bit' of type 'FULL_BIT' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'minized_sbc_base.hpfm' of type 'HPFM' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'prj/rebuild.tcl' of type 'REBUILD_TCL' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'prj/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd' of type 'TOP_BD' in the Hardware Platform.
INFO: [Vivado 12-6066] Finished running validate_hw_platform for file: '/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.xsa'

***** Close the implemented design...


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 Generating Binary...
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Found End of Bitstream Creation...


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 Closing Project...
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close_project: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:06 . Memory (MB): peak = 3340.473 ; gain = 0.000 ; free physical = 11219 ; free virtual = 14472


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Your Build Took
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or a total of:

days [0]
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to complete

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INFO: [Common 17-206] Exiting Vivado at Wed Jul 26 14:32:31 2023...
anushyab@vm_test:/work/avnet-git/hdl/scripts$ 

2. Exploring the block design:

After the design was build, I opened the block design and explored further. This is a good level of abstraction for a beginner like me as I didnot want to delve directly into code. Abstraction definitely helps.

I tried to trace the path of the audio data in the block design as highlighted below.

I could see the audio data coming from from the input to the micorphone_mgr_0 module, it gets converted to AUDIO_PDM and is fed back to pdm_filt_0 module.
The result of the pdm_filt_0 is a 16 bit bus signal that goes to the AUDIO_RAW input of the led_mgr_0 module. This module then is connected to the PL_LED's.
The above flow gives an intuition for what is happening in the design. The audio data from the microphone is pulse density modulated, then filtered and the raw input is then processed by a module and triggers the LED based on the specific bits beging high (Mostly MSB's I expect).

3. Tracking the source files from the block design.

The last step of the process is to find the files corresponding to the block design. I did this by exploring the build directories. Finally managed to locate the relevant files as shown below.

anushyab@vm_test:/work/avnet-git/hdl/projects/minized_sbc_base_2021_2/minized_sbc_base.srcs/sources_1$ tree -L 3

It is always good to have a working system. So that we can reverse engineer the code to learn how things are working and does it match our understanding.This is especiallly useful as I aim to use the interfaces to do some image processing example.