Introduction

The MiniZed is a single ARM Cortex®-A9 processor mated with 28nm Artix 7 based programmable logic, representing a low cost entry point to the scalable Zynq 7000 platform.  It can run Linux, RTOS and programmable logic which is called FPGA. MiniZed is similar to Arty series FPGA platform, which contains Arduino header for extensible embedded system design. There are 2 PMOD ports for extra PMOD compatible daughter cards.

The center piece of MiniZed is Zynq 7000S device.  This blog will focus on Block RAM(BRAM) and BRAM controller for the programmable logic implementation because MiniZed TTC Lab 5/6 implement the IPs as the homework as below:

I added AXI BRAM controller and BRAM generator from Vivado IP Catalog as below.

 Here is the BRAM information from AMD/Xilinx DS190 datasheet.

AXI BRAM Controller is a soft AMD IP core for use with Vivado standalone core in the Viado IP catalog. The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to local BRAM. The core supports both single and burst transactions to the BRAM and is optimized for performance.

BRAM Structure

The BRAM on Z-70007s is 36Kb RAM, which can store up to 36 Kbits of data and can be configured as either two independent 18Kb RAMs or one 36Kb RAM.  The architecture of Artix 7 series FPGA devices has flexible internal memory resources, which can be configured into a variety of different sizes. The common internal memory types on Artix 7 series FPGAs are BRAM, RAM and distributed RAM. OCM is one type of internal memory at PS side.

Z-70007s has up to 50 dual-port block RAMs, each capable of storing 36 Kb, 32 Kb of which is allocated to data storages, and in some memory configurations, an additional 4 Kb allocated to parity bits. Each BRAM has two completely independent ports that share nothing but the stored data. Each port can be configured as:

• 32Kx1
• 16Kx2
• 8Kx4
• 4Kx9 (or 8)
• 2K x 18 (or 16)
• 1K x 36 (or 32)
• 512 x 72 (or 64)

Here is the interface of true dual port BRAM block(TDPRAM) from AMD/Xilinx UG953.

Each BRAM can be divided into two completely independent 18 Kb block RAMs that can each be configured to any aspect ratio from 16K x 1 to 512 x 36. When a 36K block RAM is split into two independent block RAMs, each of the two independent block RAMs behaves exactly like a one 36 Kb block RAM, just half the size. Conversely, if the user requires larger memory arrays, two adjacent 36 Kb block RAMs can be configured like one cascaded 64K x 1 dual-port RAM without any additional logic.

BRAM is one of the popular internal memories for FPGA configuration since it is a FPGA macro on FPGA fabric die. The implementation snippet of one BRAM is presented here from Lab5 Vivado project.

The distributed RAM or Selected RAM is basically constructed from FPGA FIFO/LUT/MUX macros. One of example of FPGA FIFO macro on Z-70007s is as below:

In summary, BRAM is dedicated RAM with higher performance than distributed RAM on the same FPGA device.

BRAM Controller Structure

The AXI BRAM Controller core can be configured such that a single port to the BRAM block or both ports to the BRAM block are utilized in either an AXI4 or AXI4-Lite controller configuration. The AXI BRAM Controller IP can be configured with ECC functionality on the datapath with an available external ECC register set via a second AXI4-Lite control port connection. The concept structure of a general AXI BRAM control is copied from Xilinx pg078 as below.(From MiniZed TTC training document: Avnet_MiniZed_TTC_Lecture_Zynq_HW_2021.pdf)

In Lab 5, the AXI BRAM controller is configured as 64 bit BRAM data width for AXI4 protocol bus.

Here is the configuration of AXI BRAM controller in Lab 5:

AXI channel handshake basics from Avnet_MiniZed_TTC_Lecture_Zynq_HW_2021.pdf:

All AXI channels follow READY/VALID handshake rules: once valid is asserted, it cannot be reasserted until the corresponding ready is received; once valid is asserted, other signals driver by initiator must not change; READY can be withheld; valid must never be withheld (system may deadlock).

I presented the Vivado Lab ILA IP: AXI4 bus waveform from my homework of Lab5/6, for the demonstration of AXI4 channel handshake.

where AXI bus performs the data read from BRAM to DDR3 for data package is configured at 512 bytes length.

MiniZed TTC Lab5 and Lab6 Report

After I finished the general Vivado project creation instructed from Lab5, I added a Vivado Lab ILA block into the project. First select ILA IP from IP Catalog as below into BD canvas in Vivado:

The configuration of ILA IP is illustrated as below.

Here is my Lab5 Vivado project:

Following the instruction of Lab 6, I created BRAM test API at Vitis 2021.1:

Do you notice that I modified line 26 at dma_test.c?

#define LENGTH 4096    // bug fix for Lab 6

There is a bug at the original dma_test.c:

#define LENGTH 8192   // bug for Lab 6

The address map of MiniZed for axi_bram_ctrl_0 is 8K, which making the BRAM block source address at 8192 is out of the boundary of this controller.

After I download BRAM_test.elf into MiniZed, I can run bram2DDR test without hanging AXI4 bus any more.

Here are the testing snapshots of UART from MiniZed on Lab 6 for 1024 bytes transfer.

  Case 01: BRAM to BRAM:

Case 02: BRAM to DDR

Case 03: DDR to DDR: